TW202329327A - 半導體高壓元件及其製作方法 - Google Patents

半導體高壓元件及其製作方法 Download PDF

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TW202329327A
TW202329327A TW111130394A TW111130394A TW202329327A TW 202329327 A TW202329327 A TW 202329327A TW 111130394 A TW111130394 A TW 111130394A TW 111130394 A TW111130394 A TW 111130394A TW 202329327 A TW202329327 A TW 202329327A
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dielectric layer
gate dielectric
buried gate
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李信宏
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聯華電子股份有限公司
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Abstract

一種半導體高壓元件，包含半導體基底；高壓井，設置在半導體基底中；漂移區，設置在高壓井中；凹陷通道區，鄰近漂移區；重摻雜汲極區，設置在漂移區中並與凹陷通道區間隔開；隔離結構，設置在凹陷通道區與漂移區中的重摻雜汲極區之間；埋入閘介電層，設置在凹陷通道區上，其中埋入閘介電層的頂面低於重摻雜汲極區的頂面；以及閘極，設置在埋入閘介電層上。

Description

半導體高壓元件及其製作方法
本發明基本涉及一種半導體元件，更具體地，涉及一種場漂移金屬氧化物半導體(field drift metal oxide semiconductor，FDMOS)元件。
由於金屬氧化物半導體（MOS）電晶體的功耗比傳統電晶體低，並且可以高度集成，因此被廣泛應用於半導體產業。當輸入適當的電壓時，MOS電晶體可以用作開關來控制通過元件的電流。在高壓電路中，例如電子設備的輸入和輸出端子，場漂移金屬氧化物半導體（FDMOS）電晶體因其能夠承受重負載而被普遍使用。
然而，現有技術的FDMOS元件有幾個缺點。例如，傳統的FDMOS元件可能會有寄生場元件（parasitic field device），當操作電壓超過 10V 左右時會導通，導致電路模型不穩定。隨著集成電路的發展，改進場漂移金屬氧化物半導體（FDMOS）電晶體是一個越來越重要的問題。
本發明的主要目的在提供一種改良的半導體高壓元件，以解決上述現有技術的不足和缺點。
本發明一方面提供一種半導體高壓元件，包含：一半導體基底，具有第一導電型；一高壓井，具有所述第一導電型，設置在所述半導體基底中；一漂移區，具有一第二導電型，設置在所述高壓井中；一凹陷通道區，鄰近所述漂移區；一重摻雜汲極區，具有所述第二導電型，設置在所述漂移區中並與所述凹陷通道區間隔開；一隔離結構，設置在所述凹陷通道區與所述漂移區中的所述重摻雜汲極區之間；一埋入閘介電層，設置在所述凹陷通道區上，其中所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面；以及一閘極，設置在所述埋入閘介電層上。
根據本發明實施例，所述隔離結構具有鄰近所述凹陷通道區的第一厚度和鄰近所述重摻雜汲極區的第二厚度，其中所述第一厚度大於所述第二厚度。
根據本發明實施例，所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面下的深度等於所述第一厚度與所述第二厚度的差值。
根據本發明實施例，所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面下的深度約為500埃。
根據本發明實施例，所述隔離結構為淺溝絕緣結構。
根據本發明實施例，所述隔離結構與所述埋入閘介電層相連。
根據本發明實施例，所述漂移區與所述埋入閘介電層部分重疊。
根據本發明實施例，所述半導體高壓元件另包含：一環形擴散區，具有所述第一導電型，並且環繞所述漂移區、所述凹陷通道區和所述隔離結構。
根據本發明實施例，所述第一導電型是P型，所述第二導電型是N型。
根據本發明實施例，所述埋入閘介電層是高壓閘氧化層。
本發明另一方面提供一種製造半導體元件的方法，包含：提供具有第一導電型的半導體基底；在所述半導體基底中形成具有所述第一導電型的高壓井，並且在所述半導體基底中形成預先凹陷區；在所述高壓井中形成具有第二導電型的漂移區；形成與所述漂移區相鄰的凹陷通道區；在所述漂移區中形成與所述凹陷通道區間隔開的且具有第二導電型的重摻雜汲極區；在所述漂移區的所述凹陷通道區和所述重摻雜汲極區之間形成隔離結構，其中，所述隔離結構與所述預先凹陷區重疊；在所述凹陷通道區上形成埋入閘介電層，其中所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面；在所述埋入閘介電層上形成閘極。
根據本發明實施例，所述隔離結構具有鄰近所述凹陷通道區的第一厚度和鄰近所述重摻雜汲極區的第二厚度，且其中所述第一厚度大於所述第二厚度。
根據本發明實施例，所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面下的深度等於所述第一厚度與所述第二厚度的差值。
根據本發明實施例，所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面下的深度約為500埃。
根據本發明實施例，所述隔離結構為淺溝絕緣結構。
根據本發明實施例，所述隔離結構與所述埋入閘介電層相連。
根據本發明實施例，所述漂移區與所述埋入閘介電層部分重疊。
根據本發明實施例，所述方法另包含：在所述半導體基底中形成具有所述第一導電型的環形擴散區，其中所述環形擴散區環繞所述漂移區、所述凹陷通道區和所述隔離結構。
根據本發明實施例，所述第一導電型為P型，所述第二導電型為N型。
根據本發明實施例，所述埋入閘介電層為高壓閘氧化層。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。
當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
請參閱圖1至圖3，其中，圖1為根據本發明實施例所繪示的半導體高壓元件的佈局示意圖，圖2為沿著圖1中的切線I-I’（通道長度方向）所示的剖面示意圖，圖3為沿著圖1中的切線II-II’（通道寬度方向）所示的剖面示意圖。如圖1至圖3所示，半導體高壓元件1，例如，場漂移金屬氧化物半導體（FDMOS）電晶體，包含半導體基底100，例如，矽基底，具有第一導電型，例如，P型。在半導體基底100中，設置有高壓井110，具有第一導電型，例如，P型。根據本發明實施例，在高壓井110中設置有漂移區120，具有第二導電型，例如，N型。
根據本發明實施例，在半導體基底100上設置有凹陷通道區130，鄰近漂移區120。根據本發明實施例，凹陷通道區130可以是長條狀的區域，但是不限於此。根據本發明實施例，如圖1和圖2所示，凹陷通道區130可以與漂移區120部分重疊。根據本發明實施例，在漂移區120中設置有與凹陷通道區130間隔開的重摻雜區121，例如，重摻雜汲極區，其中，重摻雜區121具有第二導電型，例如，N型。根據本發明實施例，重摻雜區121是N +摻雜區，設置在凹陷通道區130兩相對側，用來做為半導體高壓元件1的汲極或源極。
根據本發明實施例，在凹陷通道區130與重摻雜區121之間設置有隔離結構220。根據本發明實施例，隔離結構220為淺溝絕緣結構。根據本發明實施例，基本上，隔離結構220環繞凹陷通道區130，在凹陷通道區130與重摻雜區121之間的隔離結構220與漂移區120重疊。根據本發明實施例，隔離結構220具有鄰近凹陷通道區130的第一厚度t1和鄰近重摻雜區121的第二厚度t2，其中第一厚度t1大於第二厚度t2。
根據本發明實施例，在凹陷通道區130上設置有埋入閘介電層131，例如，二氧化矽層，但不限於此。根據本發明實施例，埋入閘介電層131是高壓閘氧化層。根據本發明實施例，隔離結構220與埋入閘介電層131相連。根據本發明實施例，漂移區120與埋入閘介電層131部分重疊。
根據本發明實施例，埋入閘介電層131的頂面131a低於重摻雜區121的頂面121a。根據本發明實施例，埋入閘介電層131的頂面131a低於重摻雜區121的頂面121a下的深度d等於第一厚度t1與所述第二厚度t2的差值。根據本發明實施例，埋入閘介電層131的頂面131a低於重摻雜區121的頂面121a下的深度d約為500埃。根據本發明實施例，在埋入閘介電層131上設置有閘極300，例如多晶矽閘極，但不限於此。根據本發明實施例，閘極300可以延伸至凹陷通道區130周圍的隔離結構220上。
根據本發明實施例，半導體高壓元件1另包含設置在環形離子井140內的環形擴散區141，具有第一導電型，例如，P型。根據本發明實施例，環形擴散區141可以是P +摻雜區。環形擴散區141環繞漂移區120、凹陷通道區130和隔離結構220。根據本發明實施例，隔離結構220位於環形擴散區141和重摻雜區121之間的厚度是第二厚度t2，如圖3所示。根據本發明實施例，如圖3所示，隔離結構220位於環形擴散區141和凹陷通道區130之間的厚度是第一厚度t1。
本發明結構上的特徵在於，埋入閘介電層131的頂面131a低於重摻雜區121的頂面121a，並且隔離結構220具有鄰近凹陷通道區130的第一厚度t1和鄰近重摻雜區121的第二厚度t2，其中，第一厚度t1大於第二厚度t2，如此可以在不影響半導體高壓元件1的操作性能下，提高寄生場元件（parasitic field device）的恕值電壓（threshold voltage），改善半導體高壓元件1的電性及高壓操作時的穩定性。
請參閱圖4至圖11，其為根據本發明實施例所繪示的半導體高壓元件的製作方法示意圖。如圖4所示，首先提供半導體基底100，例如，矽基底，具有第一導電型，例如，P型。接著，在半導體基底100的高壓元件區HV的表面上以微影製程和蝕刻製程形成預先凹陷區TS，其中，預先凹陷區TS的深度h，例如，約為500埃。根據本發明實施例，預先凹陷區TS可以具有平坦的底面TSB和傾斜的側壁TSS。
根據本發明實施例，形成在高壓元件區HV的表面上的預先凹陷區TS可以與高壓井（high-voltage well）對準溝槽或稱為00對準溝槽（00 alignment trench）同步製作，因此，不需要額外的光罩。根據本發明實施例，預先凹陷區TS的範圍約略為圖1中閘極300扣除凹陷通道區130後的區域。根據本發明實施例，在半導體基底100中可以形成高壓井110。根據本發明實施例，高壓井110具有第一導電型，例如，P型。
如圖5所示，接著，在半導體基底100的表面上依序形成氧化矽墊層102和氮化矽墊層104。根據本發明實施例，氧化矽墊層102和氮化矽墊層104順形地覆蓋預先凹陷區TS。
如圖6所示，接著，在氮化矽墊層104上形成用來定義元件絕緣區域的硬遮罩圖案HM，其中，硬遮罩圖案HM包含開口OP，定義出預定在半導體基底100的表面上形成淺溝絕緣結構的區域。根據本發明實施例，開口OP涵蓋預先凹陷區TS，並且硬遮罩圖案HM還定義出凹陷通道區130。
如圖7所示，進行非等向性乾蝕刻製程，經由硬遮罩圖案HM的開口OP蝕刻掉顯露出來的氮化矽墊層104和氧化矽墊層102，以將硬遮罩圖案HM移轉至氮化矽墊層104和氧化矽墊層102。此時，預先凹陷區TS被顯露出來。
如圖8所示，繼續進行非等向性乾蝕刻製程，向下蝕刻半導體基底100，形成溝槽TR。由於預先凹陷區TS的關係，溝槽TR自對準地具有兩個不同的第一深度d1和第二深度d2，其中，鄰近凹陷通道區130的第一深度d1大於外圍的遠離凹陷通道區130的第二深度d2。根據本發明實施例，第一深度d1和第二深度d2的差值約略等於預先凹陷區TS的深度h，例如，500埃。根據本發明實施例，溝槽TR的底部也會有如同預先凹陷區TS的輪廓。
如圖9所示，接著，將剩下的硬遮罩圖案HM去除。然後，進行淺溝絕緣製程。例如，先在半導體基底100全面沉積絕緣層，例如，氧化矽層，並且使絕緣層填滿溝槽TR。隨後，進行化學機械研磨製程，將溝槽TR外多餘的絕緣層去除，此時，絕緣層表面基本上會和旁邊的氮化矽墊層104的表面齊平，如此形成隔離結構220。根據本發明實施例，隔離結構220具有鄰近凹陷通道區130的第一厚度t1和鄰近重摻雜區121的第二厚度t2，其中第一厚度t1大於第二厚度t2。
如圖10所示，接著，去除氮化矽墊層104和氧化矽墊層102。隨後，進行微影製程和蝕刻製程，蝕刻凹陷通道區130的半導體基底100的表面，使凹陷通道區130的半導體基底100的表面低於周圍的其它區域（例如，汲極或源極區域）的半導體基底100的表面，其落差d0約為，例如，500埃。
如圖11所示，接著，進行氧化製程，形成埋入閘介電層131，例如，二氧化矽層，但不限於此。根據本發明實施例，埋入閘介電層131是高壓閘氧化層。根據本發明實施例，隔離結構220與埋入閘介電層131相連。根據本發明實施例，埋入閘介電層131的頂面131a低於周圍的其它區域（例如，汲極或源極區域）的半導體基底100的表面下的深度d約為500埃。根據本發明實施例，最後在埋入閘介電層131上形成閘極300，例如，多晶矽閘極，但不限於此。根據本發明實施例，閘極300可以延伸至凹陷通道區130周圍的隔離結構220上。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:半導體高壓元件 100:半導體基底 102:氧化矽墊層 104:氮化矽墊層 110:高壓井 120:漂移區 121:重摻雜區 121a:頂面 130:凹陷通道區 131:埋入閘介電層 131a:頂面 140:環形離子井 141:環形擴散區 220:隔離結構 300:閘極 t1:第一厚度 t2:第二厚度 d:深度 d0:落差 d1:第一深度 d2:第二深度 h:深度 HV:高壓元件區 HM:硬遮罩圖案 OP:開口 TS:預先凹陷區 TSB:底面 TSS:側壁 TR:溝槽
圖1為根據本發明實施例所繪示的半導體高壓元件的佈局示意圖。 圖2為沿著圖1中的切線I-I’所示的剖面示意圖。 圖3為沿著圖1中的切線II-II’所示的剖面示意圖。 圖4至圖11為根據本發明實施例所繪示的半導體高壓元件的製作方法示意圖。
1:半導體高壓元件
100:半導體基底
110:高壓井
120:漂移區
121:重摻雜區
121a:頂面
130:凹陷通道區
131:埋入閘介電層
131a:頂面
140:環形離子井
141:環形擴散區
220:隔離結構
300:閘極
t1:第一厚度
t2:第二厚度
d:深度

Claims (20)

  1. 一種半導體高壓元件，包含： 一半導體基底，具有第一導電型； 一高壓井，具有所述第一導電型，設置在所述半導體基底中； 一漂移區，具有一第二導電型，設置在所述高壓井中； 一凹陷通道區，鄰近所述漂移區； 一重摻雜汲極區，具有所述第二導電型，設置在所述漂移區中並與所述凹陷通道區間隔開； 一隔離結構，設置在所述凹陷通道區與所述漂移區中的所述重摻雜汲極區之間； 一埋入閘介電層，設置在所述凹陷通道區上，其中所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面；以及 一閘極，設置在所述埋入閘介電層上。
  2. 如請求項1所述的半導體高壓元件，其特徵在於，所述隔離結構具有鄰近所述凹陷通道區的第一厚度和鄰近所述重摻雜汲極區的第二厚度，其中所述第一厚度大於所述第二厚度。
  3. 根據請求項2所述的半導體高壓元件，其特徵在於，所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面下的深度等於所述第一厚度與所述第二厚度的差值。
  4. 根據請求項3所述的半導體高壓元件，其特徵在於，所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面下的深度約為500埃。
  5. 如請求項1所述的半導體高壓元件，其特徵在於，所述隔離結構為淺溝絕緣結構。
  6. 如請求項1所述的半導體高壓元件，其特徵在於，所述隔離結構與所述埋入閘介電層相連。
  7. 如請求項1所述的半導體高壓元件，其特徵在於，所述漂移區與所述埋入閘介電層部分重疊。
  8. 如請求項1所述的半導體高壓元件，其特徵在於，另包含： 一環形擴散區，具有所述第一導電型，並且環繞所述漂移區、所述凹陷通道區和所述隔離結構。
  9. 根據請求項1的半導體高壓元件，其特徵在於，所述第一導電型是P型，所述第二導電型是N型。
  10. 如請求項1所述的半導體高壓元件，其特徵在於，所述埋入閘介電層是高壓閘氧化層。
  11. 一種製造半導體元件的方法，包含： 提供具有第一導電型的半導體基底； 在所述半導體基底中形成具有所述第一導電型的高壓井，並且在所述半導體基底中形成預先凹陷區； 在所述高壓井中形成具有第二導電型的漂移區； 形成與所述漂移區相鄰的凹陷通道區； 在所述漂移區中形成與所述凹陷通道區間隔開的且具有第二導電型的重摻雜汲極區； 在所述漂移區的所述凹陷通道區和所述重摻雜汲極區之間形成隔離結構，其中，所述隔離結構與所述預先凹陷區重疊； 在所述凹陷通道區上形成埋入閘介電層，其中所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面；以及 在所述埋入閘介電層上形成閘極。
  12. 如請求項11所述的方法，其特徵在於，所述隔離結構具有鄰近所述凹陷通道區的第一厚度和鄰近所述重摻雜汲極區的第二厚度，且其中所述第一厚度大於所述第二厚度。
  13. 如請求項12所述的方法，其特徵在於，所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面下的深度等於所述第一厚度與所述第二厚度的差值。
  14. 如請求項13所述的方法，其特徵在於，所述埋入閘介電層的頂面低於所述重摻雜汲極區的頂面下的深度約為500埃。
  15. 如請求項11所述的方法，其特徵在於，所述隔離結構為淺溝絕緣結構。
  16. 如請求項11所述的方法，其特徵在於，所述隔離結構與所述埋入閘介電層相連。
  17. 如請求項11所述的方法，其特徵在於，所述漂移區與所述埋入閘介電層部分重疊。
  18. 如請求項11所述的方法，其特徵在於，另包含： 在所述半導體基底中形成具有所述第一導電型的環形擴散區，其中所述環形擴散區環繞所述漂移區、所述凹陷通道區和所述隔離結構。
  19. 如請求項11所述的方法，其特徵在於，所述第一導電型為P型，所述第二導電型為N型。
  20. 如請求項11所述的方法，其特徵在於，所述埋入閘介電層為高壓閘氧化層。
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