TW202333298A - 半導體裝置及其製作方法 - Google Patents

半導體裝置及其製作方法 Download PDF

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TW202333298A
TW202333298A TW111130540A TW111130540A TW202333298A TW 202333298 A TW202333298 A TW 202333298A TW 111130540 A TW111130540 A TW 111130540A TW 111130540 A TW111130540 A TW 111130540A TW 202333298 A TW202333298 A TW 202333298A
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dielectric layer
gate
semiconductor device
gate electrode
region
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李信宏
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聯華電子股份有限公司
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Abstract

半導體裝置及其製作方法，半導體裝置包括基底、第一電晶體以及第二電晶體。基底包括高壓區以及低壓區。第一電晶體設置在高壓區內，包括設置在基底的第一平面上的第一閘極介電層，以及設置在第一閘極介電層上的第一閘極電極，其中，第一閘極介電層包括複合結構，其包括由下而上依序堆疊的第一介電層與第二介電層。第二電晶體設置在低壓區內，包括突出於基底的第二平面的多個鰭狀結構，以及跨設於鰭狀結構的第二閘極電極，其中，第一介電層覆蓋第二閘極電極的側壁，且第一介電層的頂面與第二閘極電極齊平。

Description

半導體裝置及其製作方法
本發明係關於一種半導體裝置及其製作方法，特別是關於一種同時具有高壓（high-voltage, HV）元件以及低壓（low-voltage, LV）元件的半導體裝置及其製作方法。
以目前的半導體技術水準，業界已能將控制電路、記憶體、低壓操作電路以及高壓操作電路及元件同時整合製作在單一晶片上，藉此降低成本，同時提高操作效能，其中如垂直擴散金氧半導體（vertical double-diffusion metal-oxide-semiconductor, VDMOS)、絕緣閘極雙載子電晶體（insulated gate bipolar transistor, IGBT)以及橫向擴散金氧半導體（lateral-diffusion metal-oxide-semiconductor, LDMOS)等製作在晶片內的高壓元件，由於具有較佳的切換效率（power switching efficiency)，而廣為應用。如熟習該項技藝者所知，前述的高壓元件往往被要求能夠承受較高的崩潰電壓，並且能在較低的阻值下操作。
另外，隨著半導體元件的尺寸越來越小，電晶體的製程步驟也有許多的改進，以製造出體積小而高品質的電晶體。舉例來說，非平面（non-planar）式場效電晶體元件，例如鰭狀場效電晶體（fin field effect transistor, FinFET）元件儼然已取代平面式場效電晶體成為目前的主流發展趨勢。然而，隨著設備尺寸的不斷減小，於同一半導體裝置同時設置高壓元件以及鰭狀場效電晶體元件變得更加困難，並且其製程也面臨許多限制與挑戰。
本發明之一目的在於提供一種半導體裝置，係將高壓元件的主動區設置於低壓元件（如鰭狀場效電晶體元件）的周邊區域，並且，將高壓元件的閘極介電層部分寄生於該低壓元件的層間介電層內。如此，該高壓元件以及該低壓元件可具有相近的高度，可避免產生顯著的高度差，同時，設置於高壓區以及低壓區內的淺溝渠隔離亦可具有相同的深度，可避免衍生嚴重的負載效應（loading effect），故有利於提升半導體裝置的整體效能。
本發明之一目的在於提供一種半導體裝置的製作方法，係整合高壓元件以及低壓元件的製作工藝，於定義低壓元件中的鰭狀結構時一併定義高壓元件的主動區，進而達到製程簡化的效果。
為達上述目的，本發明提供一種半導體裝置，包括基底、第一電晶體以及第二電晶體。該基底包括高壓區以及低壓區。該第一電晶體設置在該高壓區內，包括設置在該基底的第一平面上的第一閘極介電層，以及設置在該第一閘極介電層上的第一閘極電極，其中，該第一閘極介電層包括複合結構，該複合結構包括由下而上依序堆疊的第一介電層與第二介電層。該第二電晶體設置在該低壓區內，包括突出於該基底的第二平面的多個鰭狀結構，以及跨設於該些鰭狀結構的第二閘極電極，其中，該第一介電層覆蓋該第二閘極電極的側壁，且該第一介電層的頂面與該第二閘極電極齊平。
為達上述目的，本發明提供一種半導體裝置的製作方法，包括以下步驟。首先，提供基底，該基底包括高壓區以及低壓區，然後，在該高壓區內形成第一電晶體，該第一電晶體包括設置在該基底的第一平面上的第一閘極介電層，以及設置在該第一閘極介電層上的第一閘極電極，其中，該第一閘極介電層包括複合結構，該複合結構包括由下而上依序堆疊的第一介電層與第二介電層。接著，在該低壓區內形成第二電晶體，該第二電晶體包括突出於該基底的第二平面的多個鰭狀結構，以及跨設於該些鰭狀結構的第二閘極電極，其中，該第一介電層覆蓋該第二閘極電極的側壁，且該第一介電層的頂面與該第二閘極電極齊平。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。並且，在不脫離本發明的精神下，下文所描述的不同實施例中的技術特徵彼此間可以被置換、重組、混合，以構成其他的實施例。
本發明是涉及了一種半導體裝置的製作方法，其整合高壓（high voltage, HV）元件以及低壓（low voltage, LV）元件的製作方法，其中該高壓元件例如係指起始電壓介於10伏特（V）至20伏特之間的半導體電晶體，而該低壓元件例如係指起始電壓介於0.5伏特至1伏特之間的半導體電晶體，但不以此為限。請參閱圖1至圖9，其為依據本發明第一實施例中半導體裝置300的製作方法的示意圖。
首先，請參照圖1所示，提供基底100，其例如包括矽基底（silicon substrate）、磊晶矽（epitaxial silicon substrate）基底、含矽基底（silicon containing substrate）或矽覆絕緣(silicon-on-insulator, SOI）基底等，但不以此為限。基底100至少具有第一區100H以及第二區100L，其中，第一區100H例如是作為基底100的高壓區（high-voltage region, HV region），用於形成各種高壓元件如適用於高壓操作的半導體電晶體，第二區100L則例如是作為基底100的低壓區（low-voltage region, LV region），用於形成各種低壓元件如適用於低壓操作的半導體電晶體。在本實施例中，第一區100H以及第二區100L之間還可進一步設置其他區域，如中壓區（medium-voltage region, MV region）等，但不以此為限。
需注意的是，基底100的第一區100H內具有高壓深井區110，其形成方法包括但不限定為以下步驟。首先，於基底100上形成遮罩結構（未繪示），覆蓋基底100的第二區100L並暴露出基底100的第一區100H，接著，對基底100的第一區100H進行離子佈植製程，例如是使用相對較高的摻雜能量進行離子摻雜，以在基底100的第一區100H內形成高壓深井區110，如此，高壓深井區110可自基底100於第一區100H內的最頂面向下延伸至基底100內，如圖1所示，但不以此為限。在一實施例中，高壓深井區110具有一導電形式，例如為P型摻雜區，但不以此為限。
然後，再如圖1所示，於基底100上進行側壁自對準雙重圖案化（sidewall aligned double patterning, SADP）製程，其包括但不限定為以下步驟。首先，於基底100上形成遮罩結構120，包括由下而上依序堆疊的第一遮罩層121（例如包含氧化矽層）、第二遮罩層123（例如包含氮化矽層）以及第三遮罩層125（例如包含氧化矽層），並透過微影暨蝕刻製程在遮罩結構120上形成多個圖案化犧牲層（mandrels）130。其中，為了利用該側壁自對準雙重圖案化製程於第二區100L（即該低壓區）內形成高積集度的低壓元件，圖案化犧牲層130包括多個尺寸與設置間距皆相對較小的第三圖案化犧牲層132，係設置於基底100的第二區100L內。接著，依序進行沉積及回蝕刻製程，以於各圖案化犧牲層130的側壁形成一側壁子140，如圖1所示。此外，在第一區100H（即該高壓區）內，同時形成的圖案化犧牲層130還包括多個尺寸與設置間距（pitch）皆相對較大的第一圖案化犧牲層131以及第二圖案化犧牲層133，第一圖案化犧牲層131例如是形成在兩個第二圖案化犧牲層133之間，並且，與兩側相鄰的第二圖案化犧牲層133之間具有相同的間距，如圖1所示。
如圖2所示，於基底100上形成遮罩層150（例如包含光阻材質），覆蓋基底100的第一區100H而暴露出基底100的第二區100L，並且，透過遮罩層150進行蝕刻製程，以去除設置於第二區100L內的第三圖案化犧牲層132，留下側壁子140來定義出所需鰭狀結構的位置。接著，完全移除遮罩層150，再透過設置於第一區100H內的第一圖案化犧牲層131、第二圖案化犧牲層133與側壁子140，以及設置於第二區100L內的側壁子140進行另一蝕刻製程，將第一區100H內的第一圖案化犧牲層131、第二圖案化犧牲層133與側壁子140的圖案同時轉移至下方的遮罩結構120以及基底100，以在第一區100H的基底100內分別定義出主動區101、103以及位在主動區101、103之間較低的平面102，其中，主動區101位於兩個主動區103之間；同時，將第二區100L內側壁子140的圖案轉移至下方的遮罩結構120以及基底100，以在第二區100L的基底100內分別蝕刻出多個鰭狀結構105以及位在各鰭狀結構105之間較低的平面104。換言之，形成於第二區100L內的鰭狀結構105係突出於基底100的平面104，並且，第二區100L內的平面104係與第一區100H內的平面102相互齊高，而各主動區101、103頂部的平面101a、103a則與鰭狀結構105的頂面齊高，如圖3所示。
而後，再如圖3所示，先進行一介電材料的沉積製程，然後利用遮罩結構120當作停止層來對該介電材料進行一平坦化製程，接著再進行一回蝕刻製程來部分移除該介電材料，以暴露出第一區100H內各主動區101、103的上半部以及第二區100L內鰭狀結構105的上半部105a，進而使剩餘的該介電材料在基底100內分別形成多個淺溝渠隔離160，並分別環繞第一區100H內的主動區101、103與第二區100L內的鰭狀結構105。之後，完全移除遮罩結構120。其中，值得注意的是，各主動區101、103頂部的平面101a、103a、各鰭狀結構105的該頂面齊平，而位在基底100的第一區100H內的淺溝渠隔離161則與位在基底100的第二區100L內淺溝渠隔離162具有相同的深度D1。之後，還可透過另一遮罩層（未繪示）於基底100的第一區100H內進行另一離子佈植製程，以在部分的主動區101與主動區103內形成高壓摻雜區115。其中，高壓摻雜區115係完全位在高壓深井區110內，並具有相同的導電型式（如同為P型或同為N型）以及相對較高的摻雜濃度，如此，可在後續製程中作為高壓元件的源極/汲極區。
如圖4所示，然後，於各主動區103暴露的該上半部以及鰭狀結構105的上半部105a上分別形成閘極結構170、180。細部來說，閘極結構170係設置於主動區103的上方，以部分覆蓋主動區103的平面103a與一側的側壁，閘極結構180則設置於至少一鰭狀結構105上，並跨設於相對應的鰭狀結構105的上半部105a。在一實施例中，閘極結構170、180的製程包括但不限於以下步驟。首先，於基底100上依序形成閘極介電材料層（未繪示，例如包括氧化矽等材質）以及閘極電極層（未繪示，例如包括多晶矽等材質），然後，對該閘極介電材料層以及該閘極電極層進行圖案化製程，以同時形成閘極結構170、180。如此，閘極結構170、180可分別包括由下而上依序堆疊的閘極介電層171、181以及閘極電極層173、183，其中，閘極介電層181係直接接觸各鰭狀結構105的上半部105a的表面上，而閘極電極183則形成在閘極介電層181上並跨設於各鰭狀結構105的上半部105a，進而成為一多晶矽閘極（poly gate）。此外，在形成多晶矽閘極之後，亦可視需求來進行蝕刻鰭狀結構（fin recess）、磊晶製程以及形成低壓電晶體的源極/汲極（source/drain, S/D）等製程，在此不多加贅述。
然後，再如圖4所示，於基底100上形成接觸蝕刻阻擋材料層（contact etch stop layer, CESL）190，其係共型地覆蓋於淺溝渠隔離160、各主動區101、103、鰭狀結構105以及閘極結構170、180上。在一實施例中，接觸蝕刻阻擋材料層190例如包括氮化矽、氮氧化矽或碳氮化矽等材質，但不以此為限。
如圖5所示，進行接觸蝕刻阻擋材料層190的圖案化製程。首先，於基底100上形成遮罩結構210，其具有開口212，以暴露出第一區100H內的主動區101及其兩側一部分的淺溝渠隔離161。在一實施例中，遮罩結構210例如包括由下而上依序堆疊的第一遮罩層211（例如包括填洞能力較佳的有機介電材質等）以及第二遮罩層213（例如包括氮化矽等材質），但不以此為限。然後，透過遮罩結構210進行蝕刻製程，部分移除接觸蝕刻阻擋材料層190，以暴露出主動區101頂部的平面101a及其兩側該部分的淺溝渠隔離161。其中，平面101a係明顯高於各主動區101、103之間的平面102，以及各鰭狀結構105之間的平面104。此外，本領域者應可理解，在進行接觸蝕刻阻擋材料層190的該圖案化製程時，還可一併於基底100的第二區100H內形成多個接觸洞，舉例來說，遮罩結構210上還可進一步包括其他開口（未繪示），以暴露出的鰭狀結構105的一部分（未繪示），如此，即可在後續製程中，於鰭狀結構105的該部分上進行金屬矽化物製程，並形成插塞（未繪示）。
如圖6所示，於完全移除遮罩結構210後，進行沉積製程，例如一可流動式化學氣相沉積（flowable chemical vapor deposition, FCVD），以於基底100上形成一介電材料層（interlayer dielectric layer, ILD）220，使得介電材料層220可整體性地覆蓋淺溝渠隔離160、各主動區101、103、鰭狀結構105以及閘極結構170、180。在一實施例中，介電材料層220例如包括氧化矽等材質，但不以此為限。
如圖7所示，進行金屬閘極置換（replacement of metal gate, RMG）製程，其包括但不限定為以下步驟。首先，進行平坦化製程，例如是化學機械研磨製程（chemical mechanical polishing/planarizing process, CMP），部分移除介電材料層220至部分暴露出接觸蝕刻阻擋材料層190，再進一步移除覆蓋在閘極結構170、180頂面的接觸蝕刻阻擋材料層190，如此，可依序形成第一介電層221與接觸蝕刻阻擋層191，其中，第一介電層221係覆蓋在接觸蝕刻阻擋層191上。需特別說明的是，第一介電層221係作為半導體裝置300的層間介電層（interlayer dielectric layer, ILD），是以，其頂面係與閘極結構170、180的該頂面齊平。然後，完全移除閘極結構170、180，以在第一介電層221內形成多個閘極溝渠，包括位於第一區100H內的兩個閘極溝渠223，其係分別暴露出主動區103頂部的平面103a，以及位於第二區100H內的閘極溝渠225，其係暴露出鰭狀結構105的頂部105a，如圖7所示。其中，各閘極溝渠223、225兩側的側壁均被接觸蝕刻阻擋層191所覆蓋，如圖7所示。
然後，如圖8所示，於各閘極溝渠223、225內依序形成閘極介電層231、251，例如包括一高介電常數介電（high dielectric constant, high-k）材質如氧化鉿（hafnium oxide, HfO 2）、矽酸鉿氧化合物（hafnium silicon oxide, HfSiO 4）或矽酸鉿氮氧化合物（hafnium silicon oxynitride, HfSiON）等，以及閘極電極233、253，其例如包括一低阻值金屬材質如鋁（aluminum, Al）、鈦（titanium, Ti）、鉭（tantalum, Ta）或鎢（tungsten, W）等，但不以此為限。如此，依序堆疊的閘極介電層231與閘極電極233可填滿各閘極溝渠223，進而形成電晶體230，位於第一區100H內。另一方面，依序堆疊的閘極介電層251與閘極電極253則可填滿閘極溝渠225，進而形成電晶體250，位於第二區100L內。在此設置下，電晶體230、250皆可包括金屬閘極（metal gate），並且分別被部分的接觸蝕刻阻擋層191以及第一介電層221所環繞，使得接觸蝕刻阻擋層191可設置於閘極電極233、253與第一介電層221之間，如圖8所示。其中，電晶體250的閘極電極253因是跨設於鰭狀結構105的頂部105a而可成為鰭狀場效電晶體，其可作為低壓電晶體而適用於低壓操作；而電晶體230則可作為虛置閘極或是適用於其他電壓範圍，但不以此為限。
而後，再如圖8所示，於基底100上形成閘極堆疊260，其包括由下而上依序堆疊的第二介電層261、導電層（例如包括多晶矽、氮化鈦等材質）263、以及蓋層（例如包括氮化矽等材質）265，以整體性地覆蓋下方的第一介電層221以及各電晶體230、250。需注意的是，第二介電層261例如包括四乙氧基矽烷（tetraethoxysilane, TEOS）等低介電材質，其係直接覆蓋於第一介電層221以及各電晶體230、250的上方，以保護下方的各電晶體230、250（特別是其閘極電極233、253）免於受到後續製程的影響，但不以此為限。
如圖9所示，對閘極堆疊260進行圖案化製程，以在主動區101上方形成電晶體270。電晶體270包括依序堆疊的第二介電層261a、閘極電極263a以及蓋層265a，其中，第二介電層261a、閘極電極263a以及蓋層265a可具有垂直切齊的側壁，並且，在垂直於基底100的垂直方向（未繪示）上可完全覆蓋於下方的主動區101。需說明的是，部分的第一介電層221（第一介電層221介於兩個電晶體230之間的部分）係形成在主動區101最頂部的平面101a上，是以，該部分的第一介電層221以及第二介電層261a可共同形成電晶體270的閘極介電層271，閘極電極263a設置於閘極介電層271上，而兩側的主動區103則可作為電晶體270的源極/汲極區，該些源極/汲極區的上方分別設置電晶體230，並透過淺溝渠隔離161與主動區101相互隔離，如圖9所示。換言之，本實施例的電晶體270的閘極介電層271係具有複合結構，其包括依序堆疊於平面101a上的第一介電層221以及第二介電層261a。需注意的是，第一介電層221以及第二介電層261a在平行於基底100的水平方向（未繪示）上分別具有不同的長度，使得第一介電層221以及第二介電層261a兩側的側壁並未垂直切齊，此外，第一介電層221以及第二介電層261a分別具有不同的厚度，其中，第一介電層221的厚度T1例如是約為第二介電層261a的厚度T2的4倍至2倍左右，使得第一介電層221與第二介電層261a的厚度比例可約為4:1至4:2，但不以此為限。
此外，需額外說明的是，本實施例的高壓元件還可進一步包括一電阻結構（未繪示），例如是高阻質的電阻元件（high resistant resistor, HiR），其包括由下依序堆疊的導電層以及蓋層。本領域者應可輕易理解，該電阻結構的製作可整合於電晶體270的製作，舉例來說，可於圖案化閘極堆疊260時，一併於第一區100H內形成閘極電極263a以及基底100的一電阻區（未繪示）內形成一電阻結構，使得該電阻結構的該導電層與電晶體270的閘極電極263a可具有相同的材質（例如包括多晶矽、氮化鈦等材質）與厚度，但不以此為限。在另一實施例中，亦可選擇於電晶體270形成前或形成後，額外進行微影暨蝕刻製程，形成該電阻結構，如此，該電阻結構的該導電層與電晶體270的閘極電極263a可分別具有不同的材質與厚度。
由此，即完成本發明第一實施例中的半導體裝置300的製作。在本實施例的形成方法係於定義鰭狀結構105時，將原本用於形成調整標記（alignment mark）的周邊區一併定義為高壓元件的主動區101、103，藉此，可在製程簡化的前提下整合鰭狀場效電晶體（即電晶體250）的製程以及高壓元件（即電晶體270）的製程。並且，在本實施例中，高壓元件（即電晶體270）具有複合結構的閘極介電層271，其中，部分的閘極介電層（即第一介電層221設置在平面101a上的部分）係寄生於半導體裝置300的層間介電層（即第一介電層221）內。在此設置下，即使高壓元件的閘極介電層具有相對較大的厚度，仍可有效地整合於鰭狀場效電晶體的結構中，使得鰭狀場效電晶體的閘極頂面可齊平於該部分的閘極介電層的頂面，避免高壓元件（即電晶體270）與低壓元件（即電晶體250）之間形成過大的高度落差，避免衍生嚴重的負載效應，故有利於提升半導體裝置300的整體效能。
本領域者應可輕易瞭解，為能滿足實際產品需求的前提下，本發明的半導體裝置亦可能有其它態樣，而不限於前述實施例所述。舉例來說，在另一實施例中，亦可在進行圖7所示的金屬閘極置換（RMG）製程時，選擇僅曝露閘極結構180，進而將閘極溝渠225內的閘極介電層181及閘極電極層183分別置換成閘極介電層251與閘極電極253。然後，再於後續製程中完全移除閘極結構170，用以將閘極溝渠223內的閘極介電層171及閘極電極層173置換成一導電材料，進而形成一直接接觸主動區103內的高壓摻雜區115的源極/汲極插塞（S/D contact, 未繪示）。下文將進一步針對本發明半導體裝置的其他實施例或變化型進行說明。且為簡化說明，以下說明主要針對各實施例不同之處進行詳述，而不再對相同之處作重複贅述。此外，本發明之各實施例中相同之元件系以相同之標號進行標示，以利於各實施例間互相對照。
請參照圖10所示，其繪示本發明第二實施例中半導體裝置500的製作方法的示意圖。本實施例的形成方法大體上與前述實施例的形成方法相同，如圖1至圖8所示，相同之處於此不再贅述。本實施例與前述實施例主要差異在於，第二介電層261直接覆蓋在電晶體250的閘極電極253的頂面。
細部來說，在圖案化本實施例的閘極堆疊260時，係利用第二介電層261作為蝕刻阻擋層，如此，本實施例的第二介電層261於該圖案化製程進行後，仍可完整的覆蓋於下方的第一介電層221以及電晶體230、250的頂面，保護下方元件，特別係電晶體230、250的閘極電極233、253。如此，本實施例的電晶體370仍包括依序堆疊的第二介電層261、閘極電極263a以及蓋層265a，其中，閘極電極263a以及蓋層265a具有垂直切齊的側壁，而第二介電層261的側壁則為垂直切齊於閘極電極263a、蓋層265a的側壁。此外，在本實施例中，形成在平面101a上的第一介電層221以及第二介電層261同樣可共同形成電晶體370的閘極介電層371，閘極電極263a設置於閘極介電層371上，而兩側的主動區103則可作為電晶體270的源極/汲極區，該些源極/汲極區的上方分別設置電晶體230，並透過淺溝渠隔離161與主動區101相互隔離，如圖10所示。在此設置下，第一介電層221以及第二介電層261兩側的側壁可垂直切齊並分別具有不同的厚度，其中，第一介電層221的厚度T1例如是約為第二介電層261的厚度T2的4倍至2倍左右，使得第一介電層221與第二介電層261的厚度比例可約為4:1至4:2，但不以此為限。
由此，即完成本發明第二實施例中的半導體裝置500的製作。在本實施例中，電晶體370的閘極介電層371同樣係部分寄生於層間介電層中，使得高壓元件的閘極介電層的一部分整合於鰭狀場效電晶體的層間介電層中，使得鰭狀場效電晶體的閘極頂面可齊平於該部分的閘極介電層的頂面，避免高壓元件（即電晶體370）與低壓元件（即電晶體250）之間形成過大的高度落差，避免衍生嚴重的負載效應，故有利於提升半導體裝置500的整體效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100:基底 100H:第一區 100L:第二區 101、103:主動區 101a、103a:平面 105:鰭狀結構 105a:頂部 110:高壓深井區 115:摻雜區 160、161、162:淺溝渠隔離 170、180:閘極結構 171、181:閘極介電層 173、183:閘極電極層 190:接觸蝕刻阻擋材料層 191:接觸蝕刻阻擋層 210:遮罩結構 211:第一遮罩層 212:開口 213:第二遮罩層 220:介電材料層 221:第一介電層 223、225:閘極溝渠 230、250:電晶體 231、251:閘極介電層 233、253:閘極電極 261、261a:第二介電層 263a:閘極電極 265a:蓋層 270、370:電晶體 271、371:閘極介電層 300、500:半導體裝置 D1:深度
圖1至圖9繪示本發明第一實施例中半導體裝置的製作方法的示意圖，其中： 圖1為一半導體裝置於進行側壁自對準雙重圖案化製程的剖面示意圖； 圖2為一半導體裝置於形成遮罩層後的剖面示意圖； 圖3為一半導體裝置於形成介電層後的剖面示意圖； 圖4為一半導體裝置於形成接觸蝕刻阻擋材料層後的剖面示意圖； 圖5為一半導體裝置於進行蝕刻製程後的剖面示意圖； 圖6為一半導體裝置於形成層間介電層後的剖面示意圖； 圖7為一半導體裝置於進行金屬閘極置換製程的剖面示意圖； 圖8為一半導體裝置於形成閘極堆疊後的剖面示意圖；以及 圖9為一半導體裝置於形成高壓閘極後的剖面示意圖。 圖10繪示本發明第二實施例中半導體裝置的製作方法的示意圖。
100:基底
100H:第一區
100L:第二區
101、103:主動區
101a、103a:平面
102、104:平面
105:鰭狀結構
105a:頂部
110:高壓深井區
115:摻雜區
160、161、162:淺溝渠隔離
191:接觸蝕刻阻擋層
221:第一介電層
230、250:電晶體
231、251:閘極介電層
233、253:閘極電極
261a:第二介電層
263a:閘極電極
265a:蓋層
270:電晶體
271:閘極介電層
300:半導體裝置

Claims (20)

  1. 一種半導體裝置，其特徵在於包括： 基底，包括高壓區以及低壓區； 第一電晶體，設置在該高壓區內，該第一電晶體包括： 第一閘極介電層，設置在該基底的第一平面上，其中，該第一閘極介電層包括複合結構，該複合結構包括由下而上依序堆疊的第一介電層與第二介電層；以及 第一閘極電極，設置在該第一閘極介電層上；以及 第二電晶體，設置在該低壓區內，該第二電晶體包括： 多個鰭狀結構，突出於該基底的第二平面；以及 第二閘極電極，跨設於該些鰭狀結構上，其中，該第一介電層覆蓋該第二閘極電極的側壁，且該第一介電層的頂面與第二閘極電極的頂面齊平。
  2. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，該第二介電層覆蓋該第二閘極電極的該頂面。
  3. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，該第二介電層的側壁與該第一閘極電極垂直切齊。
  4. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，該第二閘極電極包括金屬閘極。
  5. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，還包括： 接觸蝕刻阻擋層，設置於該第二閘極電極與該第一介電層之間，該第一介電層覆蓋該接觸蝕刻阻擋層。
  6. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，該第一平面高於該第二平面，且該第一平面與該鰭狀結構的頂面齊高。
  7. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，還包括： 多個淺溝渠隔離，設置於該基底內並分別為在該低壓區與該高壓區內，其中，位於該低壓區內的該淺溝渠隔離與位於該高壓區內的該淺溝渠隔離具有相同的深度，且該些鰭狀結構的頂部突出於該低壓區內的該淺溝渠隔離的頂面。
  8. 如申請專利範圍第7項所述的半導體裝置，其特徵在於，該第一電晶體還包括： 兩源極/汲極區設置於該基底內，該高壓區內的該淺溝渠隔離設置於該第一閘極電極與該些源極/汲極區之間。
  9. 如申請專利範圍第8項所述的半導體裝置，其特徵在於，還包括： 兩虛置閘極分別設置在該些源極/汲極區上，其中，該些虛置閘極的頂面與該第一介電層的頂面齊平。
  10. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，該第一介電層與該第二介電層的厚度比例為4:1至4:2。
  11. 一種半導體裝置的製作方法，其特徵在於包括： 提供基底，該基底包括高壓區以及低壓區； 在該高壓區內形成第一電晶體，該第一電晶體包括： 第一閘極介電層，設置在該基底的第一平面上，其中，該第一閘極介電層包括複合結構，該複合結構包括由下而上依序堆疊的第一介電層與第二介電層；以及 第一閘極電極，設置在該第一閘極介電層上；以及 在該低壓區內形成第二電晶體，該第二電晶體包括： 多個鰭狀結構，突出於該基底的第二平面；以及 第二閘極電極，跨設於該些鰭狀結構上，其中，該第一介電層覆蓋該第二閘極電極的側壁，且該第一介電層的頂面與該第二閘極電極齊平。
  12. 如申請專利範圍第11項所述的半導體裝置的製作方法，其特徵在於，還包括： 進行側壁自對準雙重圖案化製程，以在該低壓區的該第二表面上形成該些鰭狀結構，並在該高壓區內形成該第一表面；以及 分別於該低壓區與該高壓區內形成多個淺溝渠隔離，其中，位在該低壓區內的該淺溝渠隔離與位在該高壓區內的該淺溝渠隔離具有齊平的底面，該些鰭狀結構的頂部突出於位在該低壓區內的該淺溝渠隔離的頂面。
  13. 如申請專利範圍第12項所述的半導體裝置的製作方法，其特徵在於，還包括： 形成多晶矽閘極橫跨該些鰭狀結構的該頂部； 於該些淺溝渠隔離、該基底與該多晶矽閘極上形成接觸蝕刻阻擋材料層； 部分移除位在該高壓區內的該接觸蝕刻阻擋材料層； 於該接觸蝕刻阻擋材料層上形成第一介電材料層；以及 進行平坦化製程，形成接觸蝕刻阻擋層與該第一介電層，其中，該第一介電層覆蓋該接觸蝕刻阻擋層，該多晶矽閘極埋設在該第一介電層內並僅暴露出該多晶矽閘極的表面。
  14. 如申請專利範圍第13項所述的半導體裝置的製作方法，其特徵在於，還包括： 於該接觸蝕刻阻擋材料層形成之前，於該基底內形成兩源極/汲極，該些源極/汲極係被該高壓區內的該淺溝渠隔離環繞；以及 於該些源極/汲極上分別形成兩虛置閘極，其中，該些虛置閘極的頂面與該第一介電層的該頂面齊平。
  15. 如申請專利範圍第13項所述的半導體裝置的製作方法，其特徵在於，還包括： 進行金屬閘極置換製程，移除該多晶矽閘極並形成該第二閘極電極，其中，該第二閘極包括金屬閘極。
  16. 如申請專利範圍第15項所述的半導體裝置的製作方法，其特徵在於，於該金屬閘極置換製程進行後，形成該第二介電層覆蓋該第二閘極電極的該頂面，並且，形成該第一閘極電極，其中，該第二介電層的側壁與該第一閘極電極的側壁並未垂直切齊。
  17. 如申請專利範圍第15項所述的半導體裝置的製作方法，其特徵在於，於該金屬閘極置換製程進行後，還包括： 形成第二介電材料層覆蓋該第二閘極電極的該頂面； 於該第二介電材料層上形成一導電材料層；以及 圖案化該第二介電材料層以及該導電材料層，形成該第一閘極電極與該第二介電層，其中，該第二介電層的側壁與該第一閘極電極的側壁垂直切齊。
  18. 如申請專利範圍第16項所述的半導體裝置的製作方法，其特徵在於，還包括： 於該第二介電層上形成電阻結構。
  19. 如申請專利範圍第18項所述的半導體裝置的製作方法，其特徵在於，於該第一閘極電極形成時，形成該電阻結構。
  20. 如申請專利範圍第18項所述的半導體裝置的製作方法，其特徵在於，還包括： 於該自對準雙重圖案化製程進行前，於該基底內形成高壓深井區。
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