CN107978634B - 高压半导体组件以及其制作方法 - Google Patents
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Abstract
本发明公开一种高压半导体组件以及其制作方法,利用于半导体基底中形成凹陷,再于凹陷中形成栅极介电层以及主栅极结构。因此,以本发明制作方法形成的高压半导体组件可包括主栅极结构低于半导体基底中的隔离结构的上表面,由此可避免因高压半导体组件所需厚度较厚的栅极介电层所导致的栅极结构高度过高而影响与其他半导体组件之间的制作工艺整合问题。
Description
技术领域
本发明涉及一种半导体组件以及其制作方法,尤其是涉及一种高压半导体组件以及其制作方法。
背景技术
在具有高压处理能力的功率组件中,双扩散金属氧化物半导体(double-diffusedMOS,DMOS)晶体管组件持续受到重视。常见的DMOS晶体管组件有垂直双扩散金属氧化物半导体(vertical double-diffused MOS,VDMOS)与横向双扩散金属氧化物半导体(LDMOS)晶体管组件。LDMOS晶体管组件因具有较高的操作带宽与操作效率,以及易与其他集成电路整合的平面结构,现已广泛地应用于高电压操作环境中,例如中央处理器电源供应(CPUpower supply)、电源管理系统(power management system)、直流/交流转换器(AC/DCconverter)以及高功率或高频段的功率放大器等等。LDMOS晶体管组件主要的特征为利用设置具有低掺杂浓度、大面积的横向扩散漂移区域来缓和源极端与漏极端之间的高电压,因此可使LDMOS晶体管组件获得较高的击穿电压(breakdown voltage)。然而,在集成电路的整合制作工艺中,当LDMOS晶体管组件中的栅极氧化物层因电性需求而需厚度较厚时,会导致形成于栅极氧化物层上的栅极结构的高度过高,而与晶片上的其他半导体组件(例如低压半导体组件)的栅极结构高度形成明显差异,进而造成相关制作工艺(例如平坦化制作工艺)在进行时产生问题而影响到产品良率。此外,在一些产品规格的要求下,需要具有长度较长的栅极结构的LDMOS晶体管组件,然而若以金属材料(例如铝)来形成栅极结构时,较大面积的金属栅极结构在进行化学机械研磨(chemical mechanical polishing,CMP)制作工艺时易发生碟形下陷(dishing)的问题,进而对LDMOS晶体管组件的电性产生负面影响,故有必要就此问题进行改善。
发明内容
本发明提供了一种高压半导体组件(high voltage semiconductor device)以及其制作方法,利用于半导体基底中形成凹陷,再于凹陷中形成栅极介电层以及主栅极结构,故主栅极结构可低于半导体基底中的隔离结构的上表面,由此可避免因高压半导体组件所需厚度较厚的栅极介电层所导致的栅极结构高度过高而引发的相关制作工艺问题,进而达到提升产品生产良率的效果。
根据本发明的一实施例,本发明提供了一种高压半导体组件,包括一半导体基底、两个隔离结构、一栅极介电层、一主栅极结构以及两个次栅极结构。两个隔离结构设置于半导体基底中,栅极介电层设置于两个隔离结构之间,且栅极介电层低于各隔离结构的一上表面。主栅极结构设置于栅极介电层上,且主栅极结构低于各隔离结构的上表面。各次栅极结构部分设置于主栅极结构上且部分设置于两个隔离结构的其中一者上。
根据本发明的一实施例,本发明还提供了一种高压半导体组件,包括一半导体基底、两个隔离结构、一栅极介电层以及一主栅极结构。两个隔离结构设置于半导体基底中,栅极介电层设置于两个隔离结构之间,且栅极介电层低于各隔离结构的一最上表面。主栅极结构设置于栅极介电层以及两个隔离结构上,且主栅极结构低于各隔离结构的最上表面。
根据本发明的一实施例,本发明还提供了一种高压半导体组件的制作方法,包括下列步骤。提供一半导体基底,且两个隔离结构形成于半导体基底中。在半导体基底中形成一凹陷,并于半导体基底的凹陷中形成一栅极介电层。然后,在栅极介电层上形成一主栅极结构,且主栅极结构低于各隔离结构的一上表面。
附图说明
图1为本发明第一实施例的高压半导体组件的示意图;
图2至图7所绘示为本发明第一实施例的高压半导体组件的制作方法示意图,其中
图3为图2之后的制作方法示意图;
图4为图3之后的制作方法示意图;
图5为图4之后的制作方法示意图;
图6为图5之后的制作方法示意图;
图7为图6之后的制作方法示意图。
图8为本发明第二实施例的高压半导体组件的示意图。
主要组件符号说明
10 半导体基底
11 飘移区
20 隔离结构
20N 缺口
20T 第一上表面
29 图案化屏蔽
30 栅极介电层
30T 第二上表面
40 第一栅极材料层
40G 主栅极结构
40L 第一长度
40T 第三上表面
51 间隙子
52 接触蚀刻停止层
53 层间介电层
60 源极/漏极区
70 第二栅极材料层
70G 次栅极结构
70L 第二长度
90 凹陷制作工艺
101-102 高压半导体组件
D1 第一方向
D2 第二方向
DP 深度
R 凹陷
T 沟槽
TK 厚度
具体实施方式
请参阅图1。图1为本发明第一实施例的高压半导体组件的示意图。如图1所示,本实施例提供一种高压半导体组件101,包括一半导体基底10、两个隔离结构20、一栅极介电层30、一主栅极结构40G以及两个次栅极结构70G。在本实施例中,半导体基底10可包括硅基板、外延硅基板、硅锗基板、碳化硅基板或硅覆绝缘(silicon-on-insulator,SOI)基板,但不以此为限。两个隔离结构20设置于半导体基底10中,隔离结构20可包括一浅沟隔离(shallow trench isolation,STI)结构,可通过于半导体基底10中形成沟槽并填入绝缘材料而形成,但并不以此为限。在一些实施例中,隔离结构20也可为例如通过局部硅氧化(LOCOS)的方法形成场氧化层(field oxide,FOX)或其他适合的绝缘结构。此外,半导体基底10中可更形成有两个飘移区(drift region)11,而两个隔离结构20分别形成于两个飘移区11中。飘移区11可包括利用例如一注入制作工艺所形成的掺杂阱区。在一些实施例中,半导体基底10较佳可具有一第一导电型态或包括有一第一导电型态的区域,而漂移区11则较佳可具有第二导电型态,且第二导电型态与第一导电型态互补(complementary)。举例来说,本实施例中第一导电型态可为p型,第二导电型态可为n型,但并不以此为限。换句话说,半导体基底10可为p型半导体基底或具有p型阱的半导体基底,而漂移区11可为n型阱,但并不以此为限。
栅极介电层30于一第一方向D1上设置于两个隔离结构20之间,且栅极介电层30低于各隔离结构20的一上表面(例如图1中所示的第一上表面20T)。在本实施例中,栅极介电层30的任何一部分,包括其上表面(例如图1中所示的第二上表面30T)均于一垂直方向(例如图1中所示的第二方向D2)上位于隔离结构20的上表面所处的一水平面的下方。栅极介电层30可包括氧化物介电层或其他适合材料所形成的介电层。主栅极结构40G设置于栅极介电层30上,且主栅极结构40G低于各隔离结构20的第一上表面20T。举例来说,主栅极结构40G的至少部分的上表面(例如图1中所示的第三上表面40T)于第二方向D2上低于各隔离结构20的第一上表面20T。此外,在一些实施例中,主栅极结构40G的任何一部分(包括其最上表面)均于第二方向D2上位于隔离结构20的第一上表面20T所处的水平面的下方。此外,各次栅极结构70G部分设置于主栅极结构40G上且部分设置于两个隔离结构20的其中一者上。更明确地说,两个次栅极结构70G分别设置于主栅极结构40G于第一方向D1上相对的两端,且此两个次栅极结构70G也分别设置于在第一方向D1上位于主栅极结构40G两侧的两个隔离结构20上。
在一些实施例中,主栅极结构40G的材料可不同于次栅极结构70G的材料,例如主栅极结构40G可包括一多晶硅栅极结构,且各次栅极结构70G包括一金属栅极结构,但并不以此为限。此外,主栅极结构40G于第一方向D1上的长度(例如图1中所示的第一长度40L)较佳地是大于各次栅极结构70G于第一方向D1上的长度例如图1中所示的第二长度70L),但并不以此为限。两个次栅极结构70G与主栅极结构40G相连且电连接,故主栅极结构40G以及两个次栅极结构70G可构成部分位于两个隔离结构20之间以及部分位于两个隔离结构20之上的栅极结构。
此外,高压半导体组件101可还包括两个源极/漏极区60、一间隙子51、一接触蚀刻停止层52以及一层间介电层53。两个源极/漏极区60设置于半导体基底10中,且分别设置于两个隔离结构20的外侧。更明确地说,两个源极/漏极区60分别设置于两个飘移区11中,且隔离结构20于第一方向D1上位于主栅极结构40G与源极/漏极区60之间。在一些实施例中,当半导体基底10为p型半导体基底或具有p型阱的半导体基底且漂移区11为n型阱时,两个源极/漏极区60可分别为一n型掺杂区,但并不以此为限。间隙子51可分别设置于两个次栅极结构70G的侧壁上,接触蚀刻停止层52可设置于主栅极结构40G、隔离结构20以及源极/漏极区60上,而层间介电层53可设置于接触蚀刻停止层52上,但并不以此为限。
请参阅图1至图7。图2至图7所绘示为本发明第一实施例的高压半导体组件的制作方法示意图。值得说明的是,本实施例的高压半导体组件101的制作方法可包括但并不限于下列步骤。首先,如图2所示,提供半导体基底10,两个隔离结构20形成于半导体基底10中且分别位于两个飘移区11中。隔离结构20可包括浅沟隔离,故隔离结构20的最上(topmost)表面(例如第一上表面20T)大体上与半导体基底10的上表面共平面或略高于半导体基底10的上表面,但并不以此为限。然后,在半导体基底10上形成一图案化屏蔽29,图案化屏蔽29覆盖各隔离结构20的至少一部分,且将两个隔离结构20之间的半导体基底10暴露出来。接着,如图3所示,在半导体基底10中形成一凹陷R,凹陷R可利用图案化屏蔽29搭配一凹陷制作工艺90例如一蚀刻制作工艺所形成,但并不以此为限。凹陷制作工艺90较佳地是对半导体基底10以及隔离结构20具有较佳的蚀刻选择比,也就是对半导体基底10的蚀刻率大于对隔离结构20,由此可避免对于隔离结构20造成破坏且也可使图案化屏蔽29的制作工艺容许范围(process window)变得较大,而凹陷R也可以自对准(self-aligned)的方式形成。
接着,如图3至图4所示,在半导体基底10的凹陷R中形成栅极介电层30,栅极介电层30可包括一氧化物层,且此氧化物层较佳可通过一氧化(oxidation)处理所形成,但并不以此为限。在一些实施例中,也可视需要通过其他方式例如薄膜沉积来形成栅极介电层30。值得说明的是,栅极介电层30的上表面(也就是图4中所示的第二上表面30T)于第二方向D2上低于隔离结构20的第一上表面20T,而凹陷R的深度DP较佳地是大于栅极介电层30的厚度TK,但并不以此为限。举例来说,当栅极介电层30为一经由氧化处理而形成的氧化物层时,栅极介电层30于形成时也会消耗部分的半导体基底10,故栅极介电层30的厚度TK(例如约为1100埃)也有可能略大于凹陷R的深度DP(例如约为1000埃),而栅极介电层30以及其第二上表面30T依然会低于隔离结构20的第一上表面20T。
然后,如图5至图7所示,在栅极介电层30上形成主栅极结构40G,且主栅极结构40G低于各隔离结构20的第一上表面20T。主栅极结构40G的制作方法可包括但并不限于下列步骤。首先,如图5所示,在栅极介电层30以及两个隔离结构20上形成一第一栅极材料层40。第一栅极材料层40的材料可包括具导电性的经掺杂的多晶硅或其他适合的导电材料。举例来说,当第一栅极材料层40为多晶硅层时,第一栅极材料层40可与其他半导体组件(例如逻辑区的低压半导体组件,未图标)的多晶硅栅极或/及用于取代金属栅极(replacement metalgate,RMG)制作工艺的虚置栅极(dummy gate)一并形成,但并不以此为限。然后,如图6所示,在第一栅极材料层40以及两个隔离结构20上形成一层间介电层,此层间介电层可包括间隙子51、接触蚀刻停止层52以及层间介电层53,但并不以此为限。此外,在两个隔离结构20外侧的飘移区11中分别形成源极/漏极区60。
接着,如图6至图7所示,将部分的位于两个隔离结构20上的第一栅极材料层40移除,用以于层间介电层(例如图7所示的间隙子51、接触蚀刻停止层52以及层间介电层53)中形成两个沟槽T,并形成主栅极结构40G。主栅极结构40G的至少部分的上表面(例如图7中所示的第三上表面40T)于第二方向D2上低于各隔离结构20的第一上表面20T。此外,在一些实施例中,为了确保沟槽T的形成状况,在移除部分的第一栅极材料层40时,也会将隔离结构20的第一上表面20T所处的水平面的下方的部分第一栅极材料层40移除,故使得主栅极结构40G的任何一部分均于第二方向D2上位于隔离结构20的第一上表面20T所处的水平面的下方,但并不以此为限。
如图7与图1所示,在主栅极结构40G的两端形成两个次栅极结构70G,各次栅极结构70G部分形成于主栅极结构40G上且部分形成于两个隔离结构20的其中一者上。在一些实施例中,两个次栅极结构70G可通过于沟槽T中填入一第二栅极材料层70所形成,而第二栅极材料层70可包括单层或多层的金属导电材料。举例来说,第二栅极材料层70可包括一功函数层以及一低电阻层。上述的功函数层可包括氮化钛(titanium nitride,TiN)、碳化钛(titanium carbide,TiC)、氮化钽(tantalum nitride,TaN)、碳化钽(tantalum carbide,TaC)、碳化钨(tungsten carbide,WC)、三铝化钛(titanium tri-aluminide,TiAl3)或氮化铝钛(aluminum titanium nitride,TiAlN),但不以此为限。上述的低电阻层可包括例如钨、铝、铜、铝化钛、钛或其他适合的低电阻材料。换句话说,主栅极结构40G的材料可不同于次栅极结构70G的材料,例如主栅极结构40G可包括一多晶硅栅极结构,而各次栅极结构70G可包括一金属栅极结构。
如上述的制作方法,两个次栅极结构70G的形成方式可被视为包括一取代金属栅极制作工艺,且次栅极结构70G可与其他半导体组件(例如逻辑区的低压半导体组件)的金属栅极一并通过此取代金属栅极制作工艺形成,由此达到制作工艺整合与简化的效果,但并不以此为限。更明确地说,两个次栅极结构70G可通过于沟槽T中填入第二栅极材料层70,并通过化学机械研磨(chemical mechanical polishing,CMP)制作工艺移除多余的第二栅极材料层70而形成。由于本实施例的高压半导体组件101的栅极由主栅极结构40G以及两个次栅极结构70G所组成,且仅有次栅极结构70G会受到化学机械研磨制作工艺处理影响,因此当高压半导体组件101的栅极需要有较长的长度(例如大于2微米,甚至大于4微米)时,主栅极结构40G的第一长度40L可直接调整而符合需求,而次栅极结构70G由于具有相对较小的第二长度70L(例如小于2微米),故即使次栅极结构70G的第二栅极材料层70需进行化学机械研磨制作工艺,也不易产生碟形下陷(dishing)的状况。此外,由于主栅极结构40G与栅极介电层30形成于半导体基底10的凹陷中而未高于隔离结构20的上表面,故即使当栅极介电层30因组件电性需求而具有较厚的厚度时,高压半导体组件101的栅极的高度(可被视为次栅极结构70G的高度)仍可大体上与其他半导体组件的金属栅极的高度相当,由此可解决高压半导体组件与其他半导体组件之间的高度差异状况,进而可避免相关的制作工艺问题而达到提升生产良率的效果。
请参阅图8。图8所绘示为本发明第二实施例的高压半导体组件的示意图。如图8所示,本实施例提供一种高压半导体组件102,包括半导体基底10、两个隔离结构20、栅极介电层30以及主栅极结构40G。两个隔离结构20设置于半导体基底10中,栅极介电层30设置于两个隔离结构20之间,且栅极介电层30低于各隔离结构20的一最上(topmost)表面(例如图8中所示的第一上表面20T)。主栅极结构40G设置于栅极介电层30以及两个隔离结构20上,且主栅极结构40G低于各隔离结构20的最上表面。主栅极结构40G可包括一多晶硅栅极结构或其他适合的导电材料所形成的栅极结构。主栅极结构40G的至少部分的上表面(例如图8中所示的第三上表面40T)低于各隔离结构20的最上表面(也就是第一上表面20T)。
与上述第一实施例的高压半导体组件不同的地方在于,本实施例的高压半导体组件102的栅极可仅由主栅极结构40G所构成而不具有上述第一实施例的次栅极结构。此外,在于半导体基底10中形成凹陷(图8未示)以于凹陷中形成栅极介电层30的凹陷制作工艺中(与上述图3至图4所示的状况相似),可通过调整凹陷制作工艺的蚀刻选择比而于两个隔离结构20靠近凹陷的一侧分别形成一缺口20N。因此,后续形成的主栅极结构40G可部分形成于两个隔离结构20的缺口20N中而因此可部分位于两个隔离结构20上,且使得主栅极结构40G的任何一部分(包括其最上表面)均于第二方向D2上位于隔离结构20的最上表面所处的水平面的下方。此外,高压半导体组件102可还包括接触蚀刻停止层52、层间介电层53以及两个源极/漏极区60。两个源极/漏极区60设置于半导体基底10中,且分别设置于两个隔离结构20的外侧。接触蚀刻停止层52设置于源极/漏极区60、隔离结构20以及主栅极结构40G上,而层间介电层53设置于接触蚀刻停止层52上。
由于本实施例的高压半导体组件102的栅极可仅由主栅极结构40G所构成,且主栅极结构40G低于隔离结构20的最上表面,故即使当栅极介电层30因组件电性需求而具有较厚的厚度时,高压半导体组件102的栅极也不会影响到其他半导体组件的制作工艺(例如取代金属栅极制作工艺),对于不同型态的半导体组件之间的制作工艺整合与简化具有正面的帮助。此外,由于主栅极结构40G可为一多晶硅栅极结构,而多晶硅材料进行化学机械研磨制作工艺时并不易产生碟形下陷的状况,故当高压半导体组件102的栅极需要有较长的长度(例如大于2微米,甚至大于4微米)时,可直接调整主栅极结构40G的第一长度40L而符合要求。
综上所述,在本发明的高压半导体组件以及其制作方法中,由于是利用于半导体基底中形成凹陷,再于凹陷中形成栅极介电层以及主栅极结构,故主栅极结构可低于半导体基底中的隔离结构的上表面。由此可改善因高压半导体组件所需厚度较厚的栅极介电层而导致高压半导体组件与其他半导体组件之间的高度差异状况,进而可避免相关的制作工艺问题而达到提升生产良率的效果。此外,本发明的高压半导体组件的制作方法可与其他半导体组件(例如低压半导体组件)的制作工艺整合,进而达到简化制作工艺以及降低生产成本等效果。
以上所述仅为本发明的较佳实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (18)
1.一种高压半导体组件,包括:
半导体基底;
两个隔离结构,设置于该半导体基底中;
栅极介电层,设置于该两个隔离结构之间,其中该栅极介电层低于各该隔离结构的一上表面;
主栅极结构,设置于该栅极介电层上,其中该主栅极结构低于各该隔离结构的该上表面;以及
两个次栅极结构,其中各该次栅极结构部分设置于该主栅极结构上且部分设置于该两个隔离结构的其中一者上,其中该两个次栅极结构与该主栅极结构直接相连。
2.如权利要求1所述的高压半导体组件,其中该主栅极结构的材料不同于该两个次栅极结构的材料。
3.如权利要求2所述的高压半导体组件,其中该主栅极结构包括一多晶硅栅极结构,且各该次栅极结构包括一金属栅极结构。
4.如权利要求1所述的高压半导体组件,其中该两个次栅极结构分别设置于该主栅极结构于一第一方向上的两端,且该主栅极结构于该第一方向上的长度大于各该次栅极结构于该第一方向上的长度。
5.如权利要求1所述的高压半导体组件,其中该主栅极结构的至少部分的上表面低于各该隔离结构的该上表面。
6.如权利要求1所述的高压半导体组件,还包括:
两个源极/漏极区,设置于该半导体基底中,且分别设置于该两个隔离结构的外侧。
7.一种高压半导体组件,包括:
半导体基底;
两个隔离结构,设置于该半导体基底中;
栅极介电层,设置于该两个隔离结构之间,其中该栅极介电层低于各该隔离结构的一最上表面;以及
主栅极结构,设置于该栅极介电层以及该两个隔离结构上,其中该主栅极结构低于各该隔离结构的该最上表面,且该主栅极结构直接设置于该两个隔离结构上。
8.如权利要求7所述的高压半导体组件,其中该主栅极结构包括一多晶硅栅极结构。
9.如权利要求7所述的高压半导体组件,其中该主栅极结构的至少部分的上表面低于各该隔离结构的该最上表面。
10.如权利要求7所述的高压半导体组件,还包括:
两个源极/漏极区,设置于该半导体基底中,且分别设置于该两个隔离结构的外侧。
11.一种高压半导体组件的制作方法,包括:
提供一半导体基底,其中两个隔离结构形成于该半导体基底中;
在该半导体基底中形成一凹陷;
在该半导体基底的该凹陷中形成一栅极介电层;
在该栅极介电层上形成一主栅极结构,其中该主栅极结构低于各该隔离结构的一上表面;以及
在该主栅极结构的两端形成两个次栅极结构,其中各该次栅极结构部分形成于该主栅极结构上且部分形成于该两个隔离结构的其中一者上,该两个次栅极结构与该主栅极结构直接相连。
12.如权利要求11所述的高压半导体组件的制作方法,其中该凹陷的深度大于该栅极介电层的厚度。
13.如权利要求11所述的高压半导体组件的制作方法,其中该主栅极结构的至少部分的上表面低于各该隔离结构的该上表面。
14.如权利要求11所述的高压半导体组件的制作方法,其中该主栅极结构包括一多晶硅栅极结构。
15.如权利要求11所述的高压半导体组件的制作方法,其中该主栅极结构的材料不同于该两个次栅极结构的材料。
16.如权利要求11所述的高压半导体组件的制作方法,其中该主栅极结构包括一多晶硅栅极结构,且各该次栅极结构包括一金属栅极结构。
17.如权利要求11所述的高压半导体组件的制作方法,其中该两个次栅极结构以一取代金属栅极制作工艺所形成。
18.如权利要求17所述的高压半导体组件的制作方法,其中形成该主栅极结构的步骤包括:
在该栅极介电层以及该两个隔离结构上形成一第一栅极材料层;
在该第一栅极材料层以及该两个隔离结构上形成一层间介电层;以及
将部分的位于该两个隔离结构上的该第一栅极材料层移除,用以于该层间介电层中形成两个沟槽,其中该两个次栅极结构通过于该两个沟槽中填入一第二栅极材料层所形成。
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US5342796A (en) * | 1991-05-28 | 1994-08-30 | Sharp Kabushiki Kaisha | Method for controlling gate size for semiconduction process |
US5814544A (en) * | 1994-07-14 | 1998-09-29 | Vlsi Technology, Inc. | Forming a MOS transistor with a recessed channel |
US9391196B1 (en) * | 2015-07-22 | 2016-07-12 | United Microelectronics Corp. | High-voltage metal-oxide-semiconductor transistor device and manufacturing method thereof |
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US4992388A (en) * | 1989-12-10 | 1991-02-12 | Motorola, Inc. | Short channel IGFET process |
US5480823A (en) * | 1995-01-19 | 1996-01-02 | United Microelectronics Corporation | Method of making high density ROM, without using a code implant |
JP3502531B2 (ja) | 1997-08-28 | 2004-03-02 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6465842B2 (en) * | 1998-06-25 | 2002-10-15 | Kabushiki Kaisha Toshiba | MIS semiconductor device and method of fabricating the same |
JP5466933B2 (ja) * | 2009-12-03 | 2014-04-09 | 株式会社ジャパンディスプレイ | 薄膜トランジスタおよびその製造方法 |
US20150236151A1 (en) * | 2014-02-18 | 2015-08-20 | General Electric Company | Silicon carbide semiconductor devices, and methods for manufacturing thereof |
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US5342796A (en) * | 1991-05-28 | 1994-08-30 | Sharp Kabushiki Kaisha | Method for controlling gate size for semiconduction process |
US5814544A (en) * | 1994-07-14 | 1998-09-29 | Vlsi Technology, Inc. | Forming a MOS transistor with a recessed channel |
US9391196B1 (en) * | 2015-07-22 | 2016-07-12 | United Microelectronics Corp. | High-voltage metal-oxide-semiconductor transistor device and manufacturing method thereof |
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US20210119014A1 (en) | 2021-04-22 |
US10629697B2 (en) | 2020-04-21 |
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