CN110120420B - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN110120420B
CN110120420B CN201810112699.9A CN201810112699A CN110120420B CN 110120420 B CN110120420 B CN 110120420B CN 201810112699 A CN201810112699 A CN 201810112699A CN 110120420 B CN110120420 B CN 110120420B
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layer
region
gate
semiconductor
doped region
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CN110120420A (zh
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李信宏
陈冠全
李年中
李文芳
王智充
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United Microelectronics Corp
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Priority to US16/460,813 priority patent/US10535734B2/en
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Abstract

本发明公开一种半导体元件及其制造方法，该半导体元件包括半导体层，有第一元件区域与第二元件区域。浅沟槽隔离结构在所述半导体层中，位于所述第一元件区域与所述第二元件区域的边缘。第一绝缘层与第二绝缘层在所述半导体层上，分别位于所述第一元件区域与所述第二元件区域。第一栅极结构位于所述第一绝缘层上。源极区域与漏极区域在所述半导体层中，位于所述第一栅极结构的两侧。栅极掺杂区域在所述半导体层的所述第二元件区域的表面区域，当作第二栅极结构。通道层位于所述第二绝缘层上。源极层与漏极层，在所述浅沟槽隔离结构上，位于所述通道层的两侧。

Description

半导体元件及其制造方法
技术领域
本发明涉及一种半导体元件技术，且特别是涉及晶体管半导体元件的制造技术。
背景技术
数字的电子装置，例如显示器，电视，相机等等，其都会包含集成电路来执行所设计的功能。集成电路一般也会包含大量的晶体管来完成所设计的电路。
基于电子装置有更大的功能以及较小尺寸的需求，多种晶体管的结构已被提出，其中除了以硅基板为基础的晶体管结构外，也还包含其他例如薄膜晶体管的结构，或是鳍式晶体管等等的结构。
也就是说，基于制造与尺寸的考虑，半导体的晶体管的设计式继续在研发，以因应不同功能的电子装置的制造。
发明内容
依据一实施例，本发明提出一种半导体元件，包括半导体层，其有第一元件区域与第二元件区域。浅沟槽隔离结构在所述半导体层中，位于所述第一元件区域与所述第二元件区域的边缘。第一绝缘层与第二绝缘层在所述半导体层上，分别位于所述第一元件区域与所述第二元件区域。第一栅极结构位于所述第一绝缘层上。源极区域与漏极区域在所述半导体层中，位于所述第一栅极结构的两侧。栅极掺杂区域在所述半导体层的所述第二元件区域的表面区域，当作第二栅极结构。通道层位于所述第二绝缘层上。源极层与漏极层在所述浅沟槽隔离结构上，位于所述通道层的两侧。
依据一实施例，在所述的半导体元件，还包括隔离掺杂区域，在所述半导体层中，位于所述栅极掺杂区域下方，以隔离所述栅极掺杂区域，其中所述栅极掺杂区域包含第一导电型掺子，所述隔离掺杂区域包含与所述第一导电型掺子不同的第二导电型掺子。
依据一实施例，在所述的半导体元件，所述第一栅极结构、所述源极层与所述漏极层是由一取代虚拟栅极工艺所形成。
依据一实施例，在所述的半导体元件，所述取代虚拟栅极工艺包括:形成虚拟材料层于所述第一绝缘层与所述第二绝缘层上；定义所述虚拟材料层，以形成第一部分于所述第一绝缘层上及第二部分于所述第二绝缘层上；形成内介电层，覆该所述虚拟材料层的所述第一部分与所述第二部分；研磨所述内介电层，以暴露出所述虚拟材料层；移除所述虚拟材料层的所述第一部分得到第一开口，以及在所述第二部分的两边缘区域得到第二开口，其中剩余的所述第二部分当作所述通道层；以及在所述第一开口形成所述第一栅极结构，以及在所述第二开口形成所述源极层与所述漏极层。
依据一实施例，在所述的半导体元件，所述虚拟材料层的材料包括多晶硅、非晶硅、GaN、氧化铟镓锌、ZnO、或是氧化物半导体材料。
依据一实施例，在所述的半导体元件，所述第一栅极结构、所述源极层、所述漏极层是相同材料，包含Al、W、TiN或TaN。
依据一实施例，在所述的半导体元件，所述半导体层是硅基板的顶部部分，或是基板上的硅外延层。
依据一实施例，在所述的半导体元件，位于所述第二元件区域的所述栅极掺杂区域有一部分，在水平方向延伸出所述通道层。
依据一实施例，在所述的半导体元件，位于所述第二元件区域的所述通道层与位于所述第一元件区域的所述第一栅极结构是同高度。
依据一实施例，在所述的半导体元件，还包括第一间隙壁位于所述第一栅极结构的侧壁，第二间隙壁位于所述源极层与所述漏极层的外侧壁。
依据一实施例，在所述的半导体元件，所述通道层的材料包含多晶硅、非晶硅、GaN、氧化铟镓锌、ZnO、或是氧化物半导体材料。
依据一实施例，本发明提出一种制造半导体元件的方法，包括提供半导体层，半导体层有第一元件区域与第二元件区域。浅沟槽隔离结构形成在所述半导体层中，位于所述第一元件区域与所述第二元件区域的边缘。栅极掺杂区域形成在所述半导体层的所述第二元件区域的表面区域，当作第二栅极结构，所述栅极掺杂区域具有第一导电型掺子。第一绝缘层与第二绝缘层形成在所述半导体层上，分别位于所述第一元件区域与所述第二元件区域。虚拟材料层形成在所述第一绝缘层与所述第二绝缘层上。进行取代虚拟栅极工艺，以形成第一栅极结构在第一元件区域以及源/漏极层在第二元件区域。其中，所述源/漏极层是形成在所述第二绝缘层的所述虚拟材料层的两侧部分上。所述虚拟材料层的剩余部分当作通道层。在所述半导体层中的所述栅极掺杂区域当作第二栅极结构。
依据一实施例，在所述的制造半导体元件的方法，还包括形成隔离掺杂区域，在所述半导体层中，位于所述栅极掺杂区域下方，以隔离所述栅极掺杂区域，其中所述栅极掺杂区域包含第一导电型掺子，所述隔离掺杂区域包含与所述第一导电型掺子不同的第二导电型子。
依据一实施例，在所述的制造半导体元件的方法，所述取代虚拟栅极工艺包括:定义所述虚拟材料层，以形成第一部分于所述第一绝缘层上及第二部分于所述第二绝缘层上；形成内介电层，覆该所述虚拟材料层的所述第一部分与所述第二部分；研磨所述内介电层，以暴露出所述虚拟材料层；移除所述虚拟材料层的所述第一部分得到第一开口，以及在所述第二部分的两边缘区域得到第二开口，其中剩余的所述第二部分当作所述通道层；以及在所述第一开口形成所述第一栅极结构，以及在所述第二开口形成所述源极层与所述漏极层。
依据一实施例，在所述的制造半导体元件的方法，所述第一栅极结构、所述源极层、所述漏极层是相同材料，包含Al、W、TiN或TaN。
依据一实施例，在所述的制造半导体元件的方法，所述半导体层是硅基板的顶部部分，或是基板上的硅外延层。
依据一实施例，在所述的制造半导体元件的方法，位于所述第二元件区域的所述栅极掺杂区域有一部分，在水平方向延伸出所述通道层。
依据一实施例，在所述的制造半导体元件的方法，位于所述第二元件区域的所述通道层与位于所述第一元件区域的所述第一栅极结构是同高度。
依据一实施例，在所述的制造半导体元件的方法，还包括形成第一间隙壁在所述第一栅极结构的侧壁，以及形成第二间隙壁在所述源极层与所述漏极层的外侧壁。
依据一实施例，在所述的制造半导体元件的方法，所述通道层的材料包含多晶硅、非晶硅、GaN、氧化铟镓锌、ZnO、或是氧化物半导体材料。
附图说明
包含附图以便进一步理解本发明，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例，并与描述一起用于解释本发明的原理。
图1～图7为本发明一实施例，绘示制造半导体元件的方法的流程的半导体剖面结构示意图；以及
图8为本发明一实施例，绘示以基板当作栅极的晶体管结构的上视示意图。
附图标号说明
50、60:元件区域
100:基板
102:浅沟槽隔离结构
104a:掺杂区域
104b:栅极掺杂区域
106:隔离掺杂区域
108、110:绝缘层
112a、112b:虚拟材料层
114a、114b:盖冒层
116:间隙壁
118:硬介电层
120:介电层
121:蚀刻掩模层
122:源/漏极区域
126、128:开口
130:阻障层
132:阻障层
134:源/漏极层
136:栅极结构
138:内介电层
140:接触插塞
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在附图和描述中用来表示相同或相似部分。
在本发明中，在制造以基板为基础的晶体管时，也可以同时制造薄膜晶体管，其中此薄膜晶体管的栅极结构是由基板提供。此基板例如是硅基板或是半导体的外延层(semiconductor epitaxial layer)。对基板利用适当的掺杂浓度，以形成的掺杂区域当作栅极结构，这种的栅极结构也可以称为基板栅极(substrate gate)，其表示栅极结构是由基板的一掺杂区域来形成。
以下举一些实施例来说明本发明，但是本发明不限于所举的多个实施例。
图1～图7为本发明一实施例，绘示制造半导体元件的方法的流程的半导体剖面结构示意图。
参阅图1，基板100被提供当作制造的基础。基板100例如可以是硅基板或是半导体的外延层。在基板100可以有第一元件区域50与第二元件区域60。第一元件区域50用来制造一般的晶体管，而第一元件区域60在相容的制造流程中，有可以制造本发明提出的基板栅极的晶体管。
浅沟槽隔离结构102形成在基板100中，位于第一元件区域50与第二元件区域60的边缘，以隔离要制造的晶体管。在基板100中对应第一元件区域50与第二元件区域60分别先形成掺杂区域104a与栅极掺杂区域104b。对于第一元件区域50掺杂区域104a，其是对应晶体管导电型的基板掺杂区域，后续会形成晶体管所需要的源/漏极区域。对于第二元件区域60的栅极掺杂区域104b，在后续完成制造后，是当作晶体管的栅极结构来使用。另外，由于栅极掺杂区域104b是当作晶体管的栅极结构，因此在隔离的考虑下，可以更形成隔离掺杂区域106在其下方。栅极掺杂区域104b与隔离掺杂区域106是不同导电型的掺杂。
参阅图2，在第一元件区域50与第二元件区域60分别形成绝缘层108、110，其分别当作栅极绝缘层的功用。由于第一元件区域50是制造一般的晶体管，其操作电压是在低压操作范围，因此绝缘层108不需要大厚度。对于第二元件区域60的晶体管，其例如可以是高电压操作的高电压晶体管体，其绝缘层110需要足够大。然而，第二元件区域60的晶体管有可以是一般的低压晶体管，不限于高电压晶体管。因此，绝缘层108与绝缘层110可以相同或是不相同，其依照实际设计来决定。
参阅图3，先形成虚拟材料层在绝缘层108、110以及浅沟槽隔离结构102上，通过光刻蚀刻的定义工艺，可以形成虚拟材料层112a、112b分别在第一元件区域50与第二元件区域60上。在虚拟材料层112a、112b表面依实际制造的需要，也可以其表面有掩模层114a、114b。
在此，虚拟材料层112a是虚拟栅极，其在后续的制造过程中会被移除，再以实际的栅极材料取代。然而，虚拟材料层112b于后续的制造，其对应栅极掺杂区域104b是要当作晶体管的通道层的功用。配合通道层的功用，虚拟材料层112a的材料例如可以是多晶硅、非晶硅、GaN、氧化铟镓锌(IGZO)、ZnO、或是氧化物半导体材料。
参阅图4，依照在第一元件区域5形成一般的晶体管，其会在虚拟材料层112a的两侧壁形成间隙壁116以及在上表面形成盖冒层114a，同时在虚拟材料层112b的两侧壁也形成间隙壁116以及在上表面形成盖冒层114b。另外，也可以全面形成共形的硬介电层118。其后，在形成介电层120，覆盖过虚拟材料层112a、112b。
于此，虚拟材料层112a是虚拟栅极。对应的源/漏极区域122，可以先形成在基板100中，位于虚拟材料层112a的两侧。
参阅图5，对内介电层120进行研磨工艺，直到虚拟材料层112a、112b被暴露出来。于此，盖冒层114a以及硬介电层118的一部分也被移除。就整体来说，盖冒层114a、间隙壁116、硬介电层118、介电层120可以统称为内介电层，不需要特定的限制。
参阅图6，在被暴露的虚拟材料层112b上形成蚀刻掩模层121，其仅覆盖在中间区域，因此虚拟材料层112b的边缘区域维持暴露。此边缘区域是预留后续要形成源/漏极层的位置。使用此蚀刻掩模层121，例如进行回蚀刻(etching back)工艺，将虚拟材料层112b的暴露部分以及虚拟材料层112a移除，得到开口128与开口126。
参阅图7，在开口128形成栅极结构136。另外，依照实际需要，栅极结构136也例如可以再包含阻障层132，本发明的栅极结构136不限定于特定结构。对于开口126，其是预计要形成源/漏极层134在虚拟材料层112b的两侧边，其中如前述，虚拟材料层112b在第二元件区域60是提供通道层的结构给基板栅极式(substrate-gate)的晶体管。
从减少制造成本来考虑，在开口126中的源/漏极层134，可以与在开口128中栅极结构136在同一个步骤完成。同样地，源/漏极层134也可以含有阻障层130。如此可以不需要另外的制造步骤来形成源/漏极层134。然而本发明不限定于所举的实施例。
在栅极结构136与源/漏极层134同时形成的方式下，其材料是相同，例如可以包含Al、W、TiN或TaN。
在此，在前述图3到图5的制造流程，其可以统称为取代虚拟栅极工艺，对于第一元件区域50的晶体管，其先形成虚拟栅极，其后移除虚拟栅极，再以实际的栅极结构136取代。在此过程中，对于第二元件区域60的晶体管可以同时完成源/漏极层134的形成。
完成第一元件区域50与第二元件区域60的晶体管后，再后续的制造流程例如可以再利用内介电层138完成各种接触插塞140的制造。本发明不限于特定的后续制造流程。
图8为本发明一实施例，绘示以基板当作栅极的晶体管结构的上视示意图。对于第二元件区域60的晶体管，栅极掺杂区域104b是当作栅极结构，需要施加操作电压。因此，从上视的布局结构，栅极掺杂区域104b会延伸出当作通道层的虚拟材料层112b。从图8中的切割线I-I所对应的剖面结构，是在图7中的第二元件区域60的结构。栅极掺杂区域104b是由基板100的半导体层所提供，位于下方位置。虚拟材料层112b的通导层以及源/漏极层134是在上方位置。
本发明提出基板栅极式的晶体管，其可制造流程也相容于其他晶体管的制造，不会实质增加制造的困难度，而提供晶体管结构的另一个新颖的选择。本发明的基板栅极式的晶体管也可以用来制造高电压晶体管。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (20)

1.一种半导体元件，其特征在于包括:
半导体层，有第一元件区域与第二元件区域；
浅沟槽隔离结构，在所述半导体层中，位于所述第一元件区域与所述第二元件区域的边缘；
第一绝缘层与第二绝缘层，在所述半导体层上，分别位于所述第一元件区域与所述第二元件区域；
第一栅极结构，位于所述第一绝缘层上；
源极区域与漏极区域，在所述半导体层中，位于所述第一栅极结构的两侧；
栅极掺杂区域，在所述半导体层的所述第二元件区域的表面区域，当作第二栅极结构；
通道层，位于所述第二绝缘层上；以及
源极层与漏极层，在所述浅沟槽隔离结构上，位于所述通道层的两侧。
2.根据权利要求1所述的半导体元件，其特征在于，还包括隔离掺杂区域，在所述半导体层中，位于所述栅极掺杂区域下方，以隔离所述栅极掺杂区域，其中所述栅极掺杂区域包含第一导电型掺子，所述隔离掺杂区域包含与所述第一导电型掺子不同的第二导电型掺子。
3.根据权利要求1所述的半导体元件，其特征在于，所述第一栅极结构、所述源极层与所述漏极层是由一取代虚拟栅极工艺所形成。
4.根据权利要求3所述的半导体元件，其特征在于，所述取代虚拟栅极工艺包括:
形成虚拟材料层于所述第一绝缘层与所述第二绝缘层上；
定义所述虚拟材料层，以形成第一部分于所述第一绝缘层上及第二部分于所述第二绝缘层上；
形成内介电层，覆该所述虚拟材料层的所述第一部分与所述第二部分；
研磨所述内介电层，以暴露出所述虚拟材料层；
移除所述虚拟材料层的所述第一部分得到第一开口，以及在所述第二部分的两边缘区域得到第二开口，其中剩余的所述第二部分当作所述通道层；以及
在所述第一开口形成所述第一栅极结构，以及在所述第二开口形成所述源极层与所述漏极层。
5.根据权利要求4所述的半导体元件，其特征在于，所述虚拟材料层的材料包括多晶硅、非晶硅、GaN、氧化铟镓锌或是ZnO。
6.根据权利要求1所述的半导体元件，其特征在于，所述第一栅极结构、所述源极层、所述漏极层是相同材料，包含Al、W、TiN或TaN。
7.根据权利要求1所述的半导体元件，其特征在于，所述半导体层是硅基板的顶部部分，或是基板上的硅外延层。
8.根据权利要求1所述的半导体元件，其特征在于，位于所述第二元件区域的所述栅极掺杂区域有一部分，在水平方向延伸出所述通道层。
9.根据权利要求1所述的半导体元件，其特征在于，位于所述第二元件区域的所述通道层与位于所述第一元件区域的所述第一栅极结构是同高度。
10.根据权利要求1所述的半导体元件，其特征在于，还包括:
第一间隙壁，位于所述第一栅极结构的侧壁；以及
第二间隙壁，位于所述源极层与所述漏极层的外侧壁。
11.根据权利要求1所述的半导体元件，其特征在于，所述通道层的材料包含多晶硅、非晶硅、GaN、氧化铟镓锌或是ZnO。
12.一种制造半导体元件的方法，其特征在于包括:
提供半导体层，半导体层有第一元件区域与第二元件区域；
形成浅沟槽隔离结构，在所述半导体层中，位于所述第一元件区域与所述第二元件区域的边缘；
形成栅极掺杂区域，在所述半导体层的所述第二元件区域的表面区域，当作第二栅极结构，所述栅极掺杂区域具有第一导电型掺子；
形成第一绝缘层与第二绝缘层，在所述半导体层上，分别位于所述第一元件区域与所述第二元件区域；
形成虚拟材料层在所述第一绝缘层与所述第二绝缘层上；以及
进行取代虚拟栅极工艺，以形成第一栅极结构在第一元件区域以及源极层与漏极层在第二元件区域，
其中所述源极层与漏极层是形成在所述第二绝缘层的所述虚拟材料层的两侧部分上，其中所述虚拟材料层的剩余部分当作通道层，
其中在所述半导体层中的所述栅极掺杂区域当作第二栅极结构。
13.根据权利要求12所述的制造半导体元件的方法，其特征在于，还包括形成隔离掺杂区域，在所述半导体层中，位于所述栅极掺杂区域下方，以隔离所述栅极掺杂区域，其中所述栅极掺杂区域包含第一导电型掺子，所述隔离掺杂区域包含与所述第一导电型掺子不同的第二导电型掺子。
14.根据权利要求12所述的制造半导体元件的方法，其特征在于，所述取代虚拟栅极工艺包括:
定义所述虚拟材料层，以形成第一部分于所述第一绝缘层上及第二部分于所述第二绝缘层上；
形成内介电层，覆该所述虚拟材料层的所述第一部分与所述第二部分；
研磨所述内介电层，以暴露出所述虚拟材料层；
移除所述虚拟材料层的所述第一部分得到第一开口，以及在所述第二部分的两边缘区域得到第二开口，其中剩余的所述第二部分当作所述通道层；以及
在所述第一开口形成所述第一栅极结构，以及在所述第二开口形成所述源极层与所述漏极层。
15.根据权利要求12所述的制造半导体元件的方法，其特征在于，所述第一栅极结构、所述源极层、所述漏极层是相同材料，包含Al、W、TiN或TaN。
16.根据权利要求12所述的制造半导体元件的方法，其特征在于，所述半导体层是硅基板的顶部部分，或是基板上的硅外延层。
17.根据权利要求12所述的制造半导体元件的方法，其特征在于，位于所述第二元件区域的所述栅极掺杂区域有一部分，在水平方向延伸出所述通道层。
18.根据权利要求12所述的制造半导体元件的方法，其特征在于，位于所述第二元件区域的所述通道层与位于所述第一元件区域的所述第一栅极结构是同高度。
19.根据权利要求12所述的制造半导体元件的方法，其特征在于，还包括:
形成第一间隙壁，位于所述第一栅极结构的侧壁；以及
形成第二间隙壁，位于所述源极层与所述漏极层的外侧壁。
20.根据权利要求12所述的制造半导体元件的方法，其特征在于，所述通道层的材料包含多晶硅、非晶硅、GaN、氧化铟镓锌或是ZnO。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006462A (ko) * 1996-06-17 1998-03-30 모리시다 요이치 반도체 장치 및 그 제조방법
CN1956195A (zh) * 2005-10-28 2007-05-02 松下电器产业株式会社 半导体装置及其制造方法
CN102254822A (zh) * 2010-05-18 2011-11-23 茂达电子股份有限公司 制造功率半导体器件的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5686334A (en) * 1996-06-10 1997-11-11 Chartered Semiconductor Manufacturing Pte Ltd Method of making SRAM cell with thin film transistor using two polysilicon layers
US8477006B2 (en) * 2011-08-30 2013-07-02 United Microelectronics Corp. Resistor and manufacturing method thereof
US9852952B2 (en) * 2015-10-28 2017-12-26 United Microelectronics Corp. Semiconductor device and method for fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006462A (ko) * 1996-06-17 1998-03-30 모리시다 요이치 반도체 장치 및 그 제조방법
CN1956195A (zh) * 2005-10-28 2007-05-02 松下电器产业株式会社 半导体装置及其制造方法
CN102254822A (zh) * 2010-05-18 2011-11-23 茂达电子股份有限公司 制造功率半导体器件的方法

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