TW202324504A - 形成半導體結構的方法 - Google Patents
形成半導體結構的方法 Download PDFInfo
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- TW202324504A TW202324504A TW111136109A TW111136109A TW202324504A TW 202324504 A TW202324504 A TW 202324504A TW 111136109 A TW111136109 A TW 111136109A TW 111136109 A TW111136109 A TW 111136109A TW 202324504 A TW202324504 A TW 202324504A
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Abstract
一種方法,包括:結合一第一晶圓至一第二晶圓;在第一晶圓上執行一修整製程,且沉積一側壁保護層,上述側壁保護層接觸第一晶圓的一側壁。沉積側壁保護層包括沉積一高密度材料,與第一晶圓的側壁接觸。側壁保護層具有高於氧化矽的密度的一密度。上述方法更包括移除側壁保護層與第一晶圓重疊的一水平部分;以及形成一互連結構在第一晶圓上方。互連結構電性連接至第一晶圓中的複數個積體電路裝置。
Description
本揭露實施例係有關於一種形成半導體結構的方法,特別係有關於一種形成側壁保護層的方法。
載體晶圓通常用於積體電路的封裝中作為支撐機構。例如,當形成具有貫穿裝置晶圓基板的貫通孔的裝置晶圓時,裝置晶圓與載體晶圓結合,從而可以使裝置晶圓變薄,並且可以在基板的背側形成數個電連接件。
根據本揭露的一些實施例,一種方法包括:結合一第一晶圓至一第二晶圓;在第一晶圓上執行一修整製程,其中第一晶圓的一邊緣部分被移除;沉積一側壁保護層,上述側壁保護層接觸第一晶圓的一側壁,其中沉積側壁保護層包括沉積一高密度材料,與第一晶圓的側壁接觸,且其中側壁保護層具有高於氧化矽的密度的一密度;移除側壁保護層與第一晶圓重疊的一水平部分;以及形成一互連結構在第一晶圓上方,其中互連結構電性連接至第一晶圓中的複數個積體電路裝置。
根據本揭露的一些實施例,一種方法包括:結合一裝置晶圓至一載體晶圓上方;薄化裝置晶圓的一半導體基板;修整裝置晶圓,其中修整裝置晶圓的一邊緣部分;沉積一側壁保護層在裝置晶圓及載體晶圓上,其中沉積側壁保護層包括沉積一含金屬層;顯露裝置晶圓的一頂部表面;以及形成一互連結構在裝置晶圓上方,其中互連結構電性連接至裝置晶圓中的複數個積體電路裝置。
根據本揭露的一些實施例,一種方法包括:結合一裝置晶圓至一載體晶圓上方,其中裝置晶圓中的一第一介電層結合至載體晶圓中的一第二介電層;修整裝置晶圓,其中修整裝置晶圓中的一第一基板的一部分,且載體晶圓中的一第二基板的一頂部表面顯露;沉積一側壁保護層在裝置晶圓及載體晶圓上,其中沉積側壁保護層包括沉積選自金屬氧化物、金屬氮化物、金屬碳化物及上述之組合中的一材料;從裝置晶圓及載體晶圓移除側壁保護層的複數個水平部分;移除第二基板的至少一部分;以及附接一封裝構件至裝置晶圓以形成一晶圓級封裝,其中側壁保護層存在於晶圓級封裝中。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例,以簡化說明。當然,這些特定的範例並非用以限定。例如,若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方,即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例,亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間,而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外,以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的,並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
此外,與空間相關用詞,例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞,係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外,這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位),則在此使用的空間相關詞也可依此相同解釋。
提供一種晶圓結合製程及封裝的形成。根據本揭露的一些實施例,一裝置晶圓結合至一載體晶圓。將裝置晶圓薄化(thinned),隨後是邊緣修整(trimming)製程。一側壁保護層形成在裝置晶圓的側壁上。根據一些實施例,利用高密度的材料形成側壁保護層,上述材料的密度高於氧化矽。高密度的材料具有良好的阻隔能力,用於防止有害化學品及濕氣貫穿。透過利用高密度的側壁保護層,減少了裝置晶圓中低介電常數介電層和低介電常數介電層中金屬特徵的劣化(degradation),且避免裝置劣化。本文討論的實施例提供示例以實現或使用本揭露的標的,且本技術領域中具有通常知識者將輕易地理解可以進行的修改,同時保持在不同實施例的預期範圍內。在各個視圖和說明性實施例中,相似的參考符號用於表示相似的元件。儘管可以將方法實施例討論為以特定順序執行,但是其他方法實施例可以任何合理的順序執行。
第1圖至第11圖繪示根據本揭露一些實施例,裝置晶圓結合至載體晶圓,以及裝置晶圓的背側上的背側互連結構形成的中間階段的剖面圖。對應的製程亦示意性地表現在第17圖所示的流程圖中。
參照第1圖,形成晶圓20。根據一些實施例,晶圓20為一載體晶圓,因此在下文中稱為載體晶圓20。載體晶圓20在頂視圖中可具有圓的形狀。根據一些實施例,載體晶圓20包括基板22。基板22可與裝置晶圓30中的基板32(將在後續討論)以相同材料形成,使得在後續的封裝製程中,因為載體晶圓20與裝置晶圓30之間熱膨脹係數(Coefficients of Thermal Expansion,CTE)值的差異所造成的翹曲可被減少。基板22可由矽形成或包括矽,而同時亦可利用其他材料例如:陶瓷、玻璃、矽酸鹽玻璃等。根據一些實施例,整個基板22由均質的材料形成,其中不包含其他不同於均質材料的材料。舉例來說,整個載體晶圓20可由矽(摻雜或未摻雜)形成,且其中沒有金屬區域、介電區域等。
根據一些替代性實施例,晶圓20為裝置晶圓,在其中包括主動裝置(例如:電晶體)及/或被動裝置(例如:電容器、電阻器、電感器及/或類似物)。當晶圓20為裝置晶圓時,晶圓20可為未鋸割(un-sawed)晶圓,包括連續延伸至晶圓中所有裝置晶粒中的半導體基板,或可為重建(reconstructed)晶圓,包括分離的裝置晶粒,上述裝置晶粒封裝在一密封劑(例如:模製化合物)中。
結合層24沉積在基板22上。各自的製程繪示如第17圖所示的流程圖200中的製程202。根據一些實施例,結合層24由介電材料形成或包括介電材料,可為以矽為基底的介電材料,例如:二氧化矽(SiO
2)、氮化矽、氮氧化矽、碳氮氧化矽、碳化矽、碳氮化矽等、或上述之組合。根據一些實施例,結合層24具有介於約1000埃至約10000埃之間的厚度。
根據本揭露的一些實施例,利用高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition ,HDPCVD)、電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition ,PECVD)、化學氣相沉積(Chemical Vapor Deposition ,CVD)、低壓化學氣相沉積(Low-Pressure Chemical Vapor Deposition ,LPCVD)、原子層沉積(Atomic Layer deposition ,ALD)等來形成結合層24。
根據一些實施例,結合層24物理性接觸基板22。根據一些替代性實施例,載體晶圓20在結合層24與基板22之間包括複數層(圖未示)。舉例來說,可具有以氧化物為基底的層,由以氧化物為基底的材料(亦可為以氧化矽為基底)例如:氧化矽、磷矽酸鹽玻璃(phosphor-silicate glass,PSG)、硼矽玻璃(borosilicate glass,BSG)、摻硼磷矽酸鹽玻璃(boron-doped phospho silicate glass,BPSG)、摻氟矽酸鹽玻璃(fluorine-doped silicate glass,FSG)等形成。亦可具有以氮化物為基底的層,由氮化矽形成或包括氮化矽,同時亦可由其他材料形成或包括其他材料,其他材料例如:氮氧化矽(SiON)。根據本揭露的一些實施例,基板22與結合層24之間的層可利用電漿增強化學氣相沉積、化學氣相沉積、低壓化學氣相沉積、原子層沉積等形成。在結合層24與基板22之間亦可形成有定位標記。定位標記可形成為金屬塞,金屬塞可透過鑲嵌製程形成。
再參照第1圖,形成裝置晶圓30。裝置晶圓30可為未鋸割晶圓,且第2圖所示的結合製程為晶圓至晶圓的結合製程。根據一些實施例,裝置晶圓30包括基板32。可有貫通基板的通孔(圖未示)從前側(繪示的頂部側)延伸至基板32中。根據一些替代性實施例,沒有貫通孔在此階段形成,且貫通孔在第8圖所示的製程中形成。基板32可為半導體基板,例如矽基板。根據一些其他實施例,基板32可包括其他半導體材料例如:矽鍺、摻雜碳的矽等。基板32可為塊體基板,或具有層狀結構,舉例來說,包括一矽基板以及在矽基板上方的矽鍺層。
根據一些實施例,裝置晶圓30包括複數個裝置晶粒,可包括邏輯晶粒、記憶體晶粒、輸入輸出晶粒、積體被動元件(Integrated Passive Devices,IPDs)等、或上述之組合。舉例來說,裝置晶圓30中的邏輯裝置晶粒可為中央處理單元(Central Processing Unit,CPU)晶粒、圖形處理單元(Graphic Processing Unit,GPU)晶粒、行動應用晶粒、微控制器單元(Micro Control Unit,MCU)晶粒、基頻(BaseBand,BB)晶粒、應用處理器(Application processor,AP)晶粒等。裝置晶圓30中的記憶體晶粒可包括靜態隨機存取記憶體(Static Random-Access Memory,SRAM)晶粒、動態隨機存取記憶體(Dynamic Random-Access Memory,DRAM)晶粒等。裝置晶圓30可為簡單的裝置晶圓,包括連續地延伸通過裝置晶圓30的半導體基板,或可為包括封裝在其中的裝置晶粒的重建晶圓、包括整合為一系統的複數個積體電路(或裝置晶粒)的單晶片系統(System-on-Chip,SoC)晶粒等。
根據本揭露的一些實施例,積體電路裝置34形成在半導體基板32的頂部表面上。範例積體電路裝置34可包括互補性金屬氧化半導體(Complementary Metal-Oxide Semiconductor,CMOS)電晶體、電阻器、電容器、二極體及/或類似物。積體電路裝置34的細節在本此未繪示。根據一些替代性實施例,裝置晶圓30用於形成中介層,其中基板32可為半導體基板或介電基板。
層間介電質(Inter-Layer Dielectric,ILD)36形成在基板32上方且填充積體電路裝置34中電晶體的閘極堆疊(圖未示)之間的空間。根據一些範例實施例,層間介電質36由氧化矽、磷矽酸鹽玻璃(PSG)、硼矽玻璃(BSG)、摻硼磷矽酸鹽玻璃(BPSG)、摻氟矽酸鹽玻璃(FSG)等形成或包括上述材料。層間介電質36可利用旋塗、流動式化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)、化學氣相沉積(CVD)等形成。根據本揭露的一些實施例,層間介電質36利用例如電漿增強化學氣相沉積、低壓化學氣相沉積等沉積方法形成。
接觸塞38形成在層間介電質36中,且用以將積體電路裝置34電性連接至上方的金屬線及通孔。根據本揭露的一些實施例,接觸塞38由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、上述之合金及/或上述之多層的導電材料形成。接觸塞38的形成可包括形成接觸開口在層間介電質36中、填充一(些)導電材料至接觸開口中、及執行平坦化製程(例如:化學機械平坦化(Chemical Mechanical Polish,CMP)製程)以使接觸塞38的頂部表面與層間介電質36的頂部表面齊平。
在層間介電質36及接觸塞38的上方放置有互連結構40。互連結構40包括金屬線42及通孔44,形成在介電層46中。介電層46在下文中可包括金屬層間介電質(Inter-Metal Dielectric,IMD)層。根據本揭露的一些實施例,一些介電層46是由低介電常數介電材料形成,具有小於約3.0的介電常數(k值)。介電層46可由含碳的低介電常數介電材料、氫矽酸鹽(Hydrogen SilsesQuioxane,HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane,MSQ)等形成或包括上述材料。根據本揭露的一些實施例,介電層46的形成包括沉積含生孔劑(porogen)的介電材料,然後執行硬化製程以去除生孔劑,因此留下的介電層46為有孔的。根據本揭露的一些替代性實施例,一些或所有介電層46是由非低介電常數介電材料形成,例如:氧化矽、碳化矽(SiC)、碳氮化矽(SiCN)、氧碳氮化矽(SiOCN)等。蝕刻停止層(圖未示)形成在介電層46之間,為了簡化目的而未圖示,蝕刻停止層可由碳化矽、氮化矽、氧氮化矽、氧化鋁、氮化鋁等、或上述之多層形成。
金屬線42及通孔44形成在介電層46中。相同高度的金屬線42在下文中集合地稱為金屬層。根據本揭露的一些實施例,互連結構40包括複數個金屬層,透過通孔44互連。金屬層間介電質層的數量是基於佈線需求而決定。舉例來說,可具有5至15之間的金屬層間介電質層。
金屬線42及通孔44可由銅或銅合金形成,且亦可由其他金屬形成。形成製程可包括單鑲嵌製程及雙鑲嵌製程。在一範例單鑲嵌製程中,先在其中一介電層46中形成一溝槽,然後以一(些)導電材料填充溝槽。然後執行一平坦化製程(例如:化學機械平坦化製程)以移除導電材料高於金屬層間介電質層頂部表面的多餘部分,剩下一金屬線在溝槽中。在雙鑲嵌製程中,一溝槽及一通孔開口皆形成在金屬層間介電質層中,其中通孔開口在溝槽下方且連接至溝槽。一(些)導電材料然後被填充至溝槽及通孔開口中以各自形成一金屬線及一通孔。導電材料可包括一擴散阻障層及擴散阻障層上方的一含銅金屬材料。擴散阻障層可包括鈦、氮化鈦、鉭、氮化鉭等。
介電層46可更包括低介電常數介電層上方的鈍化層。舉例來說,在金屬線42及通孔44上方可具有無摻雜矽玻璃(undoped silicate-glass,USG)層、氧化矽層、氮化矽層等。鈍化層比低介電常數介電層密集,且具有將低介電常數介電層從有害化學品及氣體(例如:濕氣)隔離的功能。
根據一些實施例,可具有頂部金屬墊50形成在互連結構40上方,且透過金屬線42及通孔44電性連接至積體電路裝置34。頂部金屬墊50形成在介電層46中。頂部金屬墊50可由銅、鎳、鈦、鈀等、或上述之合金形成或包括上述材料。根據一些實施例,頂部金屬墊50在鈍化層52中。根據一些替代性實施例,可形成一聚合物層(可為聚醯亞胺、聚苯并噁唑(polybenzoxazole,PBO)等),其中頂部金屬墊50在上述聚合物層中。
結合層54沉積在裝置晶圓30的頂部,且因此為裝置晶圓30的頂部表面層。各自的製程繪示如第17圖所示的流程圖200中的製程204。結合層54可由選自用於形成結合層24的相同一組候選材料中的一材料形成。舉例來說,結合層54可選自二氧化矽(SiO
2)、氮化矽、氮氧化矽、碳氮氧化矽、碳化矽、碳氮化矽等、或上述之組合。結合層24與結合層54的材料可彼此相同或彼此不同。根據一些實施例,結合層54具有介於約1000埃至約10000埃之間的厚度。
參照第2圖,裝置晶圓30上下翻轉,且結合至載體晶圓20,其中結合層54結合至結合層24。此結合可透過熔融接合(fusion bonding)執行,舉例來說,形成矽-氧-矽鍵以將載體晶圓20與裝置晶圓30接合。各自的製程繪示如第17圖所示的流程圖200中的製程206。根據一些實施例,裝置晶圓30至載體晶圓20的結合包括在包括氧(O
2)及/或氮(N
2)的處理氣體中預處理結合層24及結合層54、執行預結合製程以將結合層24及結合層54接合在一起、及在預結合製程之後執行退火製程。根據一些實施例,在預結合製程期間,將裝置晶圓30放置接觸載體晶圓20,其中施加一壓力以將裝置晶圓30按壓抵靠載體晶圓20。
在預結合製程之後,執行一退火製程。可形成矽-氧-矽鍵以將結合層24及結合層54接合在一起,使得結合層24及結合層54用高結合強度彼此結合。根據一些實施例,退火製程是在約250℃至約400℃之間的溫度執行。退火期間可在約30分鐘至60分鐘之間的範圍內。根據一些實施例,如第2圖所示,裝置晶圓30在載體晶圓20上方且裝置晶圓30結合至下方的載體晶圓20。根據一些替代性實施例,裝置晶圓30在下方且結合至上方的載體晶圓20,且在結合之後,結合的結構翻轉,而產生的結構如第2圖所示。
參照第3圖,聚合物層58分配至基板22與基板32之間的間隙中,且在互連結構40的側壁上。各自的製程繪示如第17圖所示的流程圖200中的製程208。根據一些實施例,聚合物層58由聚醯亞胺、聚苯并噁唑(PBO)等形成或包括上述材料。聚合物層58是以可流動的形式分配,然後被硬化及固化。進一步地,聚合物層58被分配為一環,完整地環繞基板22與基板32之間的區域。
參照第4圖,從裝置晶圓30背側執行一背側研磨製程,而基板32被薄化。各自的製程繪示如第17圖所示的流程圖200中的製程210。背側研磨製程可透過化學機械平坦化製程或機械拋光製程執行。在背側研磨製程中,聚合物層58具有防止裝置晶圓30從載體晶圓20剝落的功能。此外,研磨製程及後續的清潔製程可能涉及利用水,而聚合物層58可阻擋濕氣從介電層46的側壁貫穿至互連結構40中,且可防止裝置晶圓30中介電層及金屬特徵的劣化。
然後執行一邊緣修整製程以移除聚合物層58及裝置晶圓30的邊緣部分。載體晶圓20的一些邊緣部分亦可被移除。各自的製程繪示如第17圖所示的流程圖200中的製程212。結果的結構如第5圖所示,其中裝置晶圓30的側壁從載體晶圓20的各自邊緣被橫向地凹陷。在第5圖及後續圖式中,顯示裝置晶圓30的一邊緣被修整。實際上,被修整的邊緣為圓形,亦即所有的圓形邊緣可被修整。根據一些實施例,被修整的寬度W1可介於約2毫米至約4毫米的範圍內。進一步地,在修整製程中,基板22的頂部部分可被修整以形成凹部60,延伸至基板22中。凹部60的深度D1可介於約50微米至約200微米的範圍內。凹部60形成一凹部環,環繞基板22的頂部部分。
在後續的製程中,基板32可進一步被薄化。根據一些替代性實施例,省略基板32的進一步薄化。根據一些實施例,基板32在一乾蝕刻製程中被薄化,乾蝕刻製程可為異向性蝕刻製程或同向性蝕刻製程。根據一些替代性實施例,蝕刻可透過乾蝕刻製程以及後續的濕蝕刻製程執行。舉例來說,乾蝕刻製程可利用蝕刻氣體執行,包括氟(F
2)、氯(Cl
2)、氯化氫(HCl)、溴化氫(HBr)、溴(Br
2)、六氟乙烷、四氟化碳、二氧化硫、溴化氫及氯及氧的混合、或溴化氫及氯及氧及二氟甲烷的混合等。若有濕蝕刻製程,可利用氫氧化鉀、四甲基氫氧化銨(tetramethylammonium hydroxide,TMAH)、乙酸、氨水、過氧化氫、異丙醇(Isopropanol,IPA)、氫氟酸及硝酸及水的溶液等。
根據一些替代性實施例,基板32的薄化可透過化學機械平坦化製程或機械研磨製程執行。在貫通孔65(第8圖)以在先前被形成以延伸至基板32中的實施例中,會藉由薄化製程顯露貫通孔65。
第6圖繪示側壁保護層62的形成,側壁保護層62亦為隔離層。各自的製程繪示如第17圖所示的流程圖200中的製程214。側壁保護層62的材料可具有高密度,舉例來說,高於氧化矽的密度,可約略為每立方公分2.65公克。進一步地,側壁保護層62的材料可包括金屬化合物例如:金屬氧化物及/或金屬氮化物,以進一步提升其密度及其阻擋能力。側壁保護層62的密度可高於約每立方公分2.7公克,且可介於每立方公分2.7公克至約每立方公分12.0公克之間的範圍內。舉例來說,氮化矽具有約每立方公分3.17公克的密度,氧化鎢具有約每立方公分7.16公克的密度,且氧化鉿具有約每立方公分9.7公克的密度。稠密的側壁保護層62容許其具有好的防止有害化學品及濕氣貫穿以抵達且劣化裝置晶圓30中低介電常數介電層及金屬特徵的能力。
根據一些實施例,側壁保護層62可由可被表示為M
wO
xN
yC
z的材料形成,其中w、x、y及z的值為相對的原子序,且w、x、y及z的值的總合等於1.0。材料M可選自矽、鋁、鈦、鋯、鉿、鎢等、或上述之組合。w、x、y及z每一者的值可小於約0.9,且可在約0.1至約0.9之間的範圍內。厚度T1亦有關於側壁保護層62的阻擋能力,較稠密的側壁保護層62較薄,而較不稠密的側壁保護層62形成為較厚。根據一些實施例,側壁保護層62的厚度T1介在約3奈米至約1000奈米之間的範圍內。
根據一些實施例,側壁保護層62可由前述的金屬化合物形成,及/或可由氮化矽、氮氧化矽、碳化矽、碳氮化矽、碳氧化矽、氧化鋁、氮化鋁等、上述之化合物、或上述之多層形成或包括上述材料。根據一些實施例,當x、y及z值等於零時,側壁保護層62亦可為矽層或金屬層,金屬選自前述的清單。當為矽層或金屬層時,矽或金屬的原子百分比可大於約百分之90或百分之95。
根據一些實施例,側壁保護層62為單一層,其中整個側壁保護層62由均質的材料形成,此材料可選自上文列出的材料。根據一些替代性實施例,側壁保護層62具有多層結構,包括複數個子層。舉例來說,第6圖繪示一範例雙層側壁保護層62,包括下子層62A及上子層62B。側壁保護層62亦可包括多於兩個子層,例如:三個子層、四個子層或更多。子層的組成彼此不同。當兩個子層被描述為具有不同的組成時,意謂著兩子層的其中一者具有至少一個不在另一子層中的元素,或者兩個子層具有相同元素,但兩子層中元素的百分比彼此不同。
根據一些實施例,下子層62A具有與載體晶圓20及裝置晶圓30良好的接著性,且對載體晶圓20及裝置晶圓30具有比各自的一或多個上子層(例如:上子層62B)更好的接著性。根據一些實施例,下子層62A具有比各自的上層較高的氮原子百分比。因為有較高的氮原子百分比,提升了接著性。舉例來說,下子層62A可表示為Ma
w1O
x1N
y1C
z1,且上子層62B可表示為Mb
w2O
x2N
y2C
z2,其中值y1大於值y2。值x2可大於值x1,使得上層比下層具有更加的阻擋能力,而值x2亦可等於或小於值x1。元件Ma及Mb的每一者可選自矽、鋁、鈦、鋯、鉿、鎢等、或上述之組合。進一步地,元件Ma可相同或不同於元件Mb。
根據一些側壁保護層62具有多層結構的實施例,下子層(例如:下子層62A)及上子層(例如:上子層62B)的每一者或其中一些具有均勻的組成,意謂當沉積時,此些子層中元素的原子百分比為均勻的,且對應前驅物的流率為均勻的。根據一些替代性實施例,當下子層及上子層彼此接觸時,下子層的下方部分可形成為具有均勻的組成,而下子層的上方部分可形成為具有逐漸地改變的組成,逐漸地由下子層的下方部分的組成過渡成上子層的組成。舉例來說,當下子層62A的下方部分由M
wO
x1N
y1C
z形成且上子層由M
wO
x2N
y2C
z2形成時,下子層62A的上方部分可具有逐漸地減少的氮原子百分比及/或逐漸地增加的氧原子百分比。在進行下子層的上方部分的沉積期間,含氮的前驅物的流率逐漸地減少,且用於沉積上子層62B的含氧的前驅物的流率可逐漸地增加,直到某一點,上子層62B開始沉積。
根據一些實施例,側壁保護層62利用保形(conformal)沉積製程例如:化學氣相沉積、原子層沉積等形成。可調整製程條件以更增加所生成的側壁保護層62的密度。舉例來說,可降低側壁保護層62的沉積速率以使側壁保護層62更稠密。這可藉由降低前驅物的流率及/或沉積腔室中的壓力而達成。亦可增加裝置晶圓30及載體晶圓20的溫度以降低沉積速率且增加側壁保護層62的密度。根據一些實施例,沉積溫度介於約25℃至約450℃之間的範圍內,且可介於約350℃至約450℃之間的範圍內。腔室壓力可介於約5毫托(milli-torr)至約50托之間的範圍內。
根據一些實施例,為了達成數個子層之間的差異,可調整製程條件,使得上子層與下子層彼此不同。根據一些實施例,在下子層的沉積中,利用一第一壓力以達成一第一沉積速率。在對應的上子層的沉積中,利用不同於第一壓力的一第二壓力以達成一第二沉積速率,第二沉積速率與第一沉積速率不同。用於沉積下子層的前驅物的流率可與用於沉積上子層的對應前驅物的流率相同。藉此,上子層及下子層可具有相同的組成,同時上子層的密度可不同於(例如:大於或小於)下子層。
第7圖繪示側壁保護層62的水平部分的移除,使得裝置晶圓30的頂部表面顯露。各自的製程繪示如第17圖所示的流程圖200中的製程216。根據一些實施例,執行一化學機械平坦化製程以移除側壁保護層62與裝置晶圓30重疊的第一部分。可執行一蝕刻製程以移除側壁保護層62與載體晶圓20中的基板22重疊且接觸的第二部分。根據一些替代性實施例,側壁保護層62的第二部分未被移除,且留在載體晶圓20上。繪示虛線區域63以顯示側壁保護層62的第二部分可存在或可不存在於此區域中。根據一些替代性實施例,透過一或多個異向性蝕刻製程以執行側壁保護層62水平部分的移除。根據此些實施例,側壁保護層62與裝置晶圓30重疊的水平部分以及側壁保護層62與載體晶圓20重疊的水平部分皆被移除。
剩餘的側壁保護層62形成一完整的環,環繞且接觸裝置晶圓30。側壁保護層62具有防止裝置晶圓30中的層剝落的功能。並且,側壁保護層62防止濕氣及氧從裝置晶圓30的側壁貫穿至裝置晶圓30中。
參照第8圖,形成介電層64,舉例來說,透過保形沉積製程形成,保形沉積製程可為原子層沉積製程、化學氣相沉積製程等。各自的製程繪示如第17圖所示的流程圖200中的製程218。根據一些實施例,介電層64由氧化矽、氮化矽、氮氧化矽等形成或包括上述材料。可形成貫通孔65以貫穿基板32,且貫通孔65電性連接至積體電路裝置34。形成製程可包括蝕刻介電層64及基板32以形成貫通開口。蝕刻可在互連結構40中的金屬墊上停止。然後,形成一隔離層以環繞每一貫通開口。形成製程可包括沉積延伸至貫通開口中的一保形介電層,然後執行一異向性蝕刻製程以再次顯露金屬墊。然後沉積一(些)導電材料以填充貫通開口,然後是一平坦化製程以移除貫通開口外側多餘的導電材料。導電材料的剩餘部分是貫通孔65。各自的製程繪示如第17圖所示的流程圖200中的製程220。
根據一些替代性實施例,貫通孔65已在先前形成(舉例來說,在第1圖所示的製程中)。藉此,在第8圖所示的製程中,可在基板32上執行背側研磨製程及一回蝕刻(etch-back)製程,使得貫通孔65突出高於基板32凹陷的頂部表面。然後沉積介電層64,然後是輕(light)化學機械平坦化製程以再次顯露貫通孔65。
如第8圖所示,介電層64可延伸在側壁保護層62的外側壁上。介電層64可進一步延伸在基板22的頂部表面上且接觸基板22的頂部表面。相反地,當側壁保護層62的此些部分未被移除時,介電層64延伸在虛線區域63(第7圖)中側壁保護層62的水平部分的頂部表面上且接觸此頂部表面。
參照第9圖,形成背側互連結構68,包括一或多個介電層72及一或多層重分布線(redistribution lines,RDLs)70。各自的製程繪示如第17圖所示的流程圖200中的製程222。根據一些實施例,重分布線70透過鑲嵌製程形成,包括沉積對應的介電層72、在介電層72中形成溝槽及通孔開口、及用一(些)金屬材料填充溝槽及通孔開口以形成重分布線70。介電層72可由無機介電材料形成或包括無機介電材料,例如:氧化矽、氮化矽、氮氧化矽等。
根據一些替代性實施例,介電層72可由聚合物形成,聚合物可為光敏性的,且重分布線層的形成製程可包括沉積一金屬種晶層、形成及圖案化金屬種晶層上的電鍍遮罩、執行電鍍製程以形成重分布線、移除電鍍遮罩以顯露金屬種晶層的下方部分、以及蝕刻金屬種晶層的顯露部分。
根據一些實施例,電連接件76形成在裝置晶圓30的背表面上。電連接件76可包括金屬凸塊、金屬墊、焊料區域等。根據一些實施例,電連接件76突出高於介電層72的頂部表面。根據一些替代性實施例,電連接件76的頂部表面與介電層72的表面共平面。
根據一些實施例,移除載體晶圓20。各自的製程繪示如第17圖所示的流程圖200中的製程224。根據一些實施例,第9圖所示的結構的頂側附接至一膠帶,且結構被上下翻轉。然後移除基板22,可透過化學機械平坦化製程、機械研磨製程、蝕刻製程或上述之組合。可移除結合層24,或可留著不移除。當結合層24被移除時,結合層54會被顯露。所生成的結構如第10圖繪示。
第10圖亦顯示,電連接件78形成在裝置晶圓30的前側上。各自的製程繪示如第17圖所示的流程圖200中的製程226。形成製程可包括蝕刻結合層54以形成開口,使得金屬墊50被顯露,且形成延伸至開口中以電性連接金屬墊50的電連接件78。
根據一些實施例,可在一晶粒鋸切製程中被切割以形成離散(discrete)的裝置晶粒30’。側壁保護層62藉由晶粒鋸切製程被移除,且不存在於所生成的裝置晶粒30’中。根據一些替代性實施例,另一裝置晶圓結合至晶圓30以形成一重建晶圓,重建晶圓被切割以將裝置晶粒30’彼此分割,其中每一裝置晶粒30’與其他晶圓中的另一裝置晶粒結合。
第11圖繪示一封裝80,包括與裝置晶粒82結合的裝置晶粒30’。 各自的製程繪示如第17圖所示的流程圖200中的製程228。可分配密封劑84以密封裝置晶粒82。密封劑84可為模製化合物、模製底部填充料等。封裝構件88結合至裝置晶粒30’。封裝構件88可為印刷電路板、封裝基板等。底部填充料86可設置於裝置晶粒30’與封裝構件88之間。
根據一些替代性實施例,裝置晶粒82並非在基板22(第9圖)的移除之後結合至裝置晶粒30’,而是在基板22的移除之前結合至未鋸割的裝置晶圓30中的裝置晶粒30’。藉此,如第11圖所示的裝置晶粒82可結合至第9圖所示的結構,然後透過一密封製程形成一重建晶圓,重建晶圓包括載體晶圓20、裝置晶圓30、裝置晶粒82及密封劑84(第11圖)。然後可執行後續製程以形成第11圖所示的結構。
第12圖至第14圖繪示根據本揭露的一些替代性實施例,封裝形成中的中間階段的剖面圖。此些實施例類似於第1圖至第11圖所示的實施例,除了裝置晶粒並非結合至裝置晶粒30’的前側,而是一封裝構件附接至裝置晶粒30’的背側,且載體晶圓/晶粒的基板22並未完全移除。除非額外指明,此些實施例中的材料及形成製程基本上與相似的構件相同,且用先前在第1圖至第11圖所示的實施例中相似的參考符號標示。因此,關於第12圖至第14圖所示的形成製程及構件材料的細節可見於先前實施例的討論。
此些實施例的初始製程基本上與第1圖至第9圖所示的相同。然後,如第12圖所示,基板22被薄化,舉例來說,透過化學機械平坦化製程或機械研磨製程薄化。
根據一些實施例,裝置晶圓30及基板22可在一晶粒鋸割製程中被切割以形成離散封裝81,每一封裝81包括裝置晶粒30’的其中一者及基板22的一部分。藉由晶粒鋸割製程移除側壁保護層62,側壁保護層62不存在於所生成的封裝81中。第13圖繪示其中一個所生成的封裝81。
第14圖繪示根據一些替代性實施例,封裝80的形成。應理解的是,封裝80的封裝可與第14圖所示不相同。封裝81可透過熱界面材料(Thermal Interface Material,TIM)85或固晶膜(die-attach film)而附接至封裝構件88’。根據一些實施例,裝置晶粒30’透過結合線路87電性連接至封裝構件88。
第15圖繪示一結構,其中形成一晶圓級封裝80’。在晶圓級封裝中,裝置晶圓30未被鋸割,且以晶圓的形狀被使用。裝置晶圓30包括基板32。此實施例可用於一些高性能的應用中,例如:在人工智慧(Artificial Intelligence,AI)的應用。裝置晶圓30結合至晶圓88’’,舉例來說,透過焊料區域78結合。可分配底部填充料86。替代性地,裝置晶圓30可透過晶圓級混成結合而結合至晶圓88’’。如第15圖所示,側壁保護層62可被留在最終結構中。側壁保護層62可形成一完整的環,完整地環繞裝置晶圓30。
根據一些第15圖所示的實施例,移除載體晶圓20的基板22。根據一些替代性實施例,如第16圖所示,基板22被薄化,且封裝構件88’’’附接至下方的基板22,基板22為未鋸割的載體晶圓20的一部分。
本揭露的實施例具有一些有利的特徵。藉由形成稠密的側壁保護層(比氧化矽更稠密),側壁保護層可有效地阻擋氧及濕氣在後續製程中貫穿至裝置晶圓中。藉此,提升側壁保護層的隔離氧及濕氣的能力。
根據本揭露的一些實施例,一種方法包括:結合一第一晶圓至一第二晶圓;在第一晶圓上執行一修整製程,其中第一晶圓的一邊緣部分被移除;沉積一側壁保護層,上述側壁保護層接觸第一晶圓的一側壁,其中沉積側壁保護層包括沉積一高密度材料,與第一晶圓的側壁接觸,且其中側壁保護層具有高於氧化矽的密度的一密度;移除側壁保護層與第一晶圓重疊的一水平部分;以及形成一互連結構在第一晶圓上方,其中互連結構電性連接至第一晶圓中的複數個積體電路裝置。在一實施例中,沉積側壁保護層包括沉積一含金屬的介電層。在一實施例中,含金屬的介電層包括選自鋁、鈦、鋯、鉿、鎢及上述之組合的一金屬。在一實施例中,沉積側壁保護層包括:沉積由一第一材料形成的一第一子層;以及沉積一第二子層在第一子層上,其中第二子層由不同於第一材料的一第二材料形成。在一實施例中,沉積第二子層包括沉積包括一第一金屬的一第一含金屬層。在一實施例中,沉積第一子層包括沉積包括一第二金屬的一第二含金屬層,第二金屬與第一金屬不同。在一實施例中,上述方法更包括:在沉積第一子層與沉積第二子層之間,沉積一第三子層,其中在沉積第三子層的期間,複數個處理氣體逐漸地從用於沉積第一子層的複數個第一前驅物過渡成用於沉積第二子層的複數個第二前驅物。在一實施例中,側壁保護層的整體包括高密度材料。在一實施例中,上述方法更包括:在互連結構形成之後,從第一晶圓移除第二晶圓。在一實施例中,上述方法更包括:在第一晶圓上執行一切割製程,以將第一晶圓分割成複數個裝置晶粒。在一實施例中,複數個裝置晶粒不包含側壁保護層的部分。在一實施例中,上述方法更包括:結合第一晶圓至一晶圓級封裝構件;以及在第一晶圓與晶圓級封裝構件之間設置一底部填充料,其中底部填充料物理性接觸側壁保護層。
根據本揭露的一些實施例,一種方法包括:結合一裝置晶圓至一載體晶圓上方;薄化裝置晶圓的一半導體基板;修整裝置晶圓,其中修整裝置晶圓的一邊緣部分;沉積一側壁保護層在裝置晶圓及載體晶圓上,其中沉積側壁保護層包括沉積一含金屬層;顯露裝置晶圓的一頂部表面;以及形成一互連結構在裝置晶圓上方,其中互連結構電性連接至裝置晶圓中的複數個積體電路裝置。在一實施例中,側壁保護層包括選自鋁、鈦、鋯、鉿、鎢及上述之組合的一金屬。在一實施例中,沉積側壁保護層包括:沉積一第一子層;以及沉積一第二子層在第一子層上,其中第二子層具有比第一子層更高的氮原子百分比。在一實施例中,第二子層具有比第一子層更高的氧原子百分比。在一實施例中,上述方法更包括:在第一子層與第二子層之間沉積一過渡層,其中在沉積過渡層時,複數個製程條件逐漸地由用於形成第一子層的製程條件過渡成用於形成第二子層的製程條件。
根據本揭露的一些實施例,一種方法包括:結合一裝置晶圓至一載體晶圓上方,其中裝置晶圓中的一第一介電層結合至載體晶圓中的一第二介電層;修整裝置晶圓,其中修整裝置晶圓中的一第一基板的一部分,且載體晶圓中的一第二基板的一頂部表面顯露;沉積一側壁保護層在裝置晶圓及載體晶圓上,其中沉積側壁保護層包括沉積選自金屬氧化物、金屬氮化物、金屬碳化物及上述之組合中的一材料;從裝置晶圓及載體晶圓移除側壁保護層的複數個水平部分;移除第二基板的至少一部分;以及附接一封裝構件至裝置晶圓以形成一晶圓級封裝,其中側壁保護層存在於晶圓級封裝中。在一實施例中,沉積側壁保護層包括沉積一含金屬的材料。在一實施例中,沉積側壁保護層包括沉積一金屬化合物,其中金屬化合物包括選自鋁、鈦、鋯、鉿、鎢及上述之組合的一金屬。
前述內文概述了許多實施例的特徵,使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解,且可輕易地以本揭露為基礎來設計或修飾其他製程及結構,並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下,可對本揭露進行各種改變、置換或修改。
20:載體晶圓(晶圓)
22:基板
24:結合層
30:裝置晶圓
30’:裝置晶粒
32:基板(半導體基板)
34:積體電路裝置
36:層間介電質
38:接觸塞
40:互連結構
42:金屬線
44:通孔
46:介電層
50:頂部金屬墊
52:鈍化層
54:結合層
58:聚合物層
60:凹部
62:側壁保護層
62A:下子層
62B:上子層
63:虛線區域
64:介電層
65:貫通孔
68:背側互連結構
70:重分布線
72:介電層
76:電連接件
78:電連接件(焊料區域)
80:封裝
80’:晶圓級封裝
81:封裝
82:裝置晶粒
84:密封劑
85:熱界面材料
86:底部填充料
87:結合線路
88:封裝構件
88’:封裝構件
88’’:晶圓
88’’’:封裝構件
200:流程圖
202,204,206,208,210,212,214,216,218,220,222,224,226,228:製程
D1:深度
T1:厚度
W1:寬度
根據以下的詳細說明並配合所附圖式做完整揭露。應被強調的是,根據本產業的一般作業,圖示並未必按照比例繪製。事實上,可能任意的放大或縮小元件的尺寸,以做清楚的說明。
第1圖至第11圖繪示根據一些實施例,晶圓結合製程及封裝形成中的中間階段。
第12圖至第14圖繪示根據一些實施例,晶圓結合製程及封裝形成中的中間階段。
第15圖及第16圖繪示根據一些實施例,晶圓級封裝的剖面圖。
第17圖繪示根據一些實施例,晶圓結合製程及封裝形成的流程圖。
200:流程圖
202,204,206,208,210,212,214,216,218,220,222,224,226,228:製程
Claims (20)
- 一種形成半導體結構的方法,包括: 結合一第一晶圓至一第二晶圓; 在該第一晶圓上執行一修整製程,其中該第一晶圓的一邊緣部分被移除; 沉積一側壁保護層,該側壁保護層接觸該第一晶圓的一側壁,其中沉積該側壁保護層包括沉積一高密度材料,與該第一晶圓的該側壁接觸,且其中該側壁保護層具有高於氧化矽的密度的一密度; 移除該側壁保護層與該第一晶圓重疊的一水平部分;以及 形成一互連結構在該第一晶圓上方,其中該互連結構電性連接至該第一晶圓中的複數個積體電路裝置。
- 如請求項1之方法,其中沉積該側壁保護層包括沉積一含金屬的介電層。
- 如請求項2之方法,其中該含金屬的介電層包括選自鋁、鈦、鋯、鉿、鎢及上述之組合的一金屬。
- 如請求項1之方法,其中沉積該側壁保護層包括: 沉積由一第一材料形成的一第一子層;以及 沉積一第二子層在該第一子層上,其中該第二子層由不同於該第一材料的一第二材料形成。
- 如請求項4之方法,其中沉積該第二子層包括沉積包括一第一金屬的一第一含金屬層。
- 如請求項5之方法,其中沉積該第一子層包括沉積包括一第二金屬的一第二含金屬層,該第二金屬與該第一金屬不同。
- 如請求項4之方法,更包括:在沉積該第一子層與沉積該第二子層之間,沉積一第三子層,其中在沉積該第三子層的期間,複數個處理氣體逐漸地從用於沉積該第一子層的複數個第一前驅物過渡成用於沉積該第二子層的複數個第二前驅物。
- 如請求項1之方法,其中該側壁保護層的整體包括該高密度材料。
- 如請求項1之方法,更包括:在該互連結構形成之後,從該第一晶圓移除該第二晶圓。
- 如請求項1之方法,更包括:在該第一晶圓上執行一切割製程,以將該第一晶圓分割成複數個裝置晶粒,其中該些裝置晶粒不包含該側壁保護層的部分。
- 如請求項10之方法,其中該些裝置晶粒不包含該側壁保護層的部分。
- 如請求項1之方法,更包括: 結合該第一晶圓至一晶圓級封裝構件;以及 在該第一晶圓與該晶圓級封裝構件之間設置一底部填充料,其中該底部填充料物理性接觸該側壁保護層。
- 一種形成半導體結構的方法,包括: 結合一裝置晶圓至一載體晶圓上方; 薄化該裝置晶圓的一半導體基板; 修整該裝置晶圓,其中修整該裝置晶圓的一邊緣部分; 沉積一側壁保護層在該裝置晶圓及該載體晶圓上,其中沉積該側壁保護層包括沉積一含金屬層; 顯露該裝置晶圓的一頂部表面;以及 形成一互連結構在該裝置晶圓上方,其中該互連結構電性連接至該裝置晶圓中的複數個積體電路裝置。
- 如請求項13之方法,其中該側壁保護層包括選自鋁、鈦、鋯、鉿、鎢及上述之組合的一金屬。
- 如請求項13之方法,其中沉積該側壁保護層包括: 沉積一第一子層;以及 沉積一第二子層在該第一子層上,其中該第二子層具有比該第一子層更高的氮原子百分比。
- 如請求項15之方法,其中該第二子層具有比該第一子層更高的氧原子百分比。
- 如請求項15之方法,更包括:在該第一子層與該第二子層之間沉積一過渡層,其中在沉積該過渡層時,複數個製程條件逐漸地由用於形成該第一子層的製程條件過渡成用於形成該第二子層的製程條件。
- 一種形成半導體結構的方法,包括: 結合一裝置晶圓至一載體晶圓上方,其中該裝置晶圓中的一第一介電層結合至該載體晶圓中的一第二介電層; 修整該裝置晶圓,其中修整該裝置晶圓中的一第一基板的一部分,且該載體晶圓中的一第二基板的一頂部表面顯露; 沉積一側壁保護層在該裝置晶圓及該載體晶圓上,其中沉積該側壁保護層包括沉積選自金屬氧化物、金屬氮化物、金屬碳化物及上述之組合中的一材料; 從該裝置晶圓及該載體晶圓移除該側壁保護層的複數個水平部分; 移除該第二基板的至少一部分;以及 附接一封裝構件至該裝置晶圓以形成一晶圓級封裝,其中該側壁保護層存在於該晶圓級封裝中。
- 如請求項18之方法,其中沉積該側壁保護層包括沉積一含金屬的材料。
- 如請求項18之方法,其中沉積該側壁保護層包括沉積一金屬化合物,其中該金屬化合物包括選自鋁、鈦、鋯、鉿、鎢及上述之組合的一金屬。
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