TW202322330A - 採用耦合到晶粒側嵌入式跡線基板（ｅｔｓ）層中的嵌入式金屬跡線的補充金屬層的積體電路（ｉｃ）封裝以及相關的製造方法 - Google Patents

採用耦合到晶粒側嵌入式跡線基板（ｅｔｓ）層中的嵌入式金屬跡線的補充金屬層的積體電路（ｉｃ）封裝以及相關的製造方法 Download PDF

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Publication number
TW202322330A
TW202322330A TW111135447A TW111135447A TW202322330A TW 202322330 A TW202322330 A TW 202322330A TW 111135447 A TW111135447 A TW 111135447A TW 111135447 A TW111135447 A TW 111135447A TW 202322330 A TW202322330 A TW 202322330A
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Taiwan
Prior art keywords
metal
layer
die
interconnects
package
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TW111135447A
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English (en)
Chinese (zh)
Inventor
米雪兒藝珍 金
姜歸源
瓊雷伊維拉爾巴 比奧
黃清流
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美商高通公司
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Application filed by 美商高通公司 filed Critical 美商高通公司
Publication of TW202322330A publication Critical patent/TW202322330A/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
TW111135447A 2021-10-18 2022-09-20 採用耦合到晶粒側嵌入式跡線基板（ｅｔｓ）層中的嵌入式金屬跡線的補充金屬層的積體電路（ｉｃ）封裝以及相關的製造方法 TW202322330A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/451,302 US12362269B2 (en) 2021-10-18 2021-10-18 Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods
US17/451,302 2021-10-18

Publications (1)

Publication Number Publication Date
TW202322330A true TW202322330A (zh) 2023-06-01

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Family Applications (1)

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TW111135447A TW202322330A (zh) 2021-10-18 2022-09-20 採用耦合到晶粒側嵌入式跡線基板（ｅｔｓ）層中的嵌入式金屬跡線的補充金屬層的積體電路（ｉｃ）封裝以及相關的製造方法

Country Status (7)

Country Link
US (1) US12362269B2 (enExample)
EP (1) EP4420164A1 (enExample)
JP (1) JP2024537996A (enExample)
KR (1) KR20240074788A (enExample)
CN (1) CN118056277A (enExample)
TW (1) TW202322330A (enExample)
WO (1) WO2023069820A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12100645B2 (en) 2021-09-23 2024-09-24 Qualcomm Incorporated Integrated circuit (IC) package employing added metal for embedded metal traces in ETS-based substrate for reduced signal path impedance, and related fabrication methods

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101514539B1 (ko) 2013-08-29 2015-04-22 삼성전기주식회사 전자부품 내장기판
US8772951B1 (en) 2013-08-29 2014-07-08 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
US10748843B2 (en) 2016-11-18 2020-08-18 Advanced Semiconductor Engineering, Inc. Semiconductor substrate including embedded component and method of manufacturing the same
US10096542B2 (en) 2017-02-22 2018-10-09 Advanced Semiconductor Engineering, Inc. Substrate, semiconductor package structure and manufacturing process
US20180350630A1 (en) 2017-06-01 2018-12-06 Qualcomm Incorporated Symmetric embedded trace substrate
US10354969B2 (en) * 2017-07-31 2019-07-16 Advanced Semiconductor Engineering, Inc. Substrate structure, semiconductor package including the same, and method for manufacturing the same
US11004779B2 (en) * 2018-02-09 2021-05-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10418316B1 (en) * 2018-04-04 2019-09-17 Advanced Semiconductor Engineering, Inc. Semiconductor substrate, semiconductor package structure and method of manufacturing a semiconductor device
US10622292B2 (en) 2018-07-06 2020-04-14 Qualcomm Incorporated High density interconnects in an embedded trace substrate (ETS) comprising a core layer
US10804195B2 (en) * 2018-08-08 2020-10-13 Qualcomm Incorporated High density embedded interconnects in substrate
US12142567B2 (en) * 2019-04-17 2024-11-12 Intel Corporation Coreless architecture and processing strategy for EMIB-based substrates with high accuracy and high density
JP7430990B2 (ja) 2019-06-26 2024-02-14 新光電気工業株式会社 配線基板の製造方法
US11742301B2 (en) 2019-08-19 2023-08-29 Advanced Micro Devices, Inc. Fan-out package with reinforcing rivets
MY208458A (en) * 2019-09-26 2025-05-09 Intel Corp Organic mold interconnects in shielded interconnects frames for integrated-circuit packages
EP4161222A4 (en) * 2020-05-26 2024-07-10 LG Innotek Co., Ltd. PACKAGING SUBSTRATE
US12354935B2 (en) 2020-08-25 2025-07-08 Qualcomm Incorporated Integrated circuit (IC) package substrate with embedded trace substrate (ETS) layer on a substrate, and related fabrication methods
US12100645B2 (en) 2021-09-23 2024-09-24 Qualcomm Incorporated Integrated circuit (IC) package employing added metal for embedded metal traces in ETS-based substrate for reduced signal path impedance, and related fabrication methods
US11791320B2 (en) 2021-11-22 2023-10-17 Qualcomm Incorporated Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods
US20230215849A1 (en) 2022-01-05 2023-07-06 Qualcomm Incorporated PACKAGE SUBSTRATES WITH EMBEDDED DIE-SIDE, FACE-UP DEEP TRENCH CAPACITOR(S) (DTC(s)), AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS
US20250062235A1 (en) 2023-08-16 2025-02-20 Qualcomm Incorporated Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (ic) packages and fabrication methods

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Publication number Publication date
WO2023069820A1 (en) 2023-04-27
CN118056277A (zh) 2024-05-17
JP2024537996A (ja) 2024-10-18
EP4420164A1 (en) 2024-08-28
US12362269B2 (en) 2025-07-15
KR20240074788A (ko) 2024-05-28
US20230118028A1 (en) 2023-04-20

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