TW202240874A - 垂直通道矽場效應電晶體的製造製程 - Google Patents

垂直通道矽場效應電晶體的製造製程 Download PDF

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TW202240874A
TW202240874A TW110145717A TW110145717A TW202240874A TW 202240874 A TW202240874 A TW 202240874A TW 110145717 A TW110145717 A TW 110145717A TW 110145717 A TW110145717 A TW 110145717A TW 202240874 A TW202240874 A TW 202240874A
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劉遠良
輝 臧
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美商豪威科技股份有限公司
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Abstract

一種製造在溝槽中具有垂直閘的電晶體的方法，包括微影蝕刻以形成寬溝槽；在溝槽中形成介電質並用可流動的材料填充溝槽；以及微影蝕刻以在寬溝槽內形成窄溝槽從而在由窄溝槽暴露的基板頂部磊晶生長半導體條之前暴露阱或基板；移除可流動的材料；在半導體條上生長閘極氧化物；在閘極氧化物上方以及在磊晶生長的半導體條與介電質之間的間隙中形成閘極導體；遮罩和蝕刻閘極導體；以及佈植源極和汲極區域。所形成的電晶體具有從源極區域延伸至汲極區域的半導體條、在半導體條的兩個垂直壁上形成的閘極氧化物；以及在介電質和閘極氧化物之間的閘極材料，半導體條在溝槽內，溝槽壁用介電質絕緣。

Description

垂直通道矽場效應電晶體的製造製程
本發明提出了一種用於小型垂直通道絕緣閘場效應電晶體的新製造製程。在一個實施例中，這些電晶體被用作埋入型光電二極體影像感測器電路中的源極隨耦器(source follower)和重置電晶體(reset transistors)，以實現小單元尺寸和最小化像素面積。
具有非共面(non-coplanar)源極/汲極擴散的矽場效應電晶體(Silicon field-effect transistors)(典型地其中源極和汲極區域中的一個在另一個之上)通常用於大功率開關元件中，並且還被用作選擇電晶體以將埋入型光電二極體耦接到上覆電路。然而，這些元件不使用垂直通道在共面但水平分離的源極/汲極擴散之間進行耦接。
在一個實施例中，一種製造在寬溝槽中具有垂直閘的電晶體的方法，包括遮罩和蝕刻寬溝槽；在寬溝槽內和周圍形成介電質；將可流動的材料沉積到寬溝槽中；遮罩和蝕刻以在寬溝槽內形成內部窄溝槽並從而暴露阱或基板。該方法繼續在內部窄溝槽內磊晶生長由阱或基板種晶(seeded)的半導體條；從寬溝槽中移除可流動的材料；在半導體條上生長閘氧化物；在閘氧化物上方以及在磊晶生長的半導體條和介電質之間的間隙中形成閘極導體；遮罩和蝕刻閘極導體；以及佈植源極和汲極區域。
在另一個實施例中，一種垂直閘電晶體包括從第二導電類型的源極區域延伸到第二導電類型的汲極區域的第一導電類型的半導體條，半導體條 形成在溝槽內，溝槽壁用介電質絕緣；在半導體條的兩個垂直壁上形成的閘極氧化物；以及在介電質和閘極氧化物之間的閘極材料。
120:電晶體
122:源極
126:汲極
127:阱或基板
130:第一和第二側
124:半導體條或填充物
128:重疊區域
129:延伸
100:電晶體
104、127:阱或基板
102:溝槽
106:半導體條
108:薄閘極絕緣體
110:閘極導體
112:垂直閘極部分
114:厚介電質
116:重疊部分
118:互連部分
130、110:閘極導體材料
200:光電二極體像素單元
202:源極隨耦器電晶體
204:單元選擇電晶體
206:重置電晶體
208、210、212、214:光電二極體傳輸閘電晶體
216、218、220、222:埋入型光電二極體
250:方法
252、254、255、256、258、259、260、262、264、266、268:步驟
402:溝槽
404:阱或基板
406:介電質
407:可流動的CVD材料
402A:空間
408:內部窄溝槽
406A:介電質的形狀
407A:可流動CVD材料的形狀
404:基板或阱
410:半導體條
412:閘極氧化物
414:閘極導體
406A:介電質
圖1是被配置用於共面源極/汲極區域之間的垂直通道的電晶體的俯視平面圖。
圖2是沿著圖1的線A-A截取的被配置用於垂直通道的電晶體的橫截面圖，垂直通道沿著溝槽中的磊晶半導體條的側壁。
圖3是在影像感測器積體電路中有用的四個埋入型光電二極體、七個電晶體像素單元的示意圖。
圖4是製造圖1和圖2的電晶體的方法的流程圖。
圖5、6、7、8、9、10、11、12和13是圖示圖1和2的部分製造的電晶體的橫截面圖，每一個都可能出現在圖4的方法的特定步驟中。
在圖1的俯視平面圖中圖示了在溝槽中具有磊晶半導體條的新電晶體120。電晶體具有第一擴散類型(諸如N型)的源極122和汲極126擴散區域，其在第二擴散類型(諸如P型)半導體(諸如矽)的阱或基板127中。在替代的實施例中，半導體是另一種IV族材料(諸如鍺)、化合物半導體(諸如矽與碳或鍺的合金)、或者III-V族半導體(諸如砷化鎵，砷化鎵銦)。電晶體120具有由導體(諸如多晶矽)直接在第二擴散類型的半導體條或填充物124上方形成的閘極，延伸至包括半導體條或填充物124的第一和第二側130的閘極，並且閘極導體可以在重疊區域128中重疊電晶體。閘極導體材料可以在元件的其他部分上延伸129以用作互連。
在橫截面中，新電晶體100是在第二導體類型的阱或基板104、 127中切割的溝槽102內和頂部製造的。磊晶生長的半導體條106大致位於溝槽102的中心，沿其側面有薄閘極絕緣體108。閘極導體110在半導體條106上形成，並在半導體條106的兩側面填充溝槽102的垂直閘極部分112。溝槽102的剩餘部分填充有厚介電質114，該厚介電質114還在閘極導體110的重疊部分116和互連部分118下方延伸跨過阱或基板表面。
在特定的實施例中，阱或基板104、127是P型矽，半導體填充物124是磊晶生長的P型矽，閘極絕緣體108是熱生長的氧化矽，閘極導體材料130、110是多晶矽，並且當閘極導體材料130、110被適當加偏壓時形成的反轉區域是N型的，並且具有磊晶帶124、106的電晶體作為N通道金屬氧化物半導體(MOS)電晶體操作。在該實施例中，厚介電質114是氧化矽(silicon oxide)，諸如熱生長氧化物或化學氣象沉積(CVD)氧化物膜，但也可以使用其他介電質。
當閘極導體110被適當加偏壓時，沿著磊晶生長的半導體條(epitaxially-grown semiconductor strip)106、124的頂部和側壁形成反轉區域(inversion regions)，從而在有效閘極寬度為兩倍於溝槽102的深度加上半導體條106、124的寬度的總和的情況下操作。
與現有MOS電晶體相比，在溝槽中具有磊晶半導體條的電晶體120具有優勢，因為電晶體的有效閘極寬度可以大於使用相同表面積的半導體晶片製造的傳統製造的平面電晶體的有效閘極寬度。
在一個實施例中，具有磊晶條106的電晶體100在影像感測器積體電路中用作影像感測器的四個-埋入型光電二極體像素單元(4-burried-photodiode pixel cell)200中的減小物理寬度的源極隨耦器電晶體202(圖3)、單元選擇電晶體(cell-selection transistor)204和重置電晶體(reset transistor)206。在該影像感測器像素單元中，光電二極體傳輸閘電晶體208、210、212、214可以是用於選擇埋入型光電二極體(buried photodiodes)216、218、220、222的垂直電晶體(vertical transistors)。
在一個實施例中，圖1和圖2的具有磊晶條的電晶體100是根據圖4的方法250製造的；注意，在方法250的步驟之前，需要在加工中的早期步驟來製備晶片，除了在此描述的步驟之外，還可以執行諸如清潔和光阻膠剝離(photoresist stripping)之類的中間步驟，並且需要以下步驟來完成積體電路(integrated circuit)。
執行遮罩和蝕刻操作(步驟)252以將深度為50至400奈米的溝槽402(圖5)蝕刻到阱或基板404中。除了光遮罩材料的沉積、光遮罩材料的曝光、光阻膠材料的顯影、蝕刻和光阻膠的移除之外，本文所描述的遮罩和蝕刻操作還可以包括沉積和移除硬遮罩材料(諸如氮化矽SiN)。再平坦化操作，諸如化學機械拋光(chemical-mechanical polishing)，還可以穿插在圖4中記錄的步驟之間。
在蝕刻溝槽402、102之後，然後在溝槽402中和周圍將所形成的介電質406襯於溝槽402、102中(圖6)。在實施例中，該介電質是生長在圍繞溝槽的半導體阱或基板上的熱氧化物(thermal oxide)。
在形成介電質(步驟)254之後，沉積並流動(步驟)255可流動的CVD材料407(圖7)。在流動該氧化物之後，可流動的CVD材料可以被平坦化(圖8)以使晶片表面平整，在未被介電質406佔據的每個溝槽內的空間402A留下可流動的CVD材料407。在一個實施例中，可流動的CVD材料407是氮化矽或含有矽、氮和氫的膜。
一旦形成介電質406和可流動的CVD材料407，就執行遮罩和蝕刻操作(步驟)256以在介電質406和可流動的CVD材料407中形成內部窄溝槽408(圖9)，形成剩餘的介電質的形狀406A(圖9)和剩餘的可流動CVD材料的形狀407A以及在窄溝槽408的底部暴露基板或阱404。在內部溝槽408形成之後，在內部溝槽408的底部並在溝槽402內居中對準的半導體條410(圖10)通過由阱或基板404種晶的磊晶生長(步驟)258形成。在生長半導體條 410之後，在移除(步驟)259剩餘的可流動材料407(圖11)並在半導體條410上生長(步驟)260閘極氧化物412(圖12)之前，可以任選地再平坦化正在形成的元件。
在閘極氧化物412生長(步驟)260之後，閘極導體414(圖13)沉積(步驟)262在閘極氧化物412上並進入磊晶生長的半導體條410和介電質406A之間的間隙，在一個實施例中，閘極導體414是用鉬矽化的多晶矽。
在沉積(步驟)262閘極導體414之後，閘極導體被遮罩和蝕刻(步驟)264，以根據特定積體電路設計的需要用閘極區域130、124(圖1)、重疊區域(如果有的話)128和延伸的互連區域129對該導體圖案化。
在閘極導體414被遮罩和蝕刻(步驟)264之後，源極和汲極區域122、126被佈植(步驟)266，之後用傳統的金屬、通孔和接觸沉積、遮罩和蝕刻步驟完成(步驟)268積體電路。
在實施例中，在每個晶片上形成數十萬或數百萬個本文描述的橫向垂直閘電晶體，每個數百萬像素影像感測器的像素單元有一個或多個。
組合
一種指定為A的製造在寬溝槽中具有垂直閘的電晶體的方法，包括遮罩和蝕刻寬溝槽；在寬溝槽中和周圍形成介電質；用可流動的材料填充寬溝槽；遮罩和蝕刻以在寬溝槽中形成內部窄溝槽，從而暴露阱或基板。該方法繼續在由內部窄溝槽暴露的阱或基板頂部磊晶生長由阱或基板種晶的半導體條；從寬溝槽中移除可流動的材料；在半導體條上生長閘氧化物；在閘氧化物上方以及在磊晶生長的半導體條和介電質之間的間隙中形成閘極導體；遮罩和蝕刻閘極導體；以及佈植源極和汲極區域。
指定為AA的方法，包括指定為A的方法，其中寬溝槽的深度為50至400奈米。
指定為AB的方法，包括指定為A或AA的方法，其中半導體條主要包括矽。
指定為AC的方法，包括指定為A、AA或AB的方法，其中阱或基板主要包括矽。
指定為AD的方法，包括指定為A、AA、AB或AC的方法，其中閘極導體主要包括多晶矽。
指定為AE的方法，包括指定為A、AA、AB、AC或AD的方法，其中介電質包括二氧化矽。
指定為AF的方法，包括指定為A、AA、AB、AC、AD或AE的方法，其中半導體條具有P型矽並且源極和汲極具有N型矽。
指定為AG的方法，包括指定為A、AA、AB、AC、AD、AE或AF的方法，其中可流動材料包括矽、氮和氫。
指定為B的垂直閘電晶體，包括從第二導電類型的源極區域延伸到第二導電類型的汲極區域的第一導電類型的半導體條，半導體條形成在溝槽內，溝槽壁用介電質絕緣；在半導體條的兩個垂直壁上形成的閘氧化物；以及在介電質與閘氧化物之間的閘極材料。
指定為BA的垂直閘電晶體，包括指定為B的垂直閘電晶體，其中半導體條主要包括矽。
指定為BB的垂直閘電晶體，包括指定為B或BA的垂直閘電晶體，其中閘極材料主要包括多晶矽。
指定為BC的垂直閘電晶體，包括指定為B、BA或BC的垂直閘極電晶體，其中溝槽具有在50與400奈米之間的深度。
雖然已經參照本發明的優選實施例具體地示出和描述了本發明，但是本領域技術人員將理解，在不脫離本發明的精神和範圍的情況下，可以對形式和細節進行各種其他改變。應當理解，在使本發明適應於不同實施例的過程中，可以在不脫離本文公開並由所附權利要求所理解的更廣泛的發明概念下進行各種改變。
250:方法
252、254、255、256、258、259、260、262、264、266、268:步驟

Claims (12)

  1. 一種製造在寬溝槽中具有垂直閘的電晶體的方法，包括：
    遮罩和蝕刻該寬溝槽；
    在該寬溝槽中和其周圍形成介電質；
    利用可流動的材料填充該寬溝槽；
    遮罩和蝕刻以在該寬溝槽中形成內部窄溝槽，從而暴露阱或基板；
    在由該內部窄溝槽暴露的該阱或基板頂部磊晶生長由該阱或基板種晶的半導體條；
    從該寬溝槽中移除該可流動的材料；
    在該半導體條上生長閘極氧化物；
    在該閘極氧化物上方以及在磊晶生長的該半導體條和該介電質之間的間隙中形成閘極導體；
    遮罩和蝕刻該閘極導體；以及
    佈植源極和汲極區域。
  2. 如請求項1所述的方法，其中該寬溝槽的深度為50至400奈米。
  3. 如請求項2所述的方法，其中該半導體條主要包括矽。
  4. 如請求項2所述的方法，其中該阱或基板主要包括矽。
  5. 如請求項3所述的方法，其中所述閘極導體主要包括多晶矽。
  6. 如請求項5所述的方法，其中該介電質包括可流動的化學氣相沉積(CVD) 氧化物。
  7. 如請求項6所述的方法，其中該半導體條具有P型矽並且該源極和汲極具有N型矽。
  8. 如請求項6所述的方法，其中該可流動的材料包括矽、氮和氫。
  9. 一種垂直閘電晶體，包括：
    從第二導電類型的源極區域延伸到該第二導電類型的汲極區域的第一導電類型的半導體條，該半導體條形成在溝槽內，該溝槽的壁用介電質絕緣；
    在該半導體條的兩個垂直壁上形成的閘極氧化物；以及
    在該介電質和該閘極氧化物之間的閘極材料。
  10. 如請求項9所述的垂直閘電晶體，其中該半導體條主要包括矽。
  11. 如請求項9所述的垂直閘電晶體，其中該閘極材料主要包括多晶矽。
  12. 如請求項9-11中任何一項中所述的垂直閘電晶體，其中所述溝槽的深度在50與400奈米之間。
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