CN114649210A - 竖直沟道硅场效应晶体管的制造工艺 - Google Patents

竖直沟道硅场效应晶体管的制造工艺 Download PDF

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CN114649210A
CN114649210A CN202111443837.XA CN202111443837A CN114649210A CN 114649210 A CN114649210 A CN 114649210A CN 202111443837 A CN202111443837 A CN 202111443837A CN 114649210 A CN114649210 A CN 114649210A
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semiconductor strip
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刘远良
臧辉
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Omnivision Technologies Inc
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Abstract

提供了一种制造在宽沟槽中具有竖直栅的晶体管的方法和一种竖直栅晶体管。制造在沟槽中具有竖直栅的晶体管的方法包括光刻以形成宽沟槽；在沟槽中形成介质并用可流动的材料填充沟槽；以及光刻以在宽沟槽内形成窄沟槽从而在由窄沟槽暴露的基板顶部外延生长半导体条之前暴露阱或基板；移除可流动的材料；在半导体条上生长栅氧化物；在栅氧化物上方以及在外延生长的半导体条与介质之间的间隙中形成栅极导体；掩模和刻蚀栅极导体；以及注入源极和漏极区域。所形成的晶体管具有从源极区域延伸至漏极区域的半导体条、在半导体条的两个竖直壁上形成的栅氧化物；以及在介质和栅氧化物之间的栅极材料，半导体条在沟槽内，沟槽壁用介质绝缘。

Description

竖直沟道硅场效应晶体管的制造工艺
技术领域
本发明涉及一种制造在宽沟槽中具有竖直栅的晶体管的方法和一种竖直栅晶体管。
背景技术
具有非共面源极/漏极扩散的硅场效应晶体管(典型地其中源极和漏极区域中的一个在另一个之上)通常用于大功率开关器件中，并且还被用作选择晶体管以将埋入型光电二极管耦接到上覆电路。然而，这些器件不使用竖直通道在共面但水平分离的源极/漏极扩散之间进行耦接。
发明内容
提出了一种用于小型竖直沟道绝缘栅场效应晶体管的新制造工艺。在一个实施方案中，这些晶体管被用作埋入型光电二极管图像传感器电路中的源极跟随器和复位晶体管，以实现小单元尺寸和最小化像素面积。
本发明提供了一种制造在宽沟槽中具有竖直栅的晶体管的方法和一种竖直栅晶体管。
在一方面，一种制造在宽沟槽中具有竖直栅的晶体管的方法，包括掩模和刻蚀宽沟槽；在宽沟槽内和周围形成介质；将可流动的材料沉积到宽沟槽中；掩模和刻蚀以在宽沟槽内形成内部窄沟槽并从而暴露阱或基板。该方法继续在内部窄沟槽内外延生长由阱或基板引晶(seed)的半导体条；从宽沟槽中移除可流动的材料；在半导体条上生长栅氧化物；在栅氧化物上方以及在外延生长的半导体条和介质之间的间隙中形成栅极导体；掩模和刻蚀栅极导体；以及注入源极和漏极区域。
在一些实施方案中，所述宽沟槽的深度为50至400纳米。
在一些实施方案中，所述半导体条主要包括硅。
在一些实施方案中，所述阱或基板主要包括硅。
在一些实施方案中，所述栅极导体主要包括多晶硅。
在一些实施方案中，所述介质包括可流动的化学气相沉积(CVD)氧化物。
在一些实施方案中，所述半导体条具有P型硅并且所述源极和漏极具有N型硅。
在一些实施方案中，所述可流动的材料包括硅、氮和氢。
在另一方面，一种竖直栅晶体管包括从第二导电类型的源极区域延伸到第二导电类型的漏极区域的第一导电类型的半导体条，半导体条形成在沟槽内，沟槽壁用介质绝缘；在半导体条的两个竖直壁上形成的栅氧化物；以及在介质和栅氧化物之间的栅极材料。
在一些实施方案中，所述半导体条主要包括硅。
在一些实施方案中，所述栅极材料主要包括多晶硅。
在一些实施方案中，所述沟槽的深度在50与400纳米之间。
附图说明
图1是被配置用于共面源极/漏极区域之间的竖直沟道的晶体管的俯视平面图。
图2是沿着图1的线A-A截取的被配置用于竖直沟道的晶体管的横截面图，竖直沟道沿着沟槽中的外延半导体条的侧壁。
图3是在图像传感器集成电路中有用的四埋入型光电二极管、七晶体管像素单元的示意图。
图4是制造图1和图2的晶体管的方法的流程图。
图5、6、7、8、9、10、11、12和13是图示图1和2的部分制造的晶体管的横截面图，每一个都可能出现在图4的方法的特定步骤中。
具体实施方式
在图1的俯视平面图中图示了在沟槽中具有外延半导体条的新晶体管120。晶体管具有第一扩散类型(诸如N型)的源极122和漏极126扩散区域，其在第二扩散类型(诸如P型)半导体(诸如硅)的阱或基板127中。在替代的实施方案中，半导体是另一种IV族材料(诸如锗)、化合物半导体(诸如硅与碳或锗的合金)、或者III-V族半导体(诸如砷化镓，砷化镓铟)。晶体管120具有由导体(诸如多晶硅)直接在第二扩散类型的半导体条或填充物124上方形成的栅极，延伸至包括半导体条或填充物124的第一和第二侧130的栅极，并且栅极导体可以在重叠区域128中重叠晶体管。栅极导体材料可以在器件的其他部分上延伸129以用作互连。
在横截面中，新晶体管100是在第二导体类型的阱或基板104、127中切割的沟槽102内和顶部制造的。外延生长的半导体条106大致位于沟槽102的中心，沿其侧面有薄栅极绝缘体108。栅极导体110在半导体条106上形成，并在半导体条106的两侧面填充沟槽102的竖直栅极部分112。沟槽102的剩余部分填充有厚介质114，该厚介质114还在栅极导体110的重叠部分116和互连部分118下方延伸跨过阱或基板表面。
在特定的实施方案中，阱或基板104、127是P型硅，半导体填充物124是外延生长的P型硅，栅极绝缘体108是热生长的氧化硅，栅极导体材料130、110是多晶硅，并且当栅极导体材料130、110被适当加偏压时形成的反转区域是N型的，并且具有外延带124、106的晶体管作为N沟道金属氧化物半导体(MOS)晶体管操作。在该实施方案中，厚介质114是氧化硅，诸如热生长氧化物或CVD氧化物膜，但也可以使用其他介质。
当栅极导体110被适当加偏压时，沿着外延生长的半导体条106、124的顶部和侧壁形成反转区域，从而在有效栅极宽度为两倍于沟槽102的深度加上半导体条106、124的宽度的总和的情况下操作。
与现有MOS晶体管相比，在沟槽中具有外延半导体条的晶体管120具有优势，因为晶体管的有效栅极宽度可以大于使用相同表面积的半导体晶片制造的传统制造的平面晶体管的有效栅极宽度。
在一个实施方案中，具有外延条106的晶体管100在图像传感器集成电路中用作图像传感器的4-埋入型光电二极管像素单元200中的减小物理宽度的源极跟随器晶体管202(图3)、单元选择晶体管204和复位晶体管206。在该图像传感器像素单元中，光电二极管传输栅晶体管208、210、212、214可以是用于选择埋入型光电二极管216、218、220、222的竖直晶体管。
在一个实施方案中，图1和图2的具有外延条的晶体管100是根据图4的方法250制造的；注意，在方法250的步骤之前，需要在加工中的早期步骤来制备晶片，除了在此描述的步骤之外，还可以执行诸如清洁和光刻胶剥离之类的中间步骤，并且需要以下步骤来完成集成电路。
执行掩模和刻蚀操作252以将深度为50至400纳米的沟槽402(图5)刻蚀到阱或基板404中。除了光掩模材料的沉积、光掩模材料的曝光、光刻胶材料的显影、刻蚀和光刻胶的移除之外，本文所描述的掩模和刻蚀操作还可以包括沉积和移除硬掩模材料(诸如氮化硅SiN)。再平坦化操作，诸如化学机械抛光，还可以穿插在图4中记录的步骤之间。
在刻蚀沟槽402、102之后，然后在沟槽402中和周围将所形成的介质406衬于沟槽402、102中(图6)。在实施方案中，该介质是生长在围绕沟槽的半导体阱或基板上的热氧化物。
在形成介质254之后，沉积并流动255可流动的CVD材料407(图7)。在流动该氧化物之后，可流动的CVD材料可以被平坦化(图8)以使晶片表面平整，在未被介质406占据的每个沟槽内的空间402A留下可流动的CVD材料407。在一个实施方案中，可流动的CVD材料407是氮化硅或含有硅、氮和氢的膜。
一旦形成介质406和可流动的CVD材料407，就执行掩模和刻蚀操作256以在介质406和可流动的CVD材料407中形成内部窄沟槽408(图9)，形成剩余的介质的形状406A(图9)和剩余的可流动CVD材料的形状407A以及在窄沟槽408的底部暴露基板或阱404。在内部沟槽408形成之后，在内部沟槽408的底部并在沟槽402内居中对准的半导体条410(图10)通过由阱或基板404引晶的外延生长258形成。在生长半导体条410之后，在移除259剩余的可流动材料407(图11)并在半导体条410上生长260栅氧化物412(图12)之前，可以任选地再平坦化正在形成的器件。
在栅氧化物412生长260之后，栅极导体414(图13)沉积262在栅氧化物412上并进入外延生长的半导体条410和介质406A之间的间隙，在一个实施方案中，栅极导体414是用钼硅化的多晶硅。
在沉积262栅极导体414之后，栅极导体被掩模和刻蚀264，以根据特定集成电路设计的需要用栅极区域130、124(图1)、重叠区域(如果有的话)128和延伸的互连区域129对该导体图案化。
在栅极导体414被掩模和刻蚀264之后，源极和漏极区域122、126被注入266，之后用传统的金属、通孔和接触沉积、掩模和刻蚀步骤完成268集成电路。
在实施方案中，在每个晶片上形成数十万或数百万个本文描述的横向竖直栅晶体管，每个数百万像素图像传感器的像素单元有一个或多个。
组合
一种指定为A的制造在宽沟槽中具有竖直栅的晶体管的方法，包括掩模和刻蚀宽沟槽；在宽沟槽中和周围形成介质；用可流动的材料填充宽沟槽；掩模和刻蚀以在宽沟槽中形成内部窄沟槽，从而暴露阱或基板。该方法继续在由内部窄沟槽暴露的阱或基板顶部外延生长由阱或基板引晶的半导体条；从宽沟槽中移除可流动的材料；在半导体条上生长栅氧化物；在栅氧化物上方以及在外延生长的半导体条和介质之间的间隙中形成栅极导体；掩模和刻蚀栅极导体；以及注入源极和漏极区域。
指定为AA的方法，包括指定为A的方法，其中宽沟槽的深度为50至400纳米。
指定为AB的方法，包括指定为A或AA的方法，其中半导体条主要包括硅。
指定为AC的方法，包括指定为A、AA或AB的方法，其中阱或基板主要包括硅。
指定为AD的方法，包括指定为A、AA、AB或AC的方法，其中栅极导体主要包括多晶硅。
指定为AE的方法，包括指定为A、AA、AB、AC或AD的方法，其中介质包括二氧化硅。
指定为AF的方法，包括指定为A、AA、AB、AC、AD或AE的方法，其中半导体条具有P型硅并且源极和漏极具有N型硅。
指定为AG的方法，包括指定为A、AA、AB、AC、AD、AE或AF的方法，其中可流动材料包括硅、氮和氢。
指定为B的竖直栅晶体管，包括从第二导电类型的源极区域延伸到第二导电类型的漏极区域的第一导电类型的半导体条，半导体条形成在沟槽内，沟槽壁用介质绝缘；在半导体条的两个竖直壁上形成的栅氧化物；以及在介质与栅氧化物之间的栅极材料。
指定为BA的竖直栅晶体管，包括指定为B的竖直栅晶体管，其中半导体条主要包括硅。
指定为BB的竖直栅晶体管，包括指定为B或BA的竖直栅晶体管，其中栅极材料主要包括多晶硅。
指定为BC的竖直栅晶体管，包括指定为B、BA或BC的竖直栅极晶体管，其中沟槽具有在50与400纳米之间的深度。
虽然已经参照本发明的优选实施方案具体地示出和描述了本发明，但是本领域技术人员将理解，在不脱离本发明的精神和范围的情况下，可以对形式和细节进行各种其他改变。应当理解，在使本发明适应于不同实施方案的过程中，可以在不脱离本文公开并由所附权利要求所理解的更广泛的发明概念下进行各种改变。

Claims (12)

1.一种制造在宽沟槽中具有竖直栅的晶体管的方法，包括：
掩模和刻蚀所述宽沟槽；
在所述宽沟槽中和周围形成介质；
用可流动的材料填充所述宽沟槽；
掩模和刻蚀以在所述宽沟槽中形成内部窄沟槽，从而暴露阱或基板；
在由所述内部窄沟槽暴露的所述阱或基板顶部外延生长由所述阱或基板引晶的半导体条；
从所述宽沟槽中移除所述可流动的材料；
在所述半导体条上生长栅氧化物；
在所述栅氧化物上方以及在外延生长的所述半导体条和所述介质之间的间隙中形成栅极导体；
掩模和刻蚀所述栅极导体；以及
注入源极和漏极区域。
2.根据权利要求1所述的方法，其中所述宽沟槽的深度为50至400纳米。
3.根据权利要求2所述的方法，其中所述半导体条主要包括硅。
4.根据权利要求2所述的方法，其中所述阱或基板主要包括硅。
5.根据权利要求3所述的方法，其中所述栅极导体主要包括多晶硅。
6.根据权利要求5所述的方法，其中所述介质包括可流动的化学气相沉积(CVD)氧化物。
7.根据权利要求6所述的方法，其中所述半导体条具有P型硅并且所述源极和漏极具有N型硅。
8.根据权利要求6所述的方法，其中所述可流动的材料包括硅、氮和氢。
9.一种竖直栅晶体管，包括：
从第二导电类型的源极区域延伸到所述第二导电类型的漏极区域的第一导电类型的半导体条，所述半导体条形成在沟槽内，所述沟槽的壁用介质绝缘；
在所述半导体条的两个竖直壁上形成的栅氧化物；以及
在所述介质和所述栅氧化物之间的栅极材料。
10.根据权利要求9所述的竖直栅晶体管，其中所述半导体条主要包括硅。
11.根据权利要求9所述的竖直栅晶体管，其中所述栅极材料主要包括多晶硅。
12.根据权利要求9至11中任一项所述的竖直栅晶体管，其中所述沟槽的深度在50与400纳米之间。
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