TW202315135A - 具有不同通道材料之經堆疊場效電晶體 - Google Patents

具有不同通道材料之經堆疊場效電晶體 Download PDF

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TW202315135A
TW202315135A TW111112432A TW111112432A TW202315135A TW 202315135 A TW202315135 A TW 202315135A TW 111112432 A TW111112432 A TW 111112432A TW 111112432 A TW111112432 A TW 111112432A TW 202315135 A TW202315135 A TW 202315135A
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channel
layer
semiconductor device
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瑞龍 謝
艾瑞克 米勒
郭德超
傑佛瑞 Ｃ 席瑞爾
范淑貞
朱立安 弗洛吉爾
維拉拉葛凡 Ｓ 貝斯克
俊利 王
城大 石
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美商萬國商業機器公司
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Abstract

一種半導體裝置包含至少一個第一環繞式閘極通道，該第一環繞式閘極通道具有一水平物理定向，其中該至少一個第一環繞式閘極通道由一第一材料構成，其中該至少一個第一環繞式閘極通道具有具備(100)晶向之一側壁表面。至少一個第二環繞式閘極通道具有一垂直物理定向，其中該第二通道位於該至少一個第一環繞式閘極通道上方，其中該至少一個第二環繞式閘極通道由一第二材料構成，其中該至少一個第二環繞式閘極通道具有具備(110)晶向之一側壁表面。一閘極金屬封閉該至少一個第一環繞式閘極通道及該至少一個第二環繞式閘極通道。

Description

具有不同通道材料之經堆疊場效電晶體
本發明大體上係關於經堆疊電晶體領域，更具體言之，係關於在特定通道定向上同時形成具有不同通道材料的電晶體，以增加結構中之通道遷移率。
經堆疊電晶體是一種有吸引力的進階CMOS節點裝置架構。藉由將一個裝置堆疊在另一個裝置上，除了習知閘極間距及BEOL金屬間距縮放之外，經堆疊電晶體還可以進一步實現面積縮放。習知經堆疊電晶體具有頂部及底部裝置，其中經堆疊電晶體使用相同的通道材料並具有相同的通道定向，這對於通道遷移率而言不是最佳的。
額外態樣及/或優點將在以下描述中被部分地闡述，且部分地將自該描述顯而易見，或可藉由實踐本發明而獲悉。
一種半導體裝置包含具有水平物理定向之至少一個第一環繞式閘極通道，其中至少一個第一環繞式閘極通道由第一材料構成，其中至少一個第一環繞式閘極通道具有具有(100)晶向之側壁表面。具有垂直物理定向之至少一個第二環繞式閘極通道，其中第二通道位於至少一個第一環繞式閘極通道上方，其中至少一個第二環繞式閘極通道由第二材料構成，其中至少一個第二環繞式閘極通道具有具有(110)晶向之側壁表面。閘極金屬，其封閉至少一個第一環繞式閘極通道及至少一個第二環繞式閘極通道。
提供參考隨附圖式之以下描述以輔助對如由申請專利範圍及其等效者所界定的本發明之例示性實施例的全面理解。以下描述包括各種特定細節以輔助該理解，但此等細節應被視為僅僅例示性的。因此，一般技術者將認識到，可在不脫離本發明之範疇及精神的情況下對本文中所描述之實施例進行各種改變及修改。另外，出於清楚及簡明起見，可省略熟知的功能及構造之描述。
以下描述及申請專利範圍中所使用之術語及詞語並不限於書面含義，而是僅僅用以實現對本發明之清楚且一致的理解。因此，對於熟習此項技術者而言應顯而易見，本發明之例示性實施例之以下描述係僅出於說明目的而非出於限制如由所附申請專利範圍及其等效者所界定之本發明的目的而提供。
應理解，除非上下文另有明確規定，否則單數形式「一(a/an)」及「該」包括複數個指示物。因此，舉例而言，除非上下文另有明確規定，否則對「一組件表面」之參考包括對此類表面中之一或多者之參考。
本文中揭示所主張結構及方法之詳細實施例：然而，可理解，所揭示實施例僅僅說明可以各種形式體現之所主張結構及方法。然而，本發明可以許多不同形式體現且不應被認作限於本文中所闡述之例示性實施例。更確切地，提供此等例示性實施例，使得本發明將透徹且完整並將向熟習此項技術者傳達本發明之範疇。在描述中，可省略熟知的特徵及技術之細節以避免不必要地混淆本實施例。
本說明書中對「一項實施例」、「一實施例」、「一實例實施例」等等之參考指示所描述之實施例可包括特定特徵、結構或特性，但每一實施例可不包括該特定特徵、結構或特性。此外，此類片語未必係指同一實施例。此外，當結合一實施例描述特定特徵、結構或特性時，應認為，無論是否予以明確地描述，結合其他實施例實現此類特徵、結構或特性係在一般技術者之認識範圍內。
出於下文中之描述之目的，術語「上部」、「下部」、「右側」、「左側」、「豎直」、「水平」、「頂部」、「底部」及其衍生詞應與所揭示結構及方法相關，如繪製圖中所定向。術語「上覆」、「在頂上」、「在頂部上」、「定位在上」或「定位在頂上」意謂諸如第一結構之第一元件存在於諸如第二結構上之第二元件，其中諸如界面結構之介入元件可存在於第一元件與第二元件之間。術語「直接接觸」意謂諸如第一結構之第一元件及諸如第二結構之第二元件在兩個元件之界面處沒有任何中間導電、絕緣或半導體層的情況下連接。
為了不混淆本發明之實施例之呈現，在以下詳細描述中，可能已將此項技術中已知之一些處理步驟或操作組合在一起以用於呈現並用於說明性目的，且在一些例項中可能尚未詳細地描述該等處理步驟或操作。在其他例項中，可能根本不描述此項技術中已知之一些處理步驟或操作。應理解，以下描述更確切地集中於本發明之各種實施例之獨特特徵或元件。
本文中參考相關圖式描述本發明之各種實施例。可在不脫離本發明之範疇的情況下設計出替代實施例。應注意，在以下描述及圖式中之元件之間闡述各種連接及位置關係(例如之上、下方、鄰近等等)。除非另有指定，否則此等連接及/或位置關係可為直接或間接的，且本發明在此方面不意欲為限制性的。因此，實體之耦接可指直接或間接耦接，且實體之間的位置關係可為直接或間接位置關係。作為間接位置關係之實例，在本描述中對在層「B」之上形成層「A」之參考包括一或多個中間層(例如層「C」)在層「A」與層「B」之間的情形，只要層「A」及層「B」之相關特性及功能並未被中間層實質上改變即可。
以下定義及縮寫將用於解譯申請專利範圍及本說明書。如本文中所使用，術語「包含(comprises/comprising)」、「包括(includes/including)」、「具有(has/having)」、「含有(contains/containing)」或其任何其他變化意欲涵蓋非獨占式包括。舉例而言，包含元件之清單的組合物、混合物、製程、方法、物品或設備未必僅限於該等元件，而是可包括未明確地列出或此類組合物、混合物、製程、方法、物品或設備所固有之其他元件。
另外，詞語｢例示性｣在本文中用以意謂｢充當實例、例項或說明｣。本文中被描述為「例示性」之任何實施例或設計未必被認作比其他實施例或設計較佳或有利。術語「至少一個」及「一或多個」可被理解為包括大於或等於一個之任何整數，亦即一個、兩個、三個、四個等等。術語「複數個」可被理解為包括大於或等於兩個之任何整數，亦即兩個、三個、四個、五個等等。術語「連接」可包括間接「連接」及直接「連接」兩者。
如本文中所使用，修飾本發明所使用之成分、組分或反應物之量的術語「約」係指可例如經由用於產生濃縮物或溶液之典型量測及液體處置程序而發生的數值量之變化。此外，可由於以下各者而發生變化：量測程序中之無意誤差；用以製成組合物或執行方法之成分之製造、源或純度之差異；及其類似者。術語「約」或「實質上」意欲包括與基於在申請本申請案時可用之裝備而對特定量進行之量測相關聯的誤差之程度。舉例而言，約可包括給定值之±8%或±5%或±2%之範圍。在另一態樣中，術語「約」意謂在所報告數值之5%內。在另一態樣中，術語「約」意謂在所報告數值之10%、9%、8%、7%、6%、5%、4%、3%、2%或1%內。
用以形成將封裝至積體電路(IC)中之微晶片之各種製程分成四個一般類別，亦即膜沈積、移除/蝕刻、半導體摻雜及圖案化/微影。沈積為將材料生長、塗佈或以其他方式轉移至晶圓上之任何製程。可用技術包括物理氣相沈積(PVD)、化學氣相沈積(CVD)、電化學沈積(ECD)、分子束磊晶(MBE)，及近年來的原子層沈積(ALD)等等。移除/蝕刻為自晶圓移除材料之任何製程。實例包括蝕刻製程(濕式或乾式)、反應性離子蝕刻(RIE)及化學機械平坦化(CMP)及其類似者。半導體摻雜為藉由摻雜例如電晶體源極及汲極(通常藉由擴散及/或藉由離子植入)來修改電性質。此等摻雜製程之後為熔爐退火或快速熱退火(RTA)。退火用以活化植入摻雜劑。導體(例如鋁、銅等等)及絕緣體(例如各種形式之二氧化矽、氮化矽等等)兩者之膜用以連接及隔離電組件。半導體基板之各種區域之選擇性摻雜允許藉由電壓之施加而改變基板之導電性。
現在將詳細地參考本發明之實施例，隨附圖式中繪示了該等實施例之實例，其中相同參考數字貫穿全文係指相同元件。經堆疊FET裝置可包括由Si通道或SiGe通道構成的經堆疊奈米片電晶體。通常，Si及SiGe通道電晶體皆具有水平定向(亦即，寬度方向比垂直高度更長)。
在形成具有特定定向(水平或垂直)之SiGe通道時，形成之通道的厚度會影響形成於通道中之缺陷率。例如，缺陷率隨著通道厚度的增加而增加。垂直定向通道(亦即垂直高度)往往會比水平定向通道更厚。需要更多製造時間來形成更厚的通道，因此有更多機會將缺陷引入至通道中。缺陷可被引入至由SiGe構成之水平通道中。缺陷可由形成通道、通道內之Ge百分比或導致缺陷之其他因素引起。通道內之缺陷率隨著Ge百分比的增加而增加，因此高Ge百分比往往會導致通道中形成更多的缺陷。通道內的缺陷形成率可藉由控制通道內之Ge百分比來控制或限制。由於缺陷率可藉由控制Ge百分比來管理，因此可形成具有垂直定向之SiGe通道。
在形成由Si構成之通道時，犧牲層用以分開各個Si層。用於犧牲層之材料通常為經摻雜Si，例如SiGe。一旦犧牲材料中之Ge%達到高比例(55%+)，則犧牲層中開始形成缺陷。因此，犧牲層中之Ge百分比低於55%。在製造期間，犧牲層被移除，但在犧牲層由SiGe構成且通道中的一者由SiGe構成時，會出現困難。能夠選擇性地移除單層SiGe並且不損壞另一層SiGe是困難的。可藉由控制層中之Ge百分比來實現層之選擇性針對。可藉由使犧牲層中之Ge百分比高於通道層中之Ge百分比，針對性地對犧牲層進行選擇性移除。垂直通道或水平通道由SiGe構成，其中Ge百分比在約5%至35%之範圍內。犧牲層由SiGe構成，其中犧牲層中之Ge百分比約為50%。犧牲層及通道中之Ge百分比差異可以實現選擇性地移除犧牲層，而只保留通道層。因此，可選擇性地蝕刻犧牲層而保留通道層。
電晶體之遷移率可藉由改變電晶體中的至少一者之物理定向(亦即，水平至垂直)而增加。此外，電晶體之遷移率可藉由控制電晶體之通道定向來最佳化。在下部NFET電晶體具有具備(100)晶向之通道側壁表面且上部PFET電晶體具有具備(110)晶向之通道側壁表面時，電晶體之結晶定向(結構)可以分別實現NFET及PFET之電子及電洞遷移率之最佳化。頂部電晶體具有垂直定向，通道側壁表面具有(110)晶向，而下部電晶體可具有垂直定向或水平定向，通道側壁表面具有(100)晶向。
圖1A展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖。圖1B展示根據本發明之實施例的經堆疊FET裝置100之自上而下視圖的橫截面A。圖1B展示在初始製造階段之後的經堆疊FET裝置100。經堆疊FET裝置100包括基板105、氧化物層110、第一層115、第二層120、第三層125、第四層130、第五層135、第六層140及硬遮罩145。第一層115、第三層125及第五層135為位於將為電晶體之層(亦即，第二層120及第四層130)上方及下方的犧牲層。圖中所示之層數僅出於例示性目的。可存在更少的層或更多的層，只要使用犧牲層來分開電晶體層即可。基板105可由矽晶圓、藍寶石晶圓或允許形成奈米片裝置100之任何類型的合適層構成。氧化物層110形成於基板105之頂部上。第一層115形成於氧化物層110之頂部上。第一層115可由例如SiGe 50%構成。第二層120形成於第一層115之頂部上。第二層120具有水平定向，亦即第二層120更寬而非更高。第三層125形成於第二層120之頂部上。第三層可由例如SiGe 50%構成。第四層130形成於第三層125之頂部上。第四層130具有水平定向，亦即第四層130更寬而非更高。第五層135形成於第四層130之頂部上。第五層135可由例如SiGe 50%構成。第一層115、第三層125及第五層135中之Ge濃度不限於50%。層中之Ge濃度需要具有足夠高的百分比，以區分犧牲層(亦即，第一層115、第三層125及第五層135)與Ge百分比較低的其他SiGe層。第六層140形成於第五層135之頂部上。圖1B展示已對第六層140進行處理，以在第五層135之頂部上形成複數個垂直鰭片。第二層120及第四層130由第一材料構成，且第六層140由第二材料構成。第一材料及第二材料中使用了不同的材料。第一材料可選自由Si或SiGe 5%-35%組成之群組。第二材料可選自由Si或SiGe 5%-35%組成之群組。例如，包含第二層120及第四層130之第一材料可為具有具備(100)晶向之通道側壁表面的Si，且包含第六層140之第二材料可為具有具備(110)晶向之通道側壁表面的SiGe 5%-35%。或者，包含第二層120及第四層130之第一材料可為具有具備(100)晶向之通道側壁表面的SiGe 5%-35%，且包含第六層140之第二材料可為具有具備(110)晶向之通道側壁表面的Si。硬遮罩145形成於第六層140之頂部上。
圖1B展示用以形成水平電晶體之由交替層構成之經堆疊FET堆疊的初始形成。圖1B展示含有兩個水平奈米片通道(亦即，第二層120及第四層130)之底部水平電晶體，但此僅出於例示性目的。經堆疊FET堆疊可由更少或更多的交替層構成，以增加或減小將形成之奈米片通道之數目。圖1B亦展示由兩個垂直通道(亦即，第六層140)構成之頂部水平電晶體之形成，但它可具有更少或更多的垂直通道。
圖2A展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖。圖2B展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖的橫截面A。間隔件150形成於第五層135、第六層140及硬遮罩145之曝露表面上。間隔件150例如藉由反應性離子蝕刻(RIE)進行蝕刻，以移除位於第五層135之頂部上的大部分間隔件150材料。剩餘的間隔件150位於第六層140及硬遮罩145的柱的側面上。
圖3A展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖。圖3B展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖的橫截面A。對奈米片堆疊之水平層進行蝕刻以減小第一層115、第二層120、第三層125、第四層130及第五層135之寬度。水平層之寬度減小到實質上等於垂直柱之總寬度。其中，垂直柱之總寬度由間隔件150、第六層140及硬遮罩145之組合寬度構成。圖3B及3C展示一種界定底部奈米片寬度之方式。或者，可應用微影及蝕刻製程以將底部奈米片堆疊圖案化至不同於頂部電晶體之垂直柱之總寬度的寬度。
圖4A展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖。圖4B展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖的橫截面A。間隔件150及硬遮罩145被移除，且虛設閘極152形成於氧化物層110、奈米片堆疊及柱之曝露表面的頂部上。虛設閘極152封閉奈米片堆疊之水平區段的曝露區域及柱之垂直區段的曝露區域。硬遮罩155形成於虛設閘極152之頂部上。
圖4C展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖的橫截面B。在虛設閘極152圖案化之後，閘極間隔件160形成於虛設閘極152及硬遮罩155之側壁處。此後，選擇性SiGe50壓痕製程用以在犧牲層(亦即，第一層115、第三層125及第五層135)上方形成空腔。請注意，藉由使具有SiGex之頂部溝道材料140中的Ge%小於35%，能夠在SiGe50內部創建此等空腔而不會損壞頂部通道材料(亦即，第六層140)。此後，內部間隔件185形成於第一層115、第三層125及第五層135之側上以填充該等空腔。此後，形成底部源極/汲極epi 165、隔離層170及頂部源極/汲極epi 175。底部源極/汲極epi層165可選自由N-epi或P-epi材料組成之群組。頂部源極/汲極epi層175可選自由N-epi或P-epi組成之群組。
圖5A展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖。圖5B展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖的橫截面A。虛設閘極152及硬式光罩155被移除，繼之以移除犧牲層(亦即，第一層115、第三層125及第五層135)。藉由使犧牲層中之Ge%高於頂部通道(亦即，第六層140)，能夠藉由合適的化學方法(諸如汽相HCl)選擇性地移除犧牲材料而不會損壞頂部通道。此後，形成替換閘極190，其可由從由以下組成的群組中選出的材料構成：高k閘極介電質、功函數金屬及導電閘極金屬填充材料。高k金屬閘極190封閉第二層120、第四層130及第六層140。圖5C展示根據本發明之實施例的經堆疊FET裝置100的自上而下視圖的橫截面B。經堆疊FET裝置100進行替代製程，其中具有高Ge%之層(亦即第一層115、第三層125及第五層135)被替換為替換閘極190。替換閘極190另外填充位於間隔件160之間的空間，此係因為虛設閘極152被移除。第二ILD 195形成於柱中之每一者之間的第二epi層175之頂部上。在此階段，頂部PFET具有SiGe通道材料及(110)表面定向，這有利於增強電洞遷移率。底部NFET裝置具有Si通道及(100)表面定向，這有利於電子遷移率。
圖6展示根據本發明之實施例的形成裝置200之製程階段的橫截面。裝置200包括在基板205上方之接合通道210。在執行晶圓接合時，故意地旋轉供體或受體晶圓45度。定界通道210可由諸如氧化物之接合介電質構成。基板205及上層215包含不同材料。基板205材料可為Si，且上層215材料可為SiGe 5-50%，或者，基板205材料可為SiGe 5-50%，且上層215材料可為Si。
圖7展示根據本發明之實施例的形成裝置200之製程階段的橫截面。對裝置200進行蝕刻以形成由基板205、晶圓接合層210及上層215構成之至少一個鰭片。圖7展示兩個鰭片之形成，然而，裝置200可具有比圖7所示更少或更多的鰭片。淺溝槽隔離層220形成於基板205之頂部上。因為45度旋轉是在晶圓接合之前完成，所以頂部(上層215)及底部通道(基板205)可在通道側壁表面處具有不同的晶向。在頂部通道材料215為SiGe的情況下，側壁表面具有(110)晶向，且對於底部Si通道205，側壁表面具有(100)晶向。
圖8展示根據本發明之實施例的形成裝置200之製程階段的橫截面。在裝置200製造之下游階段，高k金屬閘極225形成於淺溝槽隔離層220之頂部上。高k金屬閘極225封閉鰭片，使得高k金屬閘極225與包含各柱之基板205、晶圓接合層210及上層215的側面直接接觸。在此階段，頂部PFET具有SiGe通道材料及(110)表面定向，這有利於增強電洞遷移率。底部NFET裝置具有Si通道及(100)表面定向，這有利於電子遷移率。
圖9展示根據本發明之實施例的形成裝置300之製程階段的橫截面。裝置包括在基板305上方之接合通道315。在晶圓接合之前，磊晶犧牲層(第一犧牲層310及第二犧牲層320)包含生長於基板305及接合通道315上方之高Ge% SiGe (＞50% Ge%)。在執行晶圓接合時，故意地旋轉供體或受體晶圓45度。接合通道315可由諸如氧化物之接合介電質構成。上層325形成於第二犧牲層320之頂部上。基板305及上層325包含不同材料。基板305可由Si構成，且上層可由SiGe 5-35%構成，或者基板305材料可為SiGe 5-35%，且上層325材料可為Si。
圖10展示根據本發明之實施例的形成裝置300之製程階段的橫截面。對裝置300進行蝕刻以形成由基板305、第一犧牲層310、晶圓接合層315、第二犧牲層320及上層325構成之至少一個鰭片。圖10展示兩個鰭片之形成，然而，裝置300可具有比圖10中所示更少或更多的柱。淺溝槽隔離層330形成於基板305之頂部上。因為45度旋轉是在晶圓接合之前完成，所以頂部及底部通道可在通道側壁表面處具有不同晶向。在頂部通道材料(上層325)為SiGe的情況下，側壁表面具有(110)晶向，且對於底部Si通道(基板305)，側壁表面具有(100)晶向。
圖11展示根據本發明之實施例的形成裝置300之製程階段的橫截面。使用替代製程在淺溝槽隔離層330的頂部上形成高k金屬閘極335。替代製程用高k金屬閘極335替代第一犧牲層310及第二犧牲層320。高k金屬閘極335封閉柱之下部區段的三個側面，使得高k金屬閘極335與基板305之三個側面直接接觸。高k金屬閘極335另外封閉晶圓接合層315之所有側面，且高k金屬閘極335封閉上層325之所有側面。因為使用了低Ge% SiGe材料325 (Ge%＜35%)，所以可以移除具有高Ge%之SiGe材料(第一犧牲層310及第二犧牲層320)而不會損壞通道材料(上層325)。在此階段，頂部PFET具有SiGe通道材料及(110)表面定向，這有利於增強電洞遷移率。底部NFET裝置具有Si通道及(100)表面定向，這有利於電子遷移率。
儘管本發明已參考其某些例示性實施例予以展示及描述，但熟習此項技術者應理解，可在不脫離如由所附申請專利範圍及其等效者所界定的本發明之精神及範疇的情況下對該等例示性實施例進行形式及細節上之各種改變。
已出於說明目的而呈現本發明之各種實施例之描述，但該等描述並不意欲為詳盡的或限於所揭示之實施例。在不脫離所描述實施例之範疇及精神的情況下，許多修改及變化對於一般技術者而言將顯而易見。本文中所使用之術語經選擇以最佳地解釋一或多項實施例之原理、實際應用或對用於市場中之技術之技術改良，或使其他一般技術者能夠理解本文中所揭示之實施例。
100:經堆疊FET裝置 105:基板 110:氧化物層 115:第一層 120:第二層 125:第三層 130:第四層 135:第五層 140:第六層 145:硬遮罩 150:間隔件 152:虛設閘極 155:硬遮罩 160:硬遮罩 165:底部源極/汲極epi 170:隔離層 175:頂部源極/汲極epi 185:內部間隔件 190:高k金屬閘極 195:第二ILD 200:裝置 205:裝置 210:接合通道/晶圓接合層 215:上層/頂部通道材料 220:淺溝槽隔離層 225:高k金屬閘極 300:裝置 305:裝置 310:第一犧牲層 315:接合通道/晶圓接合層 320:第二犧牲層 325:上層 330:淺溝槽隔離層 335:高k金屬閘極
本發明之某些例示性實施例之以上及其他態樣、特徵及優點將自結合隨附圖式進行的以下描述更顯而易見，在隨附圖式中：
圖1A展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖。
圖1B展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖的橫截面A。
圖2A展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖。
圖2B展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖的橫截面A。
圖3A展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖。
圖3B展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖的橫截面A。
圖4A展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖。
圖4B展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖的橫截面A。
圖4C展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖的橫截面B。
圖5A展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖。
圖5B展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖的橫截面A。
圖5C展示根據本發明之實施例的經堆疊FET裝置的自上而下視圖的橫截面B。
圖6展示根據本發明之實施例的形成裝置之製程階段的橫截面。
圖7展示根據本發明之實施例的形成裝置之製程階段的橫截面。
圖8展示根據本發明之實施例的形成裝置之製程階段的橫截面。
圖9展示根據本發明之實施例的形成裝置之製程階段的橫截面。
圖10展示根據本發明之實施例的形成裝置之製程階段的橫截面。
圖11展示根據本發明之實施例的形成裝置之製程階段的橫截面。
105:基板
110:氧化物層
115:第一層
120:第二層
125:第三層
130:第四層
135:第五層
140:第六層
145:硬遮罩

Claims (20)

  1. 一種半導體裝置，其包含： 至少一個第一環繞式閘極通道，其具有一水平物理定向，其中該至少一個第一環繞式閘極通道由一第一材料構成，其中該至少一個第一環繞式閘極通道具有具備(100)晶向之一側壁表面； 至少一個第二環繞式閘極通道，其具有一垂直物理定向，其中該第二通道位於該至少一個第一環繞式閘極通道上方，其中該至少一個第二環繞式閘極通道由一第二材料構成，其中該至少一個第二環繞式閘極通道具有具備(110)晶向之一側壁表面；及 一閘極金屬，其封閉該至少一個第一環繞式閘極通道及該至少一個第二環繞式閘極通道。
  2. 如請求項1之半導體裝置，其中該第一材料及該第二材料不同。
  3. 如請求項1之半導體裝置，其中該第一材料為Si。
  4. 如請求項3之半導體裝置，其中該第二材料為Si1-xGex，其中Ge百分比x為5%至35%。
  5. 如請求項1之半導體裝置，其中該第一材料為SiGe 5至35$。
  6. 如請求項5之半導體裝置，其中該第二材料為Si。
  7. 一種半導體裝置，其包含： 至少一個下部通道，其具有一垂直物理定向，其中該通道更高而非更寬，其中該至少一個下部通道具有具備(100)晶向之一側壁表面，其中該至少一個下部通道由一第一材料構成；及 至少一個上部通道，其具有一垂直物理定向，其中該通道更高而非更寬，其中該至少一個上部通道具有具備(110)晶向之一側壁表面，其中該至少一個上部通道由一第二材料構成，其中該第一材料及該第二材料不同。
  8. 如請求項7之半導體裝置，其中該第一材料為Si。
  9. 如請求項8之半導體裝置，其中該第二材料為SiGe 5%至35%。
  10. 如請求項7之半導體裝置，其中該第一材料為SiGe 5至35$。
  11. 如請求項10之半導體裝置，其中該第二材料為Si。
  12. 如請求項7之半導體裝置，其中該至少一個下部通道為一雙閘控通道。
  13. 如請求項12之半導體裝置，其中該至少一個上部通道為一三閘控通道。
  14. 如請求項13之半導體裝置，其進一步包含位於該至少一個下部通道與該至少一個上部通道之間的一晶圓接合層。
  15. 如請求項14之半導體裝置，其中該至少一個下部通道與該晶圓接合層之一第一側直接接觸，且該至少一個上部通道與該晶圓接合層之一第二側直接接觸，其中該晶圓接合層之該第一側不同於該晶圓接合層之該第二側。
  16. 如請求項7之半導體裝置，其中該至少一個下部通道為一三閘控通道。
  17. 如請求項16之半導體裝置，其中該至少一個上部通道為一環繞式閘極通道。
  18. 如請求項17之半導體裝置，其進一步包含位於該至少一個下部通道與該至少一個上部通道之間的一晶圓接合層。
  19. 如請求項18之半導體裝置，其進一步包含 一閘極金屬，其與該至少一個下部通道之三個側直接接觸，其中該閘極金屬封閉該晶圓接合層，且其中該閘極金屬封閉該至少一個上部通道。
  20. 一種方法，其包含： 在一基板上形成一第一層犧牲層； 用第一半導體材料形成一第一底部水平奈米片，該第一半導體材料具有具備(100)晶向之側壁表面； 在該第一水平通道層頂部上形成一第二犧牲層； 用第一半導體材料形成一第二底部水平奈米片，該第一半導體材料具有具備(100)晶向之側壁表面； 在該第二水平通道層頂部上形成一第三犧牲層； 用第二半導體材料形成頂部垂直FIN，該第二半導體材料具有具備(110)晶向之側壁表面，其中該第一半導體材料及該第二半導體材料不同；及 蝕刻該第三通道，使得該第三通道具有一垂直定向。
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