TW202211413A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202211413A
TW202211413A TW110103635A TW110103635A TW202211413A TW 202211413 A TW202211413 A TW 202211413A TW 110103635 A TW110103635 A TW 110103635A TW 110103635 A TW110103635 A TW 110103635A TW 202211413 A TW202211413 A TW 202211413A
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transmission path
semiconductor device
terminating resistor
wiring
series
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TW110103635A
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TWI771888B (zh
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大塚靖夫
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日商鎧俠股份有限公司
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Abstract

抑制訊號的品質的降低。 半導體裝置係具備： 配線基板，其係包含第1～第3焊墊； 晶片層疊體，其係包含被逐步層疊於配線基板上的複數的半導體晶片，半導體晶片的各者具有第1、第2及第3連接墊，複數的第1～第3連接墊會分別經由複數的第1～第3接合線來串聯，且藉由分別被串聯至第1～第3焊墊來形成第1～第3傳送路；及 至少一個的終端電阻，其係從由被連接至第1及第2傳送路的第1終端電阻和被連接至第1及第3傳送路的第2終端電阻所組合的群來選擇，且被設在晶片層疊體上。

Description

半導體裝置
本發明的實施形態是有關半導體裝置。 關聯申請案的引用 本案是以2020年09月9日先行申請的日本專利申請案第2020-151299號的優先權基礎且享受其權益，並將其內容全體引用於此。
大規模積體電路(LSI)等的半導體裝置是具備具有被層疊於配線基板上的複數的半導體晶片的晶片層疊體。晶片層疊體是藉由接合線來電性連接至配線基板。
一實施形態是在於提供一種抑制訊號的品質的降低之半導體裝置。
實施形態的半導體裝置係具備： 配線基板，其係包含：被電性連接至訊號端子的第1焊墊、被電性連接至電源端子的第2焊墊、及被電性連接至接地端子的第3焊墊； 晶片層疊體，其係包含被逐步層疊於配線基板上的複數的半導體晶片，半導體晶片的各者具有第1、第2及第3連接墊，複數的第1連接墊會經由複數的第1接合線來串聯，且藉由被串聯至第1焊墊來形成第1傳送路，複數的第2連接墊會經由複數的第2接合線來串聯，且藉由被串聯至第2焊墊來形成第2傳送路，複數的第3連接墊會經由複數的第3接合線來串聯，且藉由被串聯至第3焊墊來形成第3傳送路；及 至少一個的終端電阻，其係從由被連接至第1及第2傳送路的第1終端電阻和被連接至第1及第3傳送路的第2終端電阻所組成的群來選擇，且被設在晶片層疊體上。
若根據上述的構成，則可提供一種抑制訊號的品質的降低之半導體裝置。
以下，參照圖面說明有關實施形態。被記載於圖面的各構成要素的厚度與平面尺寸的關係、各構成要素的厚度的比率等是有與現物不同的情況。並且，在實施形態中，實質相同的構成要素是附上相同的符號而適當省略說明。
在本說明書中所謂的「連接」是除了特別指定的情況以外，不僅物理性地連接，還包含電性連接。
(第1實施形態) 以下說明有關半導體裝置的構造例。圖1是用以說明半導體裝置的構造例的剖面模式圖。圖2是用以說明半導體裝置的構造例的上面模式圖。半導體裝置100是具備配線基板1、晶片層疊體2、複數的終端電阻3及絕緣樹脂層4。
配線基板1是具有：被設在第1表面1a的複數的外部連接端子11、及被設在第1表面的相反側的第2表面1b的複數的焊墊(bonding pad)12。配線基板1的例子是包含印刷配線板(PWB)。
複數的外部連接端子11是包含訊號端子、電源端子及接地端子。外部連接端子11是例如使用金、銅、焊錫等來形成。外部連接端子11是例如亦可使用錫-銀系、錫-銀-銅系的無鉛焊錫來形成。又，亦可使用複數的金屬材料的層疊來形成外部連接端子11。另外，在圖1中，使用導電性球來形成外部連接端子11，但亦可使用凸塊來形成外部連接端子11。
複數的焊墊12是經由配線基板1的內部配線來連接至複數的外部連接端子11。複數的焊墊12是包含：被電性連接至訊號端子的第1焊墊121、及連接至電源端子的第2焊墊122、及被電性連接至接地端子的第3焊墊123。複數的焊墊12是例如含有銅、銀、金或鎳等的金屬元素。例如，藉由電解電鍍法或無電解電鍍法等來形成含上述材料的電鍍膜，藉此亦可形成複數的焊墊12。又，亦可使用導電性膏來形成複數的焊墊12。
晶片層疊體2是包含複數的半導體晶片20。半導體晶片20的例子是包含記憶體晶片。複數的半導體晶片20是被逐步層疊於配線基板1的第2表面1b上。換言之，複數的半導體晶片20是彼此部分地重疊。複數的半導體晶片20是例如夾著晶粒黏結薄膜(DAF(Die Attach Film))等的接著層而彼此接著。 圖1所示的晶片層疊體2是具有4個的半導體晶片20，但半導體晶片20的數量是被限定於圖1所示的數量。
複數的半導體晶片20的各者是具有複數的連接墊21。複數的半導體晶片20是經由複數的接合線22來連接。複數的連接墊21是包含：第1連接墊211、第2連接墊212及第3連接墊213。複數的接合線22是包含：複數的第1接合線221、複數的第2接合線222及複數的第3接合線223。
複數的半導體晶片20的複數的第1連接墊211是經由複數的第1接合線221來串聯，且被串聯至第1焊墊121，藉此形成第1傳送路。
複數的半導體晶片20的複數的第2連接墊212是經由第2接合線222來串聯，且被串聯至第2焊墊122，藉此形成第2傳送路。
複數的半導體晶片20的複數的第3連接墊213是經由第3接合線223來串聯，且被串聯至第3焊墊123，藉此形成第3傳送路。
接合線22是例如含有金、銀、銅、鋁等的金屬元素。
複數的終端電阻3是被設在晶片層疊體2上。複數的終端電阻3是包含第1晶片電阻器31及第2晶片電阻器32。該等的晶片電阻器是例如經由接著層來安裝於晶片層疊體2上。第1晶片電阻器31是被連接至第1傳送路及第2傳送路。第2晶片電阻器32是被連接至第1傳送路及第3傳送路。藉由使用上述晶片電阻器，例如可縮小終端電阻3的面積。終端電阻3的電阻值是不被特別加以限定，例如50Ω以上。
圖3是圖2的一部分的擴大圖。第1晶片電阻器31是具有：被連接至第1傳送路的第1電極墊311、及被連接至第2傳送路的第2電極墊312。第2晶片電阻器32是具有：被連接至第1傳送路的第1電極墊321、及被連接至第3傳送路的第2電極墊322。
半導體裝置100是只要至少具有一個的終端電阻3即可。圖4及圖5是用以說明半導體裝置100的其他的構造例的模式圖。半導體裝置100的其他的構造例是如圖4所示般未具有第1晶片電阻器31，或如圖5所示般未具有第2晶片電阻器32。有關該等的不同點以外的部分，可適當援用圖1及圖2所示的半導體裝置100的說明。
絕緣樹脂層4是覆蓋晶片層疊體2、接合線22及終端電阻3。絕緣樹脂層4是含有氧化矽(SiO2 )等的無機充填材，例如使用將無機充填材與有機樹脂等混合的密封樹脂，藉由轉移成型法、壓縮成型法、射出成型法等的模製法來形成。
在本實施形態的半導體裝置中，藉由將第1晶片電阻器31的電阻值、第2晶片電阻器32的電阻值、或第1晶片電阻器31及第2晶片電阻器32的並列合成電阻值予以和第1傳送路的特性阻抗匹配，抑制經由訊號端子的訊號的反射波。
在此，為了說明終端電阻3之反射波的抑制效果，參照圖6及圖7來說明有關半導體記憶裝置的記憶體與記憶體控制器的連接構成、及與訊號的品質的降低的關係。圖6是半導體記憶裝置的等效電路圖。圖7是表示經由訊號端子來輸出入的訊號的EYE圖案的例圖。
半導體記憶裝置是具備由晶片層疊體2所組成的記憶體及記憶體控制器5。晶片層疊體2是具有電容成分C1及電感成分L1。記憶體控制器5是具有電容成分C2及電感成分L2。晶片層疊體2與記憶體控制器5是經由配線基板1來電性連接。該等的要素是形成上述第1傳送路。
在半導體記憶裝置中，例如在讀出時經由第1傳送路來產生訊號的反射波。因此，例如訊號的偏差會變大，EYE圖案6會崩潰。上述現象是晶片層疊體2與記憶體控制器5之間的轉送速度越高越顯著。
對於此，如圖6所示般，藉由將終端電阻3連接至第1傳送路，而將終端電阻3的電阻值予以和第1傳送路的特性阻抗匹配，可抑制訊號的反射波。藉此，可抑制EYE圖案6的崩潰。因此，可抑制訊號的品質的降低。
以往的半導體裝置之一，將終端電阻連接至訊號線(該訊號線是連接至單一的半導體晶片)的情形為人所知。然而，如本實施形態的半導體裝置般，層疊複數的半導體晶片時，若不使由電性連接半導體晶片間的導體及半導體晶片的連接墊所組成的傳送路的特性阻抗和終端電阻的電阻值匹配，則難以抑制訊號的反射波。
又，以往的半導體裝置的其他之一，使用在包含半導體晶片內的輸入元件之輸入電路中內藏終端電阻的晶粒上終止(on-dietermination，ODT)的情形為人所知。然而，ODT是當由電性連接半導體晶片間的導體及半導體晶片的連接墊所組成的傳送路的特性阻抗為10數Ω小時，ODT的電路尺寸會變大，半導體晶片的尺寸會變大。又，若ODT在電路設計的階段不納入終端方式的切換電路及ODT的電阻值的調整電路，則無法終端方式的切換及ODT的電阻值的調整，因此在電路設計後無法靈活的變更。
對於此，在本實施形態的半導體裝置中，藉由在晶片層疊體上設置被連接至包含連接複數的半導體晶片的接合線的第1傳送路之終端電阻，各半導體晶片是哪個的終端電阻也不須具有。藉此，可提高半導體晶片的電路設計的自由度。
(第2實施形態) 以下說明有關半導體裝置的其他的構造例。圖8是用以說明半導體裝置的其他的構造例的剖面模式圖。圖9是用以說明半導體裝置的其他的構造例的上面模式圖。半導體裝置100是具備：配線基板1、晶片層疊體2、複數的終端電阻3及絕緣樹脂層4。有關配線基板1、晶片層疊體2及絕緣樹脂層4是與第1實施形態的半導體裝置的配線基板1、晶片層疊體2及絕緣樹脂層4相同，因此省略說明，可適當援用第1實施形態的說明。
複數的終端電阻3是被設在晶片層疊體2上。複數的終端電阻3是包含第1配線33及第2配線34。該等的配線是例如藉由濺射或電鍍等的方法來形成於晶片層疊體2的表面。配線是例如包含金、銀、銅、鈦、鉻等的材料。第1配線33是被連接至第1傳送路及第2傳送路。第2配線34是被連接至第1傳送路及第3傳送路。藉由使用上述配線，可例如容易調整終端電阻3的電阻值。
圖10是圖9的一部分的擴大圖。第1配線33是具有：被連接至第1傳送路的一端、及被連接至第2傳送路的另一端。第2配線34是具有：被連接至第1傳送路的一端、及被連接至第3傳送路的另一端。
半導體裝置100是只要具有至少一個的終端電阻3即可。圖11及圖12是用以說明半導體裝置100的其他的構造例的模式圖。半導體裝置100的其他的構造例是如圖11所示般未具有第1配線33、或如圖12所示般未具有第2配線34。有關該等的不同點以外的部分是可適當援用圖8及圖9所示的半導體裝置100的說明。
圖9～圖12所示的第1配線33及第2配線34的平面形狀是具有迴路(loop)形狀，但第1配線33及第2配線34的平面形狀是不被特別加以限定。 圖13是用以說明第1配線33及第2配線34的其他的平面形狀的模式圖。第1配線33及第2配線34的其他的平面形狀是具有蜿蜒(meander)形狀。藉此，可容易增加終端電阻3的電阻。
圖14及圖15是用以說明半導體裝置100的其他的構造例的模式圖。半導體裝置100的其他的構造例是如圖14所示般不持有具有蜿蜒形狀的第1配線33，或如圖15所示般不持有具有蜿蜒形狀的第2配線34。有關該等的不同點以外的部分是可適當援用圖8及圖9所示的半導體裝置100的說明。
在本實施形態的半導體裝置中，藉由將第1配線33的電阻值、第2配線34的電阻值、或第1配線33及第2配線34的並列合成電阻值予以和第1傳送路的特性阻抗匹配，可抑制經由訊號端子的訊號的反射波。因此，可抑制訊號的品質的降低。
又，在本實施形態的半導體裝置中，藉由在晶片層疊體上設置被連接至包含連接複數的半導體晶片的接合線的第1傳送路之終端電阻，各半導體晶片是哪個的終端電阻也不須具有。藉此，可提高半導體晶片的電路設計的自由度。
說明了本發明的幾個的實施形態，但該等的實施形態是作為例子提示者，不是意圖限定發明的範圍。該等新穎的實施形態是亦可以其他各種的形態實施，可在不脫離發明的主旨的範圍進行各種的省略、置換、變更。該等實施形態或其變形為發明的範圍及主旨所包含，且為申請專利範圍記載的發明及其均等的範圍所包含。
1:配線基板 1a:第1表面 1b:第2表面 2:晶片層疊體 3:終端電阻 4:絕緣樹脂層 5:記憶體控制器 6:EYE圖案 11:外部連接端子 12:焊墊 20:半導體晶片 21:連接墊 22:接合線 31:第1晶片電阻器 32:第2晶片電阻器 33:第1配線 34:第2配線 100:半導體裝置 121:第1焊墊 122:第2焊墊 123:第3焊墊 211:第1連接墊 212:第2連接墊 213:第3連接墊 221:第1接合線 222:第2接合線 223:第3接合線 311:第1電極墊 312:第2電極墊 321:第1電極墊 322:第2電極墊 C1:電容成分 C2:電容成分 L1:電感成分 L2:電感成分
[圖1]是用以說明半導體裝置的構造例的剖面模式圖。 [圖2]是用以說明半導體裝置的構造例的上面模式圖。 [圖3]是圖2的一部分的擴大圖。 [圖4]是用以說明半導體裝置的其他的構造例的模式圖。 [圖5]是用以說明半導體裝置的其他的構造例的模式圖。 [圖6]是半導體記憶裝置的等效電路圖。 [圖7]是表示經由訊號端子來輸出入的訊號的EYE圖案的例圖。 [圖8]是用以說明半導體裝置的其他的構造例的剖面模式圖。 [圖9]是用以說明半導體裝置的其他的構造例的上面模式圖。 [圖10]是圖9的一部分的擴大圖。 [圖11]是用以說明半導體裝置的其他的構造例的模式圖。 [圖12]是用以說明半導體裝置的其他的構造例的模式圖。 [圖13]是用以說明第1配線及第2配線的其他的平面形狀的模式圖。 [圖14]是用以說明半導體裝置的其他的構造例的模式圖。 [圖15]是用以說明半導體裝置的其他的構造例的模式圖。
1:配線基板
1a:第1表面
1b:第2表面
2:晶片層疊體
3:終端電阻
4:絕緣樹脂層
11:外部連接端子
12:焊墊
20:半導體晶片
21:連接墊
22:接合線
100:半導體裝置

Claims (6)

  1. 一種半導體裝置，其特徵係具備： 配線基板，其係包含：被電性連接至訊號端子的第1焊墊、被電性連接至電源端子的第2焊墊、及被電性連接至接地端子的第3焊墊； 晶片層疊體，其係包含被逐步層疊於前述配線基板上的複數的半導體晶片，前述半導體晶片的各者具有第1、第2及第3連接墊，複數的前述第1連接墊會經由複數的第1接合線來串聯，且藉由被串聯至前述第1焊墊來形成第1傳送路，複數的前述第2連接墊會經由複數的第2接合線來串聯，且藉由被串聯至前述第2焊墊來形成第2傳送路，複數的前述第3連接墊會經由複數的第3接合線來串聯，且藉由被串聯至前述第3焊墊來形成第3傳送路；及 至少一個的終端電阻，其係從由被連接至前述第1及第2傳送路的第1終端電阻和被連接至前述第1及第3傳送路的第2終端電阻所組成的群來選擇，且被設在前述晶片層疊體上。
  2. 如請求項1記載的半導體裝置，其中， 前述第1終端電阻的電阻值，係與前述第1傳送路的特性阻抗匹配， 前述第2終端電阻的電阻值，係與前述第1傳送路的特性阻抗匹配。
  3. 如請求項1記載的半導體裝置，其中，前述至少一個的終端電阻，係包含前述第1終端電阻及前述第2終端電阻， 前述第1及第2終端電阻的並列合成電阻值，係與前述第1傳送路的特性阻抗匹配。
  4. 如請求項1～請求項3之任一項記載的半導體裝置，其中， 前述第1終端電阻，係包含第1晶片電阻器，該第1晶片電阻器具有：被連接至前述第1傳送路的第1電極墊、及被連接至前述第2傳送路的第2電極墊， 前述第2終端電阻，係包含第2晶片電阻器，該第2晶片電阻器具有：被連接至前述第1傳送路的第3電極墊、及被連接至前述第3傳送路的第4電極墊。
  5. 如請求項1～請求項3之任一項記載的半導體裝置，其中， 前述第1終端電阻，係包含第1配線，該第1配線具有：被連接至前述第1傳送路的一端、及被連接至前述第2傳送路的另一端； 前述第2終端電阻，係包含第2配線，該第2配線具有：被連接至前述第1傳送路的一端、及被連接至前述第3傳送路的另一端。
  6. 如請求項1～請求項3之任一項記載的半導體裝置，其中，前述複數的半導體晶片的各者，係不具有終端電阻。
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