TW202203331A - 封裝基板及其製作方法 - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 71
- 229910000679 solder Inorganic materials 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 105
- 239000011521 glass Substances 0.000 claims description 55
- 239000000463 material Substances 0.000 claims description 21
- 229920005989 resin Polymers 0.000 claims description 12
- 239000011347 resin Substances 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 239000011135 tin Substances 0.000 claims description 4
- 230000008054 signal transmission Effects 0.000 abstract description 9
- 230000005540 biological transmission Effects 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 14
- 239000010949 copper Substances 0.000 description 12
- 230000017525 heat dissipation Effects 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical class [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229930040373 Paraformaldehyde Natural products 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- -1 polyoxymethylene Polymers 0.000 description 1
- 229920006324 polyoxymethylene Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
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Abstract
一種封裝基板及其製作方法,方法包括:提供玻璃框架,玻璃框架設置有通孔和埋芯空腔;在埋芯空腔內部固定電子構件;塗覆介質層至玻璃框架上表面、通孔和埋芯空腔並固化;對介質層進行光刻,形成開窗,開窗設置在通孔上方;經由開窗沉積金屬,並對金屬進行圖形製作,形成金屬柱和線路層,金屬柱貫穿通孔,線路層設置在玻璃框架的上表面和/或下表面,與電子構件和金屬柱連接;在線路層表面形成阻焊層,並對阻焊層進行圖形製作形成焊墊,焊墊與線路層連接。封裝基板可降低電子構件的訊號傳輸損耗和傳輸延時,提升訊號傳輸性能和基板可靠性。
Description
本發明關於半導體封裝技術領域,尤其關於一種封裝基板及其製作方法。
隨著電子產業的蓬勃發展,電子產品體積日趨輕薄,整合密度日益提高,採用嵌埋封裝基板的封裝方式得以大力發展。目前在嵌埋封裝基板的應用中,封裝方式通常為貼裝電子構件後經由壓合有機介質材料來完成封裝。
但目前有機介質材料主要為聚醯亞胺、環氧樹脂或雙馬來醯亞胺-三嗪樹脂或它們與玻璃纖維的共混物,此類材料的介電常數(Dk)、介電損耗(Df)相對較大,在產品電訊號傳遞過程中,會導致延時時間長,電訊號損耗大等缺點,很大程度上限制了高頻產品的應用;同時有機介質與所嵌埋的電子構件或晶片的熱膨脹係數(CTE)差異較大,在極限條件下,容易發生由漲縮不匹配引起的可靠性問題;另外,在封裝過程中使用傳統的壓合方式,會導致晶片在壓合過程中出現碎裂的風險。
本發明旨在至少在一定程度上解決相關技術中的技術問題之一。為此,本發明提出一種封裝基板及其製作方法,以下是對本文詳細描述的主題的概述。本概述並非是為了限制發明專利範圍的保護範圍。技術方案如下:
第一方面,本發明實施例提供一種封裝基板製作方法,包括以下步驟:
提供玻璃框架,玻璃框架設置有通孔和埋芯空腔;
在埋芯空腔內部固定電子構件;
塗覆介質層至玻璃框架的上表面、通孔和埋芯空腔並固化;
對介質層進行光刻,形成開窗,開窗設置在通孔和電子構件上方;
經由開窗沉積金屬,並對金屬進行圖形製作,形成金屬柱和線路層,金屬柱貫穿通孔,線路層設置在玻璃框架的上表面和/或下表面,與電子構件和金屬柱連接;
在線路層表面形成阻焊層,並對阻焊層進行圖形製作形成焊墊,焊墊與線路層連接。
根據本發明第一方面實施例的封裝基板製作方法,至少具有以下技術效果:第一方面,本發明提出的封裝基板採用玻璃框架取代有機基質框架,利用玻璃的低介電常數和低介電損耗的材料特性降低電子構件的電訊號傳輸損耗,提高電訊號傳送速率從而提升電訊號傳輸性能;第二方面,玻璃框架具有較廣的熱膨脹係數(CTE),在於嵌埋的電子構件基材匹配時選擇性較多,在極限條件下,可以滿足產品的設計需求和可靠性;協力廠商面,使用塗覆封裝介質材料的方式取代壓合封裝,減小了電子構件在封裝過程中所受的壓合力,降低了嵌埋產品在製作過程中電子構件碎裂的風險;第四方面,玻璃基板加工成本較低,可有效降低產品的製作成本。
可選地,在本發明的一實施例中,開窗還可以設置在電子構件上方。
可選地,在本發明的一實施例中,還包括沉積金屬種子層,金屬種子層貼附在通孔側壁以及介質層和電子構件的表面。
可選地,在本發明的一實施例中,金屬種子層材料包括金屬鈦和金屬銅。
可選地,在本發明的一實施例中,還包括在焊墊的表面形成保護層。
可選地,在本發明的一實施例中,保護層材料包括鎳鈀金、鎳金、錫、銀、有機保焊膜。
可選地,在本發明的一實施例中,通孔和埋芯空腔的數量至少為1個,多個埋芯空腔的體積可以相同也可以不同。
可選地,在本發明的一實施例中,介質層為感光型樹脂材料,具有流動性。
第二方面,本發明實施例提供了一種封裝基板,包括:
玻璃框架,玻璃框架設置有通孔和埋芯空腔;
電子構件,設置在埋芯空腔內部;
介質層,填充在玻璃框架上表面和埋芯空腔內;
金屬柱,貫穿於通孔;
線路層,設置在玻璃框架的上表面和/或下表面,與電子構件和金屬柱連接;
阻焊層,設置在線路層表面,阻焊層設置有焊墊,焊墊與線路層連接。
根據本發明第二方面實施例的封裝基板,至少具有以下有益效果:第一方面,本發明提出的封裝基板採用玻璃框架取代有機基質框架,利用玻璃的低介電常數和低介電損耗的材料特性降低電子構件的電訊號傳輸損耗,提高電訊號傳送速率從而提升電訊號傳輸性能;第二方面,玻璃框架具有較廣的熱膨脹係數(CTE),在於嵌埋的電子構件基材匹配時選擇性較多,在極限條件下,可以滿足產品的設計需求和可靠性;協力廠商面,使用塗覆封裝介質材料的方式取代壓合封裝,減小了電子構件在封裝過程中所受的壓合力,降低了嵌埋產品在製作過程中電子構件碎裂的風險;第四方面,玻璃基板加工成本較低,可有效降低產品的製作成本。
可選地,在本發明的一實施例中,還包括金屬種子層,金屬種子層貼附在通孔側壁以及介質層和電子構件的表面。
可選地,在本發明的一實施例中,還包括保護層,設置在焊墊的上表面。
本發明的其它特徵和優點將在隨後的說明書中闡述,並且,部分地從說明書中變得顯而易見,或者經由實施本發明而瞭解。本發明的目的和其他優點可經由在說明書、申請專利範圍以及圖式中所特別指出的結構來完成和獲得。
為了使本發明的目的、技術方案及優點更加清楚明白,以下結合圖式及實施例,對本發明進行進一步詳細說明。應當理解,此處所描述的具體實施例僅用以解釋本發明,並不用於限定本發明,故不具技術上的實質意義,任何結構的修飾、比例關係的改變或大小的調整,在不影響本發明所能產生的功效及所能達成的目的下,均應仍落在本發明所揭示的技術內容得能涵蓋的範圍內。
本部分將詳細描述本發明的具體實施例,本發明之較佳實施例在圖式中示出,圖式的作用在於用圖形補充說明書文字部分的描述,使人能夠直觀地、形象地理解本發明的每個技術特徵和整體技術方案,但其不能理解為對本發明保護範圍的限制。
在發明的描述中,若干的含義是一個或者多個,多個的含義是兩個及兩個以上,大於、小於、超過等理解為不包括本數,以上、以下、以內等理解為包括本數。如果有描述到第一、第二只是用於區分技術特徵為目的,而不能理解為指示或暗示相對重要性或者隱含指明所指示的技術特徵的數量或者隱含指明所指示的技術特徵的先後關係。
參照圖1,本發明的一實施例提供的一種封裝基板製作方法包括以下步驟:
S100,提供玻璃框架100,玻璃框架100設置有通孔110和埋芯空腔120,具體地,如圖2所示,首先準備玻璃基板,通常為透明的玻璃,玻璃基板的厚度可根據嵌埋結構需求進行設定,對玻璃基板進行雷射雷射,雷射路徑L的玻璃性質改變可以進行刻蝕,以蝕刻藥水對雷射路徑進行刻蝕,形成帶有通孔110和埋芯空腔120結構的玻璃框架100,刻蝕藥水主要為氫氟酸溶液,刻蝕藥水的濃度可根據蝕刻速率和蝕刻厚度的要求進行調整,需要說明的是,雷射加工,又名雷射加工是利用高能量密度的光束,照射到材料表面,使材料汽化或發生顏色變化的加工過程,雷射加工過程中,雷射光束能量密度高,加工速度快,並且是局部加工,對非雷射照射部位沒有或影響極小,在微電子行業可以用於半導體器件和晶片的加工,也可以用於精密光學器件的加工;雷射埋芯空腔120和通孔110的數量分別至少為1個,用於嵌埋電子構件200和電子構件200的電極引出及散熱(見圖3)。在本發明的一實施例中,埋芯空腔120的數量為兩個,並且兩個埋芯空腔120的體積不同,可以同時貼裝不同型號大小的電子構件200(見圖3),通孔110數量為兩個,分別對應設置在兩個埋芯空腔120的一側。
S200,在埋芯空腔120內部固定電子構件200,具體地,如圖3所示,在玻璃框架100底部黏貼膠帶900,使通孔110和埋芯空腔120底部暫時封閉,膠帶900可對後續貼的電子構件200進行預固定;分別在體積不同的兩個埋芯空腔120中貼裝電子構件200,使電子構件200的一端與膠帶900接觸固定,需要說明的是,電子構件200按照是否有接線端子分為正面和反面,電子構件200包括但不限於裝置、晶片,可以是主動裝置也可以是被動裝置,可以是獨立的晶片或裝置,也可以是多顆晶片或者裝置的組合,按用途分類可以是不同的功率裝置,還可以是射頻或邏輯晶片,晶片或裝置的種類和數量可根據實際需求按照3D背靠背堆疊多顆晶片的組合,也可以是上下左右單層陣列組合設計。電子構件200可以正面向下安裝於埋芯空腔120中,還可以反面安裝於埋芯空腔120中電子構件200具體的安裝方向和安裝數量以及安裝種類可依據設計需求進行設置,均屬於本發明的保護範圍。
S300,塗覆介質層300至玻璃框架100上表面、通孔110和埋芯空腔120並固化,具體地,如圖4所示,貼裝電子構件200後,在玻璃框架100的上表面塗覆介質層300,介質層300材料為感光型樹脂材料,感光型樹脂材料具有流動性,藉由樹脂材料的流動性將通孔110和貼裝有電子構件200的埋芯空腔120的空隙填滿,塗覆樹脂材料後進行預烘烤使樹脂介質處於固化狀態,需要說明的是,感光型樹脂材料是熱固型的樹脂材料,包括JSR WPR(水溶性酚醛樹脂)系列、Hitachi AR-5100(丙烯酸酯類)系列、Asahi LV(聚甲醛)系列等,塗覆時黏度範圍在10Pa.s~10000Pa.s。
S400,對介質層300進行光刻,形成開窗310,開窗310設置在通孔110和電子構件200上端,具體地,如圖5所示,對感光型樹脂材料進行曝光、顯影,進行圖形製作在通孔110上方位置上形成開窗310結構,將玻璃框架100通孔110露出來,同時也可根據電子構件200是否需要散熱進行光刻形成電子構件200背面開窗310,後續可在電子構件200的背面電鍍金屬進行散熱;曝光顯影後,進行後烘烤,將樹脂材料完全固化,需要說明的是,可根據電子構件200的大小及散熱要求選擇性在背面進行開窗,對於面積大,散熱要求高的電子構件200可以藉由形成開窗310後進行背面金屬沉積進行散熱,對於面較小,散熱要求不高的電子構件200則可以不用形成開窗310,直接經由介質層300進行散熱即可。
S500,經由開窗310沉積金屬,並對金屬進行圖形製作,形成金屬柱410和線路層420,金屬柱410貫穿通孔110,線路層420設置在玻璃框架100的上表面和下表面,與電子構件200連接,具體地,如圖6所示,去除玻璃框架100下表面黏貼的膠帶900,在玻璃框架100的上下表面製作金屬種子層600,使金屬種子層600覆蓋在通孔110側壁,電子構件200視窗露出面以及整個玻璃框架100框架周圍,製作金屬種子層600可選擇沉積銅和物理濺射金屬鈦和金屬銅(Ti/Cu)等方式,本發明實施例中,較佳的,採用物理濺射Ti/Cu的方式,Ti/Cu厚度可根據製程能力綜合調整,Ti厚度通常為50~150nm,Cu厚度通常為0.5~1.5um;如圖7所示,建立種子層後,在種子層表面貼附感光阻擋層800,並對感光阻擋層800進行圖形製作,露出線路層420和通孔110位置,電鍍金屬,具體為電鍍金屬銅,使銅金屬覆蓋通孔110和特定位置的金屬種子層600上表面,形成金屬柱410和線路層420,部分線路層420經由金屬種子層600與電子構件200連接,達到散熱和電極引出的作用;在如圖8所示,使用有機或者無機脫膜液進行脫膜,去除感光阻擋層800,對金屬種子層600進行刻蝕,使金屬種子層600與線路層420保持一致,需要說明的是,形成線路層420和金屬柱410還可以經由另外一種流程製作,具體為整個玻璃框架100框架周圍電鍍金屬銅,形成金屬柱410,對表面金屬銅進行圖形製作,刻蝕形成線路層420,再脫膜進行金屬種子層600刻蝕,另外,本發明的一些實施例中還可以是進行多層玻璃框架100的封裝,可以是兩層,也可以多層,根據實際產品佈線需求進行設計封裝。
S600,在線路層420表面形成阻焊層500,並對阻焊層500形成焊墊510,焊墊510與線路層420連接,具體地,如圖9所示,在如圖8所示結構的上下表面製作阻焊層500,阻焊層500厚度根據實際需求來定義,根據電極位置需求進行圖形製作形成焊墊510,具體的,分別在金屬柱410上下表面、電子構件200表面形成焊墊510,在本發明的一實施例中,部分線路層420與電子構件200的引線端子相連接,經由線路層420連接至金屬柱410以及金屬柱410表面的焊墊510,進行電極引出和電子構件200的散熱,部分線路層420直接覆蓋在電子構件200的表面,經由線路層420和焊墊510進行散熱,進一步的在焊墊510表面形成保護層,經由覆蓋保護層可以防止焊墊510氧化,增強基板的可靠性,保護層可經由沉積鎳鈀金、鎳金、錫、銀等化學穩定的金屬,還包括覆蓋有機保焊膜進行表面處理。
參照圖9,本發明提供了一種封裝基板結構,包括:玻璃框架100,玻璃框架100設置有通孔110和埋芯空腔120;電子構件200,設置在埋芯空腔120內部;介質層300,填充在玻璃框架100上表面和埋芯空腔120內;金屬柱410,貫穿于通孔110,線路層420,設置在玻璃框架100的上表面和下表面,與電子構件200和金屬柱410連接;阻焊層500,設置在線路層420表面,阻焊層500設置有焊墊510,焊墊510與線路層420連接。
在一實施例中,玻璃框架100為透明材質,玻璃框架100內設置有一個或多個通孔110和埋芯空腔120,埋芯空腔120用於貼裝電子構件200,埋芯空腔120體積和數量根據預埋入基板內部的電子構件200的種類和數量進行匹配設置,在玻璃框架100的上表面設置有介質層300,介質層300填充在埋芯空腔120內,將電子構件200包裹固定並平鋪在玻璃框架100的上表面,經由介質層300一方面可以將電子構件200與玻璃框架100進行固定,一方面可以保護玻璃基板,防止玻璃基板破碎,在玻璃基板內部還設置有金屬柱410,金屬柱410貫穿于通孔110結構延伸出玻璃框架100的上下表面與線路層420連接,線路層420同時與電子構件200連接,電子構件200一方面可以經由線路層420將產生的熱量傳遞至金屬柱410進行散熱,另一方面經由線路層420將電極引出,方便與其他元件或者基板進行連接,在線路層420的最外層設置有阻焊層500,用於基板絕緣,阻焊層500對應金屬柱410和線路層420位置設置有焊墊510,用於電性連接或測試。
參照圖9,本發明的一實施例提供了一種封裝基板結構,還包括金屬種子層600,金屬種子層600貼附在通孔110側壁以及介質層300和電子構件200表面。
在一實施例中,在玻璃框架100的上下表面還設置有金屬種子層600,覆蓋在通孔110側壁,電子元金屬種子層600厚度可根據製程能力綜合調整,本發明實施例中,較佳的,金屬鈦厚度通常50~150nm,金屬銅度通常0.5~1.5um。
參照圖9,本發明的一實施例提供了一種封裝基板結構,還包括保護層,設置在焊墊510的上表面(圖中未示出),在一實施例中,保護層可以防止焊墊510氧化,增強基板的可靠性,保護層材料包括鎳鈀金、鎳金、錫、銀等化學穩定的金屬或者有機保焊膜。
以上是對本發明的較佳實施進行了具體說明,但本發明並不局限於上述實施方式,熟悉本領域的技術人員在不違背本發明精神的前提下還可作出各種的等同變形或替換,這些等同的變形或替換均包含在本發明權利要求所限定的範圍內。
100:玻璃框架
110:通孔
120:埋芯空腔
200:電子構件
300:介質層
310:開窗
410:金屬柱
420:線路層
500:阻焊層
510:焊墊
600:金屬種子層
800:感光阻擋層
900:膠帶
L:雷射路徑
S100:步驟
S200:步驟
S300:步驟
S400:步驟
S500:步驟
S600:步驟
圖式用來提供對本發明技術方案的進一步理解,並且構成說明書的一部分,與本發明的實施例一起用於解釋本發明的技術方案,並不構成對本發明技術方案的限制。
圖1是本發明一實施例提供的封裝基板製作方法的步驟流程圖;
圖2至圖8是本發明另一實施例提供的封裝基板製作方法步驟對應的截面圖;
圖9是本發明另一實施例提供的封裝基板的截面圖。
構件焊墊
S100:步驟
S200:步驟
S300:步驟
S400:步驟
S500:步驟
S600:步驟
Claims (10)
- 一種封裝基板製作方法,包括以下步驟: 提供一玻璃框架,所述玻璃框架設置有一通孔和一埋芯空腔; 在所述埋芯空腔內部固定一電子構件; 塗覆一介質層至所述玻璃框架的一上表面、所述通孔和所述埋芯空腔並固化; 對所述介質層進行光刻,形成一開窗,所述開窗設置在所述通孔上方; 經由所述開窗沉積金屬,並對所述金屬進行圖形製作,形成一金屬柱和一線路層,所述金屬柱貫穿所述通孔,所述線路層設置在所述玻璃框架的所述上表面和一下表面中之至少一者,與所述電子構件和所述金屬柱連接; 在所述線路層表面形成一阻焊層,並對所述阻焊層進行圖形製作形成一焊墊,所述焊墊與所述線路層連接。
- 如請求項1所述的封裝基板製作方法,其中,所述開窗還設置在所述電子構件上方。
- 如請求項1所述的封裝基板製作方法,其中,還包括沉積金屬種子層,所述金屬種子層貼附在所述通孔側壁以及所述介質層和所述電子構件的一表面。
- 如請求項1所述的封裝基板製作方法,其中,還包括在所述焊墊的表面形成一保護層。
- 如請求項4所述的封裝基板製作方法,其中,所述保護層材料包括鎳鈀金、鎳金、錫、銀、有機保焊膜中之一者。
- 如請求項1所述的封裝基板製作方法,其中,所述通孔和所述埋芯空腔的數量至少為1個,多個所述埋芯空腔的體積彼此相同或相異。
- 如請求項1所述的封裝基板製作方法,其中,所述介質層為感光型樹脂材料,具有流動性。
- 一種封裝基板,包括: 一玻璃框架,所述玻璃框架設置有一通孔和一埋芯空腔; 一電子構件,設置在所述埋芯空腔內部; 一介質層,填充在所述玻璃框架的一上表面和所述埋芯空腔內; 一金屬柱,貫穿於所述通孔; 一線路層,設置在所述玻璃框架的所述上表面和一下表面中之至少一者,與所述電子構件和所述金屬柱連接; 一阻焊層,設置在所述線路層表面,所述阻焊層設置有一焊墊,所述焊墊與所述線路層連接。
- 如請求項8所述的封裝基板,其中,還包括一金屬種子層,所述金屬種子層貼附在所述通孔側壁以及所述介質層和所述電子構件的一表面。
- 如請求項8所述的封裝基板,其中,還包括一保護層,設置在所述焊墊的一上表面。
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CN113471347A (zh) * | 2021-05-14 | 2021-10-01 | 南通越亚半导体有限公司 | Led嵌埋封装基板及其制造方法 |
CN113451259B (zh) * | 2021-05-14 | 2023-04-25 | 珠海越亚半导体股份有限公司 | 一种多器件分次嵌埋封装基板及其制造方法 |
CN113658936A (zh) * | 2021-08-16 | 2021-11-16 | 浙江水晶光电科技股份有限公司 | 一种金属化玻璃及其制备方法 |
CN116666232B (zh) * | 2023-08-01 | 2024-02-23 | 广东佛智芯微电子技术研究有限公司 | 全玻璃堆叠封装结构及其制备方法 |
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