TW202114158A - 具有埋置交叉耦合互連的結構及ｓｒａｍ位元單元 - Google Patents

具有埋置交叉耦合互連的結構及ｓｒａｍ位元單元 Download PDF

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TW202114158A
TW202114158A TW109116234A TW109116234A TW202114158A TW 202114158 A TW202114158 A TW 202114158A TW 109116234 A TW109116234 A TW 109116234A TW 109116234 A TW109116234 A TW 109116234A TW 202114158 A TW202114158 A TW 202114158A
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effect transistor
field effect
layer
sacrificial layer
source
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TW109116234A
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TWI738342B (zh
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畢爾Ｃ 保羅
朱利安 弗羅吉爾
謝瑞龍
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明揭示包括互補場效電晶體的結構及靜態隨機存取記憶體位元單元以及形成此類結構及位元單元的方法。埋置交叉耦接互連沿垂直方向設置於第一場效電晶體及第二場效電晶體下方。該埋置交叉耦接互連與該第一場效電晶體的閘極電極耦接，且該埋置交叉耦接互連還與該第二場效電晶體的源/汲區耦接。

Description

具有埋置交叉耦合互連的結構及SRAM位元單元
本發明關於半導體裝置製造及積體電路，尤其關於包括互補場效電晶體的結構及SRAM位元單元(bit cell)以及形成此類結構及位元單元的方法。
靜態隨機存取記憶體(static random access memory；SRAM)可例如用以臨時儲存電腦系統中的資料。SRAM裝置包括位元單元陣列，其中，各位元單元在操作期間保留單一位元(single bit)的資料。各SRAM位元單元可具有6電晶體(6T)設計，其包括提供儲存元件的一對交叉耦接的反相器(inverter)，以及將該反相器與互補位元線(bit line)連接的一對通閘(pass-gate)電晶體。該通閘電晶體由字線控制，該字線用以選擇該SRAM記憶體單元進行讀取或寫入操作。當連續供電時，SRAM裝置的記憶體狀態持續不變，而無需資料刷新操作。
場效電晶體的裝置結構通常包括源/汲區，以及經配置以切換在該源/汲區之間的半導體本體中所形成的主動通道(active channel)中的載子流(carrier flow)的閘極電極。當向該閘極電極施加超過指定臨界電壓的控制電壓時，在該源/汲區之間的該通道中的該載子流產生裝置輸出電流。
可利用互補場效電晶體構造SRAM位元單元的反相器，其中，堆 疊不同晶體類型的源/汲區並由共用閘極電極控制主動通道。通過延伸該閘極電極並利用上方互連結構中的金屬化層將各反相器的閘極電極與相對反相器的源/汲區連接來實施交叉耦接連接。不過，這些交叉耦接連接可能需要對經生長以提供源/汲區的半導體材料圖案化，且該交叉耦接連接可能促使該位元單元的尺寸擴大。
需要包括互補場效電晶體的改進的結構及SRAM位元單元以及形成此類結構及位元單元的方法。
在本發明的實施例中，一種結構包括：具有閘極電極的第一場效電晶體，具有源/汲區的第二場效電晶體，以及沿垂直方向設置於該第一場效電晶體及該第二場效電晶體下方的埋置交叉耦接互連。該埋置交叉耦接互連與該第一場效電晶體的該閘極電極耦接，且該埋置交叉耦接互連還與該第二場效電晶體的該源/汲區耦接。
在本發明的實施例中，一種方法包括形成第一犧牲層、第二犧牲層，以及位於該第一犧牲層與該第二犧牲層之間的第三犧牲層。用介電材料替代該第一犧牲層及該第二犧牲層，以分別形成第一介電層及第二介電層。在用該介電材料替代該第一犧牲層及該第二犧牲層以後，用導體替代該第三犧牲層，以形成與第一場效電晶體的閘極電極耦接的埋置交叉耦接互連。該方法進一步包括在該第二介電層上方形成第二場效電晶體的源/汲區，以及形成將該埋置交叉耦接互連與該第二場效電晶體的該源/汲區耦接的接觸(contact)。
10:層堆疊
12:奈米片通道層
14,16,18:犧牲層
15:薄層
20:基板
22:本體特徵
22a:平行段、段
22b:橫向段、段
24:淺溝槽隔離區
25:介電覆蓋層
26,27:犧牲閘極結構
28,29,64,66:腔體
30,56,58:側間隙壁
32,34,36,48,54,62:介電層
37,38,39,40:鰭片
42:內間隙壁
43,45,73:側表面
44,46:源/汲區
50,92:層間介電層
60:蝕刻遮罩
68,69:介電柱
70:閘極結構
71:閘極覆蓋層
72:埋置交叉耦接互連
76,78:接觸開口
82,84,86,88,90:接觸
85:覆蓋層
94:金屬線
96:SRAM(靜態隨機存取記憶體)位元單元
100,102:CFET(互補場效電晶體)
104,106:場效電晶體
BLC:互補位元線
BLT:位元線
PD:下拉電晶體
PU:上拉電晶體
VDD:正供應電壓
VSS:負供應電壓
WL:字線
包含於並構成本說明書的一部分的附圖示例說明本發明的各種實施例，並與上面所作的概括說明以及下面所作的詳細說明一起用以解釋本發明的該些實施例。
圖1顯示依據本發明的實施例處於製程方法的初始製造階段的裝置結構的剖視圖。
圖2顯示大體沿圖2A中的線2-2所作的該裝置結構的剖視圖。
圖2A顯示圖2的裝置結構的頂視圖。
圖3顯示大體沿圖3C中的線3-3所作的該裝置結構的剖視圖。
圖3A顯示大體沿圖3C中的線3A-3A所作的該裝置結構的剖視圖。
圖3B顯示大體沿圖3C中的線3B-3B所作的該裝置結構的剖視圖。
圖3C顯示圖3、3A、3B的裝置結構的簡化示意頂視圖。
圖4-15顯示處於圖3的製造階段之後的連續製造階段的圖3的裝置結構的剖視圖。
圖4A-15A顯示處於圖3A的製造階段之後的連續製造階段的圖3A的裝置結構的剖視圖。
圖4B-15B顯示處於圖3B的製造階段之後的連續製造階段的圖3B的裝置結構的剖視圖。
圖5C顯示圖5、5A、5B的裝置結構的簡化示意頂視圖，其中，大體沿線5-5作圖5，大體沿線5A-5A作圖5A，以及大體沿線5B-5B作圖5B。
圖10C顯示圖10、10A、10B的裝置結構的簡化示意頂視圖，其中，大體沿線10-10作圖10，大體沿線10A-10A作圖10A，以及大體沿線10B-10B作圖10B。
圖12C顯示圖12、12A、12B的裝置結構的簡化示意頂視圖，其中，大體沿線12-12作圖12，大體沿線12A-12A作圖12A，以及大體沿線12B-12B作圖12B。
圖14C顯示圖14、14A、14B的裝置結構的簡化示意頂視圖，其中，大體沿線14-14作圖14，大體沿線14A-14A作圖14A，以及大體沿線14B-14B作圖14B。
圖16顯示利用場效電晶體構造的6電晶體SRAM位元單元的電路圖。
請參照圖1並依據本發明的實施例，層堆疊10包括奈米片通道層12、犧牲層14、犧牲層16，以及設置於犧牲層16之間的犧牲層18。層堆疊10中位於中央的一對相鄰的最近鄰犧牲層14由薄層15隔開，該薄層由與奈米片通道層12相同的半導體材料組成。層堆疊10設置於基板20上，犧牲層16、18沿垂直方向設置於層12、14與基板20之間。奈米片通道層12及犧牲層14、16、18可通過外延生長製程順序形成，通過選擇反應物，在生長期間交替組分，以提供交替佈置。基板20可由單晶半導體材料例如單晶矽組成，其通過為該外延生長提供晶體結構模板來致能(enable)該外延生長。
可相對奈米片通道層12及犧牲層14、18選擇性地通過蝕刻製程 移除犧牲層16，且可相對奈米片通道層12選擇性地通過蝕刻製程移除犧牲層14及犧牲層18。可通過在不同層12、14、16、18之間提供組分的差異來提供該蝕刻選擇性。奈米片通道層12由半導體材料組成，且犧牲層14及犧牲層18由經選擇以相對奈米片通道層12的半導體材料被選擇性移除的不同半導體材料組成。犧牲層18由半導體材料組成，且犧牲層16由經選擇以相對犧牲層18的半導體材料被選擇性移除的不同半導體材料組成。在提到材料移除製程(例如，蝕刻)時本文中所使用的術語“選擇性”表示通過合適的蝕刻劑選擇，目標材料的材料移除速率(也就是，蝕刻速率)大於暴露於該材料移除製程的至少另一種材料的移除速率。
在一個實施例中，奈米片通道層12可由矽組成，且犧牲層14、16、18可由矽鍺(SiGe)組成。在一個實施例中，與犧牲層18相比，犧牲層16可具有較高的鍺含量。在一個實施例中，與犧牲層14相比，犧牲層16可具有較高的鍺含量。在一個實施例中，犧牲層16可具有比犧牲層14高的鍺含量以及比犧牲層18高的鍺含量。在一個實施例中，犧牲層14可具有與犧牲層18大致相同的鍺含量。在一個實施例中，犧牲層16可具有約百分之五十(50%)的鍺含量，且犧牲層14及18可具有約百分之二十五(25%)的鍺含量。
請參照圖2、2A，其中類似的附圖標記表示圖1中類似的特徵，且在該製程方法的下一製造階段，通過光刻及蝕刻製程圖案化層堆疊10，以形成本體特徵22。本體特徵22可包括一對平行段22a，該對平行段由橫向段22b在中心連接，以提供H形狀。為此，在層堆疊10上方通過光刻可形成蝕刻遮罩。該蝕刻遮罩可包括例如光阻層，其通過旋塗製程施加，經預烘烤、暴露於通過光遮罩所投射的電磁輻射、曝光後烘烤，以及用化學顯影劑顯影，以定義掩蔽層堆 疊10的頂部表面上的區域的H形狀。使用蝕刻製程移除被該蝕刻遮罩暴露的未掩蔽區域上的層堆疊10的半導體材料。
該蝕刻製程還在該未掩蔽區上形成以淺深度進入基板20中的淺溝槽。在基板20中的這些淺溝槽中形成淺溝槽隔離區24。淺溝槽隔離區24圍繞本體特徵22。淺溝槽隔離區24可由通過化學氣相沉積沉積並通過蝕刻製程回蝕刻的介電材料例如二氧化矽組成。
請參照圖3、3A、3B、3C，其中類似的附圖標記表示圖2、2A中類似的特徵，且在該製程方法的下一製造階段，犧牲閘極結構26、27橫跨本體特徵22形成，尤其分別與本體特徵22的平行段22a疊置形成。本體特徵22的橫向段22b橫向設置於犧牲閘極結構26、27之間。犧牲閘極結構26、27可包括形成於本體特徵22的暴露表面上方的薄介電層(例如，二氧化矽層)，以及半導體材料例如非晶矽，其通過化學氣相沉積沉積並利用硬遮罩通過反應離子蝕刻圖案化。犧牲閘極結構26、27經設置以橫跨本體特徵22的最上奈米片通道層12，與該本體特徵的平行段22a的側壁疊置，並且還橫跨位於平行段22a之間並與其相鄰的淺溝槽隔離區24。在各犧牲閘極結構26、27上方設置介電覆蓋層(dielectric cap)25。這些介電覆蓋層25可由例如氮化矽組成，且可為在圖案化期間所使用的硬遮罩的剩餘部分。
在形成犧牲閘極結構26、27以後，相對奈米片通道層12及犧牲層14及18選擇性地通過蝕刻製程移除犧牲層16。移除犧牲層16的該蝕刻製程可經選擇以因該犧牲層的高鍺含量而選擇性移除犧牲層16的半導體材料。犧牲層14及18至少部分由於它們的較低鍺含量而未被移除，且奈米片通道層12至少部分由於沒有鍺含量而未被移除。犧牲層16的該移除在本體特徵22的基部 形成腔體28、29，該些腔體在本體特徵22的側面開放。犧牲閘極結構26、27提供在犧牲層16的該移除以後支持層堆疊10的橋。腔體28沿垂直方向設置於基板20與犧牲層18之間，且腔體29沿垂直方向設置於最下犧牲層14與犧牲層18之間。
請參照圖4、4A、4B，其中類似的附圖標記表示圖3、3A、3B、3C中類似的特徵，且在該製程方法的下一製造階段，側間隙壁(spacer)30形成於層堆疊10的最上奈米片通道層12的頂部表面上，並鄰近各犧牲閘極結構26、27及其介電覆蓋層25的側壁設置。側間隙壁30可由共形沉積的低k介電材料組成，例如通過原子層沉積共形沉積的SiOCN，並接著通過非等向性(anisotropic)蝕刻製程例如反應離子蝕刻蝕刻。
該共形沉積的介電材料還被沉積於腔體28、29(圖3、3A、3B)內部作為介電層32、34以及本體特徵22的側壁上作為介電層36。形成側間隙壁30的該蝕刻製程還凹入介電層36至相對於基板20的頂部表面及淺溝槽隔離區24高於現在由介電層34填充的最上腔體29的位置的高度。介電層32、34、36及犧牲閘極結構26、27圍繞並包覆犧牲層18，且介電層32還提供相對於基板20的最終裝置結構中的電性隔離。尤其，凹入的介電層36在未被犧牲閘極結構26、27覆蓋的本體特徵22的側壁覆蓋犧牲層18，且介電層34設置於犧牲層18上方。
請參照圖5、5A、5B、5C，其中類似的附圖標記表示圖4、4A、4B中類似的特徵，且在該製程方法的下一製造階段，通過相對介電層32、34、36選擇性凹入本體特徵22的蝕刻製程移除本體特徵22的段22b以及本體特徵22的段22a的部分，以形成鰭片37、38、39、40。凹入本體特徵22的該蝕刻製 程可經選擇以相對於介電層32、34、36的介電材料選擇性移除奈米片通道層12及犧牲層14的半導體材料。犧牲閘極結構26、27及側間隙壁30用以自對準該蝕刻製程。
在移除本體特徵22的段22b的區域上暴露介電層34、36。介電層34、36的介電材料可在該蝕刻製程期間充當蝕刻停止層。犧牲層18被包覆介電層32、34、36及犧牲閘極結構26、27保護並保留，以免被該蝕刻製程移除，否則犧牲層18容易被該蝕刻製程移除。在本體特徵22的該圖案化之後，被包覆的犧牲層18延伸於所有鰭片37、38、39、40下方。
鰭片37、38、39、40彼此斷開並相互隔開。鰭片37及38由犧牲閘極結構26及其側間隙壁30疊置。鰭片39及40由犧牲閘極結構27及其側間隙壁30疊置。後續可使用鰭片38及40形成互補場效電晶體，其中，具有相反導電類型的該場效電晶體被堆疊，且其可被用作SRAM位元單元中的上拉(pull-up)與下拉(pull-down)電晶體的緊湊組合。後續可使用鰭片37及39形成奈米片場效電晶體，其可被用作SRAM位元單元中的通閘或存取電晶體。
在形成鰭片37、38、39、40以後，在鰭片37、38、39、40的側壁中所定義的凹部(indent)內部形成內間隙壁42。為此，通過相對構成奈米片通道層12的材料選擇性蝕刻構成犧牲層14的材料的等向性(isotropic)蝕刻製程，相對於奈米片通道層12橫向凹入犧牲層14。由於奈米片通道層12未被該蝕刻製程橫向凹入，因此犧牲層14的該橫向凹入在各鰭片37、38、39、40的側壁中生成凹部。為形成內間隙壁42，可沉積由介電材料組成的共形層，例如通過原子層沉積沉積的氮化矽，其通過夾止(pinch-off)填充該凹部，並接著執行蝕刻製程，以移除位於該凹部外部的該共形層。
請參照圖6、6A、6B，其中類似的附圖標記表示圖5、5A、5B中類似的特徵，且在該製程方法的下一製造階段，鄰近鰭片37、38、39、40的相對側壁形成源/汲區44及源/汲區46。本文中所使用的術語“源/汲區”是指可充當奈米片場效電晶體的源極或汲極的半導體材料的摻雜區。源/汲區44與位於鰭片37、38、39、40的下部中的奈米片通道層12物理耦接，且源/汲區46與位於鰭片37、38、39、40的上部中的奈米片通道層12物理耦接。源/汲區44及源/汲區46通過內間隙壁42與犧牲層14物理隔離，且源/汲區44通過層32、34、36與基板20電性隔離。關聯鰭片38、39並由其共用的源/汲區44、46與關聯鰭片37、40並由其共用的源/汲區44、46橫向隔開。未共用的源/汲區44、46設置於鰭片38、39與鰭片37、39之間的空間的外部。
源/汲區44可通過外延生長製程形成，其中，半導體材料自生長晶種(seed)生長，該生長晶種由在鰭片37、38、39、40的相對側壁所暴露的奈米片通道層12的兩個側表面提供。在鰭片37與40之間的空間中，該外延生長的半導體材料合併以形成源/汲區44的其中一個。在鰭片38與39之間的空間中，該外延生長的半導體材料合併以形成源/汲區44的其中另一個。可用提供n型電性導電性的n型摻雜物(例如，磷及/或砷)在外延生長期間重摻雜構成源/汲區44的半導體材料。
在形成源/汲區44以後，在源/汲區44上方以及在圍繞鰭片37、38、39、40的空間中形成由介電材料例如二氧化矽組成的介電層48。在形成介電層48以後，可通過外延生長製程形成源/汲區46，其中，半導體材料自生長晶種生長，該生長晶種由在鰭片37、38、39的相對側壁及介電層48上方所暴露的最上奈米片通道層12的側表面提供。在鰭片37與40之間的空間中，該外延生 長的半導體材料合併以形成源/汲區46的其中一個。在鰭片38與39之間的空間中，該外延生長的半導體材料合併以形成源/汲區46的其中另一個。構成源/汲區46的該半導體材料可經重摻雜以具有與源/汲區44的電極性或導電性相反的電極性或導電性。在源/汲區44具有n型導電性的實施例中，可用提供p型電性導電性的p型摻雜物(例如，硼)在外延生長期間摻雜構成源/汲區46的半導體材料。
上方(upper)源/汲區46通過介電層48與具有相反導電類型半導體材料的下方(lower)源/汲區44物理隔開並電性隔離。位於鰭片38、39之間以及鰭片37、40之間的空間中的堆疊源/汲區44、46可用以形成互補場效電晶體。
請參照圖7、7A、7B，其中類似的附圖標記表示圖6、6A、6B中類似的特徵，且在該製程方法的下一製造階段，在犧牲閘極結構26、27，側間隙壁30，鰭片37、38、39、40，以及源/汲區44、46上方沉積層間介電層50，並利用化學機械拋光對其平坦化。該平坦化自犧牲閘極結構26、27移除介電覆蓋層25，並由此顯露位於該平坦化頂部表面的犧牲閘極結構26、27。
隨後相對奈米片通道層12、淺溝槽隔離區24、內間隙壁42、以及層間介電層50的材料選擇性地通過一個或多個蝕刻製程移除犧牲閘極結構26、27。犧牲閘極結構26、27的該移除暴露未被介電層36覆蓋的鰭片37、38、39、40的側壁處的犧牲層18的相應側表面。不過，在該流程的此點未移除犧牲層14。
請參照圖8、8A、8B，其中類似的附圖標記表示圖7、7A、7B中類似的特徵，且在該製程方法的下一製造階段，沉積介電層54，其厚度足以覆蓋由犧牲閘極結構26、27的該移除所導致的鰭片37、38、39、40的側壁處的犧 牲層18的該暴露側表面。介電層54可通過共形或定向沉積製程沉積，以使該介電材料不會沉積於鰭片37、38、39、40的側壁上。介電層54可由氮化矽組成，且介電層54具有足以與上方介電層34疊置的厚度。
側間隙壁56形成於介電層54的頂部表面上並鄰近各鰭片37、38、39、40的側壁設置。側間隙壁56可由低k介電材料例如SiC組成，其通過例如原子層沉積沉積並接著通過非等向性蝕刻製程例如反應離子蝕刻蝕刻。側間隙壁56覆蓋並掩蔽介電層54的下方部分。
請參照圖9、9A、9B，其中類似的附圖標記表示圖8、8A、8B中類似的特徵，且在該製程方法的下一製造階段，通過非等向性蝕刻製程例如反應離子蝕刻蝕刻介電層54，以形成側間隙壁58。側間隙壁56在該蝕刻製程期間提供覆蓋介電層54的下方部分的硬遮罩，且在該蝕刻製程之後，側間隙壁56直接設置於側間隙壁58上方。每對堆疊的側間隙壁56及側間隙壁58具有與最上介電層34橫向對齊的界面。介電層32、34、36與側間隙壁58配合以完全包覆並圍繞位於鰭片37、38、39、40下方的犧牲層18。
請參照圖10、10A、10B、10C，其中類似的附圖標記表示圖9、9A、9B中類似的特徵，且在該製程方法的下一製造階段，施加並圖案化蝕刻遮罩60，以覆蓋鰭片38。蝕刻遮罩60可包括旋塗硬遮罩(spin-on hardmask；SOH)，例如有機平坦化層(organic planarization layer；OPL)，其通過旋塗施加並通過光刻及蝕刻圖案化。通過蝕刻製程相對側間隙壁56及淺溝槽隔離區24選擇性地自鰭片37、39及40移除被蝕刻遮罩60暴露的側間隙壁58。側間隙壁58的該移除重新暴露設置於鰭片37、39及40下方的犧牲層18的側表面。設置於鰭片38下方的犧牲層18的側表面被蝕刻遮罩60掩蔽。
請參照圖11、11A、11B，其中類似的附圖標記表示圖10、10A、10B中類似的特徵，且在該製程方法的下一製造階段，通過例如用氧電漿(plasma)灰化來移除蝕刻遮罩60。位於鰭片37下方的犧牲層18，位於鰭片39下方的犧牲層18，以及位於鰭片40下方的犧牲層被轉換為介電材料，以形成相應介電層62。在一個實施例中，利用選擇性氧化製程可將位於鰭片37、39及40下方的犧牲層18轉換為包含矽及鍺的氧化物，該氧化製程不氧化暴露的最上奈米片通道層12。在一個實施例中，可通過使用氧電漿流的低溫電漿輔助氧化製程選擇性執行該氧化製程。在其它位置中(包括位於鰭片38下方)的犧牲層18被介電層32、34、36及側間隙壁58保護，且未被氧化。犧牲層14被側間隙壁56覆蓋，以防止氧化並保留犧牲層14以用於替代閘極製程中的後續移除。
請參照圖12、12A、12B、12C，其中類似的附圖標記表示圖11、11A、11B中類似的特徵，且在該製程方法的下一製造階段，通過一個或多個蝕刻製程自鰭片38移除側間隙壁56，並自鰭片37、39及40移除側間隙壁56及58。在淺溝槽隔離區24上方以及在鰭片37與鰭片38之間的空間中形成由介電材料例如氮化矽組成的介電柱68。在淺溝槽隔離區24上方以及在鰭片39與鰭片40之間的空間中形成類似的介電柱69。介電柱68、69隨後提供閘極切口(gate cut)。為形成介電柱68、69，可形成犧牲材料例如外延生長矽鍺的相鄰部分(該相鄰部分由在夾止之前終止形成所形成的縫隙隔開)，以及沉積介電材料例如氮化矽(其在該縫隙內部夾止)。在形成介電柱68、69以後，通過蝕刻製程選擇性移除該犧牲材料。
介電柱68位於鰭片37與鰭片38之間的空間中，且介電柱69位於鰭片39與鰭片40之間的空間中。介電柱68及69沿x-y平面內的方向(也就 是，x方向)對齊而橫向設置。介電柱68、69的該對齊被保留為在替代閘極製程之後與鰭片37、38、39、40關聯的後續形成的閘極結構的閘極電極之間的相應切口。介電柱68、69形成為相對於彼此沒有任何不對稱偏移或移位。
接著，通過蝕刻製程(例如氣相鹽酸或包括三氟化氯(ClF3)氣體的氣體化學蝕刻)相對奈米片通道層12、內間隙壁42、以及介電層62選擇性移除犧牲層14及犧牲層18的未氧化剩餘部分。還通過該蝕刻製程移除層15。犧牲層18的該移除生成腔體64，其橫向延伸於鰭片38下方以及源/汲區44、46下方。犧牲層14的該移除釋放關聯的奈米片通道層12並生成圍繞各鰭片37、38、39及40的奈米片通道層12的腔體66。介電層62中斷腔體66的連續性並防止腔體66直接形成於鰭片37、39及40下方，以使關聯鰭片37、39及40的腔體64與腔體66隔離。
請參照圖13、13A、13B，其中類似的附圖標記表示圖12、12A、12B中類似的特徵，且在該製程方法的下一製造階段，在通過犧牲層14的該移除而開放的腔體66中形成閘極結構70的部分。各閘極結構70可包括金屬閘極電極，由一種或多種介電材料(例如高k介電質如氧化鉿)組成的閘極介電層，以及位於奈米片通道層12的外表面上的薄氧化物層。該閘極介電層設置於該金屬閘極電極與位於奈米片通道層12的外表面上的該薄氧化物層之間。該金屬閘極電極包括一個或多個共形阻擋金屬層及/或功函數金屬層，例如由碳化鋁鈦(TiAlC)及/或氮化鈦(TiN)組成的層，以及由導體例如鎢(W)組成的金屬閘極填充層。在各閘極結構70上方形成由介電材料例如氮化矽組成的閘極覆蓋層71。閘極結構70的該閘極電極以閘極環繞(gate-all-around)佈置四周圍繞奈米片通道層12，且各鰭片37、38、39、40的奈米片通道層12定義主動通道，在操作期間， 載子流發生於該主動通道中。
閘極結構70的其中之一與鰭片37關聯，以定義通閘場效電晶體。閘極結構70的其中之一與鰭片38關聯，以定義具有上拉電晶體及下拉電晶體的互補場效電晶體，該上拉電晶體及下拉電晶體具有堆疊佈置的源/汲區44、46以及共用閘極結構70。埋置交叉耦接互連72在被此共用閘極結構70圍繞的奈米片通道層12所定義的主動通道下方與此共用閘極結構70耦接。閘極結構70的其中之一與鰭片39關聯，以定義另一個通閘場效電晶體。閘極結構70的其中之一與鰭片40關聯，以定義具有上拉電晶體及下拉電晶體兩者的另一個互補場效電晶體，該上拉電晶體及下拉電晶體具有堆疊佈置的源/汲區44、46以及共用閘極結構70。
介電柱68(圖12、12C)設置於關聯鰭片37的閘極結構70的閘極電極與關聯鰭片38的閘極結構70的閘極電極之間作為閘極切口。介電柱69(圖12C)設置於關聯鰭片39的閘極結構70的閘極電極與關聯鰭片40的閘極結構70的閘極電極之間作為閘極切口。
埋置交叉耦接互連72形成於腔體64中，並與關聯鰭片38的閘極結構70直接耦接。在一個實施例中，經順序沉積以形成閘極結構70的該閘極介電層的該介電材料及該閘極電極的該導體還沉積於腔體64中，以定義埋置交叉耦接互連72。介電層62防止埋置交叉耦接互連72與關聯鰭片37、39及40的閘極結構70連接，並由此將所有這些特定的閘極結構70與埋置交叉耦接互連72電性隔離。埋置交叉耦接互連72沿垂直方向設置於關聯鰭片38的閘極結構70下方，並且還沿該垂直方向設置於源/汲區44下方。介電層34防止埋置交叉耦接互連72與源/汲區44直接連接，並由此將特定的源/汲區44與埋置交叉 耦接互連72電性隔離。
請參照圖14、14A、14B、14C，其中類似的附圖標記表示圖13、13A、13B中類似的特徵，且在該製程方法的下一製造階段，通過光刻及蝕刻製程形成源/汲接觸的接觸開口76。接觸開口76沿垂直方向延伸，以暴露關聯鰭片37及40的源/汲區44的側表面43以及關聯鰭片37及40的源/汲區46的側表面45。接觸開口76的深度延伸至源/汲區44及介電層34的深度以下。因此，介電層36的一部分被接觸開口76暴露，以允許該一個或多個蝕刻製程移除位於接觸開口76內部的介電層36的此部分。介電層36的該部分移除暴露位於接觸開口76的基部處的埋置交叉耦接互連72的側表面73。通過蝕刻製程自埋置交叉耦接互連72的導體的側表面73移除該閘極介電材料。
通過光刻及蝕刻製程形成另一個源/汲接觸的接觸開口78。接觸開口78沿垂直方向延伸以暴露源/汲區46，並部分暴露關聯鰭片38及39的源/汲區44。接觸開口78比接觸開口76延伸較淺的深度，從而不移除介電層36。因此，不暴露埋置交叉耦接互連72的相對側表面。
請參照圖15、15A、15B，其中類似的附圖標記表示圖14、14A、14B中類似的特徵，且在該製程方法的下一製造階段，在接觸開口76、78中形成接觸82、84。接觸82、84可包括金屬矽化物，例如矽化鎢、矽化鈦、矽化鎳、或矽化鈷。覆蓋層85形成於接觸82、84上方，並可由介電材料例如碳化矽組成。
接觸82垂直延伸以包覆關聯鰭片38及39的源/汲區44、46並與其耦接。接觸84垂直延伸以包覆關聯鰭片37及40的源/汲區44、46的相應側表面43、45並與其耦接。由於接觸開口76的深度，接觸84與埋置交叉耦接互 連72的側表面73直接接觸，從而建立接觸84與埋置交叉耦接互連72之間的電性及物理連接。接觸84參與形成關聯鰭片38的閘極結構70的閘極電極與關聯鰭片37及40的源/汲區44、46之間的交叉耦接連接。該交叉耦接連接在不依賴中間工藝及後端工藝層級中的金屬化層的情況下建立。
在接觸82、84上方所形成的一個或多個層間介電層92中形成接觸86、88、90。可在一個或多個層間介電層92中通過光刻及蝕刻製程形成接觸86、88、90。接觸86將金屬線94與源/汲接觸82耦接，且接觸88將金屬線94與關聯鰭片40的閘極結構70的閘極電極耦接。接觸90與關聯鰭片39的閘極結構70耦接，並與接觸86接觸以提供電性連接。接觸82、86、88、90及金屬線94參與形成另一個交叉耦接連接。位於接觸82上方的覆蓋層85將接觸82與接觸88隔離。
請參照圖16，利用鰭片37、38、39、40所形成的裝置結構可被包括於SRAM記憶體裝置的六電晶體(6-T)靜態隨機存取記憶體(SRAM)位元單元96。SRAM位元單元96可屬更大陣列的SRAM位元單元，該些SRAM位元單元與SRAM位元單元96相同。源/汲區44位於沿垂直方向設置於包括源/汲區46的層下方的層中，介電層48介於該相鄰層之間。源/汲區46的其中之一堆疊於關聯鰭片38及40的源/汲區44的其中之一上方，以定義屬相應互補場效電晶體(complementary field-effect transistor；CFET)100、102的堆疊奈米片電晶體對(pair)。在各CFET 100、102中，下方源/汲區44有助於形成反相器的下方場效電晶體，且上方源/汲區46有助於形成反相器的上方奈米片場效電晶體，這些反相器在SRAM位元單元96中提供儲存。在一個實施例中，關聯CFET 100、102的下方源/汲區44的場效電晶體可被稱為SRAM位元單元96的下拉(pull-down； PD)電晶體，且關聯CFET 100、102的上方源/汲區46的場效電晶體可為SRAM位元單元96的上拉(pull-up；PU)電晶體。分別關聯鰭片37及39的場效電晶體104、106可構成SRAM位元單元96的存取或通閘電晶體，其控制讀取及寫入操作期間對該些反相器的存取。
位元線(bit line；BLT)與場效電晶體104的汲極連接，且互補位元線(complementary bit line；BLC)與場效電晶體106的汲極連接。場效電晶體104、106的閘極分別與字線(wordline；WL)連接。CFET 100、102的源/汲區46與正供應電壓(VDD)連接，且CFET 100、102的源/汲區44與負供應電壓(VSS)連接，其可為地。
在形成SRAM位元單元96的交叉耦接連接的其中之一的過程中使用埋置交叉耦接互連72可消除為提供該交叉耦接連接的其中之一而對源/汲區44、46的外延半導體材料進行複雜圖案化的需求。此外，不必移除通閘場效電晶體104、106的上方源/汲區46。埋置交叉耦接互連72的使用還致能無不對稱偏移的自對準閘極切口的形成，從而可增加SRAM位元單元96的可擴展性。埋置交叉耦接互連72的使用還可允許更緊湊的位元單元96的構造。
如上所述的方法用於積體電路晶片的製造中。製造者可以原始晶圓形式(例如，作為具有多個未封裝晶片的單個晶圓)、作為裸晶片，或者以封裝形式分配所得的積體電路晶片。可將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置整合，作為中間產品或最終產品的部分。該最終產品可為包括積體電路晶片的任意產品，例如具有中央處理器的電腦產品或智慧手機。
本文中引用的由近似語言例如“大約”、“大致”及“基本上”所修飾的術語不限於所指定的精確值。該近似語言可對應於用以測量該值的儀器的精 度，且除非依賴於該儀器的精度，否則可表示所述值的+/-10%。
本文中引用術語例如“垂直”、“水平”等作為示例來建立參考框架，並非限制。本文中所使用的術語“水平”被定義為與半導體基板的傳統平面平行的平面，而不論其實際的三維空間取向。術語“垂直”及“正交”是指垂直於如剛剛所定義的水平面的方向。術語“橫向”是指在該水平平面內的方向。
與另一個特徵“連接”或“耦接”的特徵可與該另一個特徵直接連接或耦接，或者可存在一個或多個中間特徵。如果不存在中間特徵，則特徵可與另一個特徵“直接連接”或“直接耦接”。如存在至少一個中間特徵，則特徵可與另一個特徵“非直接連接”或“非直接耦接”。在另一個特徵“上”或與其“接觸”的特徵可直接在該另一個特徵上與其直接接觸，或者可存在一個或多個中間特徵。如果不存在中間特徵，則特徵可直接在另一個特徵“上”或與其“直接接觸”。如存在至少一個中間特徵，則特徵可“不直接”在另一個特徵“上”或與其“不直接接觸”。
對本發明的各種實施例所作的說明是出於示例目的，而非意圖詳盡無遺或限於所揭示的實施例。許多修改及變更對於本領域的普通技術人員將顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使本領域的普通技術人員能夠理解本文中所揭示的實施例。
12:奈米片通道層
15:薄層
20:基板
30:側間隙壁
32,34,48,62:介電層
38,39:鰭片
42:內間隙壁
44,46:源/汲區
50,92:層間介電層
70:閘極結構
71:閘極覆蓋層
72:埋置交叉耦接互連
82,86,90:接觸

Claims (20)

  1. 一種結構，包括：
    第一場效電晶體，包括閘極電極；
    第二場效電晶體，包括第一源/汲區；以及
    埋置交叉耦接互連，沿垂直方向設置於該第一場效電晶體及該第二場效電晶體下方，該埋置交叉耦接互連與該第一場效電晶體的該閘極電極耦接，且該埋置交叉耦接互連與該第二場效電晶體的該第一源/汲區耦接。
  2. 如請求項1所述的結構，其中，該第二場效電晶體包括沿該垂直方向堆疊於該第一源/汲區上方的第二源/汲區，該第一源/汲區由第一半導體材料組成，且該第二源/汲區由具有與該第一半導體材料相反的導電類型的第二半導體材料組成。
  3. 如請求項2所述的結構，其中，該埋置交叉耦接互連進一步與該第二場效電晶體的該第二源/汲區耦接。
  4. 如請求項3所述的結構，進一步包括：
    介電層，位於該第一場效電晶體及該第二場效電晶體上方；以及
    位於該介電層中的接觸，該接觸沿該垂直方向延伸以將該埋置交叉耦接互連與該第二場效電晶體的該第二源/汲區耦接。
  5. 如請求項4所述的結構，其中，該第一源/汲區具有第一側表面，該第二源/汲區具有第二側表面，該埋置交叉耦接互連具有第三側表面，且該接觸與該第一側表面、該第二側表面、以及該第三側表面直接耦接。
  6. 如請求項2所述的結構，其中，該第二場效電晶體包括奈米片通道層，且該奈米片通道層被該閘極電極的一部分圍繞。
  7. 如請求項1所述的結構，其中，該第二場效電晶體包括閘極電極，且進一步包括：
    第一介電層，設置於腔體的第一部分中，
    其中，該腔體的該第一部分設置於該第二場效電晶體的該閘極電極下方。
  8. 如請求項7所述的結構，其中，該埋置交叉耦接互連設置於該腔體的第二部分中，該腔體的該第二部分設置於該第一場效電晶體的該閘極電極下方。
  9. 如請求項8所述的結構，進一步包括：
    第二介電層，沿該垂直方向設置於該腔體與基板之間。
  10. 如請求項1所述的結構，其中，該第一源/汲區具有側表面，該埋置交叉耦接互連具有側表面，且進一步包括：
    沿該垂直方向延伸的接觸，
    其中，該接觸與該埋置交叉耦接互連的該側表面以及該第一源/汲區的該側表面耦接。
  11. 如請求項1所述的結構，其中，該第一場效電晶體是靜態隨機存取記憶體位元單元的第一反相器的組件，且該第二場效電晶體是該靜態隨機存取記憶體位元單元的第二反相器的組件。
  12. 如請求項1所述的結構，其中，該第二場效電晶體包括閘極電極，且進一步包括：
    第三場效電晶體，包括與該第一場效電晶體的該閘極電極對齊的閘極電極；
    第四場效電晶體，包括與該第二場效電晶體的該閘極電極對齊的閘極電極；
    第一介電柱，作為第一切口設置於該第一場效電晶體的該閘極電極與該第 三場效電晶體的該閘極電極之間；以及
    第二介電柱，作為第二切口設置於該第二場效電晶體的該閘極電極與該第四場效電晶體的該閘極電極之間；
    其中，該第一介電柱與該第二介電柱橫向對齊。
  13. 如請求項1所述的結構，其中，該第一場效電晶體包括主動通道，且該埋置交叉耦接互連部分設置於該第一場效電晶體的該主動通道下方。
  14. 如請求項13所述的結構，其中，該第一場效電晶體的該主動通道包括一個或多個奈米片通道層，且該第一場效電晶體的該閘極電極經設置以圍繞各奈米片通道層。
  15. 一種方法，包括：
    形成第一犧牲層、第二犧牲層，以及位於該第一犧牲層與該第二犧牲層之間的第三犧牲層；
    用介電材料替代該第一犧牲層及該第二犧牲層，以分別形成第一介電層及第二介電層；
    在用該介電材料替代該第一犧牲層及該第二犧牲層以後，用導體替代該第三犧牲層，以形成與第一場效電晶體的閘極電極耦接的埋置交叉耦接互連；
    在該第二介電層上方形成第二場效電晶體的源/汲區；以及
    形成將該埋置交叉耦接互連與該第二場效電晶體的該源/汲區耦接的接觸。
  16. 如請求項15所述的方法，其中，用該導體替代該第三犧牲層以形成與該第一場效電晶體的該閘極電極耦接的該埋置交叉耦接互連包括：
    通過蝕刻製程相對該第一介電層及該第二介電層選擇性移除該第三犧牲層，以定義腔體；以及
    沉積該導體，該導體形成該閘極電極且該導體通過填充該腔體同時形成該埋置交叉耦接互連。
  17. 如請求項15所述的方法，其中，用該介電材料替代該第一犧牲層及該第二犧牲層以分別形成該第一介電層及該第二介電層包括：
    通過蝕刻製程相對該第三犧牲層選擇性移除該第一犧牲層及該第二犧牲層，以分別定義第一腔體及第二腔體；以及
    共形沉積該介電材料以填充該第一腔體，並填充該第二腔體，以及覆蓋該埋置交叉耦接互連的側表面。
  18. 如請求項17所述的方法，其中，該第一犧牲層及該第二犧牲層包括具有第一原子百分比的鍺的矽-鍺，且該第三犧牲層包括具有第二原子百分比的鍺的矽-鍺，該第二原子百分比的鍺大於該第一原子百分比的鍺，以提供該蝕刻製程的選擇性。
  19. 如請求項15所述的方法，其中，該第二場效電晶體包括鰭片，其具有與該源/汲區耦接並設置於該第一介電層上方的奈米片通道層，且進一步包括：
    形成經設置以覆蓋該奈米片通道層的側表面的第一側間隙壁；以及
    形成經設置以覆蓋該第三犧牲層的側表面的第二側間隙壁，
    其中，該第一側間隙壁堆疊於該第二側間隙壁上方，該第一側間隙壁由第一介電材料組成，且該第二側間隙壁由不同於該第一介電材料的第二介電材料組成。
  20. 如請求項19所述的方法，進一步包括：
    相對該第一側間隙壁選擇性移除該第二側間隙壁，以顯露該第三犧牲層；以 及
    在移除該第二側間隙壁以後，氧化該第三犧牲層的一部分。
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