TW202107670A - 具有支石墓結構的半導體裝置及其製造方法以及支持片形成用積層膜及其製造方法 - Google Patents

具有支石墓結構的半導體裝置及其製造方法以及支持片形成用積層膜及其製造方法 Download PDF

Info

Publication number
TW202107670A
TW202107670A TW109113932A TW109113932A TW202107670A TW 202107670 A TW202107670 A TW 202107670A TW 109113932 A TW109113932 A TW 109113932A TW 109113932 A TW109113932 A TW 109113932A TW 202107670 A TW202107670 A TW 202107670A
Authority
TW
Taiwan
Prior art keywords
wafer
film
forming
support sheet
resin layer
Prior art date
Application number
TW109113932A
Other languages
English (en)
Inventor
矢羽田達也
谷口紘平
橋本慎太郎
尾崎義信
Original Assignee
日商日立化成股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商日立化成股份有限公司 filed Critical 日商日立化成股份有限公司
Publication of TW202107670A publication Critical patent/TW202107670A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)
  • Adhesive Tapes (AREA)

Abstract

本揭示的半導體裝置具有支石墓結構，所述支石墓結構包括：基板；第一晶片，配置於基板上；多個支持片，配置於基板上且為第一晶片的周圍；以及第二晶片，由多個支持片支持且配置成覆蓋第一晶片，且支持片由熱硬化性樹脂組成物的硬化物構成、或者包括由熱硬化性樹脂組成物的硬化物構成的層、以及樹脂層或金屬層。

Description

具有支石墓結構的半導體裝置及其製造方法以及支持片形成用積層膜及其製造方法
本揭示是有關於一種具有支石墓結構的半導體裝置，所述支石墓結構包括：基板；第一晶片，配置在基板上；多個支持片，配置於基板上且為第一晶片周圍；以及第二晶片，由多個支持片支持並且配置成覆蓋第一晶片。另外，本揭示是有關於一種具有支石墓結構的半導體裝置的製造方法以及支持片形成用積層膜及其製造方法。再者，支石墓（dolmen）是石墓的一種，具備多個支柱石及載置在其上的板狀的岩石。在具有支石墓結構的半導體裝置中，支持片相當於「支柱石」，第二晶片相當於「板狀的岩石」。
近年來，在半導體裝置的領域，要求高積體、小型化以及高速化。作為半導體裝置的一形態，在配置於基板上的控制器晶片上積層半導體晶片的結構受到關注。例如專利文獻1揭示了一種半導體晶粒組件，該半導體晶粒組件包括控制器晶粒、以及在控制器晶粒上由支持構件支持的記憶體晶粒。專利文獻1的圖1A所示的半導體組件100可謂是具有支石墓結構。即，半導體組件100包括封裝基板102、配置在封裝基板102表面上的控制器晶粒103、配置在控制器晶粒103上方的記憶體晶粒106a、記憶體晶粒106b、以及支持記憶體晶粒106a的支持構件130a、支持構件130b。 [現有技術文獻] [專利文獻]
[專利文獻1]日本專利特表2017-515306號公報
[發明所欲解決之課題] 專利文獻1揭示了作為支持構件（支持片），能夠使用矽等半導體材料，更具體而言，能夠使用切割半導體晶圓而得到的半導體材料的斷片（參照專利文獻1的[0012]、[0014]及圖2）。為了使用半導體晶圓製造支石墓結構用的支持片，與普通的半導體晶片的製造同樣，例如需要以下的各步驟。 （1）在半導體晶圓上貼附背面研磨帶（back grind tape）的步驟； （2）背面研磨半導體晶圓的步驟； （3）對切割環與配置在其中的背面研磨後的半導體晶圓貼附具有黏著層及接著劑層的膜（切割-黏晶一體型膜）的步驟； （4）自半導體晶圓剝離背面研磨帶的步驟； （5）將半導體晶圓單片化的步驟； （6）自黏著層拾取包含半導體晶片與接著劑片的積層體的支持片的步驟； （7）將多個支持片壓接在基板的規定位置的步驟。
本揭示提供一種半導體裝置的製造方法，在具有支石墓結構的半導體裝置的製造製程中，能夠簡化製作支持片的步驟。另外，本揭示提供一種具有支石墓結構的半導體裝置、以及支持片形成用積層膜及其製造方法。 [解決課題之手段]
本揭示的一個方面是有關於一種具有支石墓結構的半導體裝置的製造方法。所述製造方法包括以下的步驟。 （A）準備依次具備基材膜、黏著層、及支持片形成用膜的積層膜的步驟； （B）藉由將支持片形成用膜單片化，而在黏著層的表面上形成多個支持片的步驟； （C）自黏著層拾取支持片的步驟； （D）在基板上配置第一晶片的步驟； （E）在基板上且為第一晶片的周圍或應配置第一晶片的區域的周圍，配置多個支持片的步驟； （F）準備帶接著劑片的晶片的步驟，所述帶接著劑片的晶片具備第二晶片、及設置在第二晶片的一個面上的接著劑片； （G）藉由在多個支持片的表面上配置帶接著劑片的晶片來構築支石墓結構的步驟。 所述支持片形成用膜為以下的膜的任一種。 ·由熱硬化性樹脂層構成的膜； ·由使熱硬性樹脂層中至少一部分硬化而成的層構成的膜 ·包括熱硬化性樹脂層、以及較該熱硬化性樹脂層具有更高剛性的樹脂層的多層膜； ·包括熱硬化性樹脂層、以及較該熱硬化性樹脂層具有更高剛性的金屬層的多層膜。 （D）步驟及（E）步驟可先實施任一項。在先實施（D）步驟的情況下，在（E）步驟中，只要在基板上且為第一晶片的周圍配置多個支持片即可。另一方面，在先實施（E）步驟的情況下，在（E）步驟中，在基板上且為應配置第一晶片的區域的周圍配置多個支持片，然後，在（D）步驟中，在該區域配置第一晶片即可。再者，上述熱硬化性樹脂層的熱硬化後的剛性可低於樹脂層或金屬層的剛性，亦可高於樹脂層或金屬層的剛性。剛性是指物體對彎曲或扭曲能夠承受破壞的能力。
在本揭示的所述製造方法中，使用將支持片形成用膜單片化而獲得的支持片。藉此，與使用切割半導體晶圓而得到的半導體材料的斷片作為支持片的先前的製造方法相比，能夠簡化製作支持片的步驟。即，先前需要上述（1）～（7）的步驟，與此相對，支持片形成用膜不包含半導體晶圓，故能夠省略與半導體晶圓的背面研磨相關的（1）、（2）及（4）的步驟。另外，由於不使用較樹脂材料昂貴的半導體晶圓，故亦能夠削減成本。再者，由於熱硬化性樹脂層相對於其他構件（例如基板）具有接著性，因此可不在支持片上另外設置接著劑層等。
（A）步驟中準備的積層膜的黏著層可為感壓型亦可為紫外線硬化型。即，黏著層可藉由紫外線照射而硬化，亦可不藉由紫外線照射而硬化，換言之，可含有具有光反應性的具有碳-碳雙鍵的樹脂，亦可不含有。再者，感壓型的黏著層亦可含有具有光反應性的具有碳-碳雙鍵的樹脂。例如，黏著層可藉由對其規定區域照射紫外線而降低該區域的黏著性，例如，可殘存具有光反應性的具有碳-碳雙鍵的樹脂。黏著層為紫外線硬化型的情況下，可藉由在（B）步驟與（C）步驟之間，實施對黏著層照射紫外線的步驟，降低黏著層的黏著性。
支持片形成用膜包含熱硬化性樹脂層。加熱支持片形成用膜或支持片使熱硬化性樹脂層或接著劑片硬化的步驟在適當的時機實施即可，例如在（G）步驟之前實施即可。在以與多個支持片的表面接觸的方式配置帶接著劑片的晶片的階段，熱硬化性樹脂層已經硬化，藉此能夠抑制支持片隨著帶接著劑片的晶片的配置而變形。
本揭示的一個方面是有關於一種具有支石墓結構的半導體裝置。即，所述半導體裝置具有支石墓結構，所述支石墓結構包括：基板；第一晶片，配置於基板上；多個支持片，配置於基板上且為第一晶片的周圍；以及第二晶片，由多個支持片支持且配置成覆蓋第一晶片，且支持片由熱硬化性樹脂組成物的硬化物構成、或者包括由熱硬化性樹脂組成物的硬化物構成的層、以及樹脂層或金屬層。第一晶片可與第二晶片分離。
本揭示的所述半導體裝置可更包括接著劑片，所述接著劑片設置在第二晶片的一個面上並且被第二晶片與多個支持片夾持。此種情況下，所述第一晶片可與接著劑片分離，亦可與接著劑片接觸。接著劑片例如以至少覆蓋第二晶片中的與第一晶片相對的區域的方式設置。接著劑片可自第二晶片的所述區域連續地延伸至第二晶片的周緣側，並且被第二晶片與多個支持片夾持。即，一個接著劑片可覆蓋第二晶片的上述區域且將第二晶片與多個支持片接著。
本揭示的一個方面是有關於一種支持片形成用積層膜。所述積層膜依次具備基材膜、黏著層、及支持片形成用膜，且支持片形成用膜為由熱硬化性樹脂層構成的膜、或為由使熱硬化性樹脂層中的至少一部分硬化而成的層構成的膜、或者為包括熱硬化性樹脂層、以及較所述熱硬化性樹脂層具有更高剛性的樹脂層或金屬層的多層膜。
所述支持片形成用膜的厚度例如為5 μm～180 μm。藉由使支持片形成用膜的厚度在該範圍內，能夠構築相對於第一晶片（例如，控制器晶片）而為適當高度的支石墓結構。支持片形成用膜中的熱硬化性樹脂層例如含有環氧樹脂。熱硬化性樹脂層較佳為含有彈性體。藉由構成支持片的熱硬化性樹脂層含有彈性體，能夠緩和半導體裝置內的應力。
支持片形成用膜所具有的樹脂層例如為聚醯亞胺層。支持片形成用膜所具有的金屬層例如為銅層或鋁層。
本揭示的一個方面是有關於一種支持片形成用積層膜的製造方法。所述製造方法包括：準備黏著膜的步驟，所述黏著膜具有基材膜、及形成在所述基材膜的一個面上的黏著層；以及在黏著層的表面上積層支持片形成用膜的步驟，且支持片形成用膜為由熱硬化性樹脂層構成的膜、或為由使熱硬化性樹脂層中的至少一部分硬化而成的層構成的膜、或者為包括熱硬化性樹脂層、以及較所述熱硬化性樹脂層具有更高剛性的樹脂層或金屬層的多層膜。
具有樹脂層或金屬層的支持片形成用積層膜例如可如以下般製造。即，該支持片形成用積層膜的製造方法包括：準備依次具備基材膜、黏著層、熱硬化性樹脂層的積層膜的步驟；以及在熱硬化性樹脂層的表面貼合較該熱硬化性樹脂層具有更高剛性的樹脂層或金屬層的步驟。 [發明的效果]
根據本揭示，提供一種半導體裝置的製造方法，在具有支石墓結構的半導體裝置的製造製程中，能夠簡化製作支持片的步驟。另外，根據本揭示，提供一種具有支石墓結構的半導體裝置、以及支持片形成用積層膜及其製造方法。
以下，參照圖式對本揭示的實施方式進行詳細說明。其中，本發明不限定於以下的實施方式。再者，本說明書中，所謂「(甲基)丙烯酸」是指丙烯酸或甲基丙烯酸，所謂「(甲基)丙烯酸酯」是指丙烯酸酯或與其對應的甲基丙烯酸酯。所謂「A或B」，只要包含A與B的任一者即可，亦可兩者均包含。
於本說明書中，用語「層」於以平面圖的形式進行觀察時，除了於整個面形成的形狀的結構以外，亦包含部分地形成的形狀的結構。另外，於本說明書中，「步驟」這一用語不僅是指獨立的步驟，即便在無法與其他步驟明確地加以區分的情況下，只要達成該步驟的預期的作用，則亦包含於本用語中。另外，使用「～」所表示的數值範圍表示包含「～」的前後所記載的數值分別作為最小值及最大值的範圍。
於本說明書中，關於組成物中的各成分的含量，於在組成物中存在多種相當於各成分的物質的情況下，只要無特別說明，則是指組成物中存在的所述多種物質的合計量。另外，例示材料只要無特別說明，則可單獨使用，亦可組合使用二種以上。另外，本說明書中階段性地記載的數值範圍中，某階段的數值範圍的上限值或下限值亦可替換為其他階段的數值範圍的上限值或下限值。另外，本說明書中所記載的數值範圍中，該數值範圍的上限值或下限值可替換為實施例中所示的值。
＜第一實施方式＞ （半導體裝置） 圖1是示意性地表示本實施方式的半導體裝置的剖面圖。該圖所示的半導體裝置100包括：基板10、配置在基板10的表面上的晶片T1（第一晶片）、配置於基板10的表面上且為晶片T1的周圍的多個支持片Dc、配置於晶片T1的上方的晶片T2（第二晶片）、由晶片T2與多個支持片Dc夾持的接著劑片Tc、積層在晶片T2上的晶片T3、晶片T4、將基板10的表面上的電極（未圖示）與晶片T1～晶片T4分別電連接的多個導線w；以及填充在晶片T1與晶片T2之間的間隙等中的密封材50。
在本實施方式中，藉由多個支持片Dc、晶片T2、以及位於支持片Dc與晶片T2之間的接著劑片Tc而在基板10上構成支石墓結構。晶片T1與接著劑片Tc分離。藉由適當設定支持片Dc的厚度，能夠確保用於連接晶片T1的上表面與基板10的導線w的空間。藉由使晶片T1與接著劑片Tc分離，能夠防止與晶片T1連接的導線w的上部接觸晶片T2所導致的導線w的短路。另外，由於無需將導線埋入與晶片T2接觸的接著劑片Tc，故具有能夠減薄接著劑片Tc的優點。
如圖1所示，晶片T1與晶片T2之間的接著劑片Tc覆蓋晶片T2中的與晶片T1相對的區域R，並且自區域R連續地延伸至晶片T2的周緣側。即，一個接著劑片Tc覆蓋晶片T2的區域R，並夾設在晶片T2與多個支持片之間而將該些接著。再者，圖1中示出了接著劑片Tc設置成覆蓋晶片T2的一個面（下表面）的整體的形態。然而，由於接著劑片Tc在半導體裝置100的製造過程中可能收縮，因此只要實質上覆蓋晶片T2的一個面（下表面）的整體即可，例如，於晶片T2的周緣的一部分亦可存在未被接著劑片Tc覆蓋的部位。圖1中的晶片T2的下表面相當於晶片的背面。近年來晶片的背面多形成有凹凸。藉由晶片T2背面的實質上的整體被接著劑片Tc覆蓋，能夠抑制晶片T2產生裂縫或破裂。
基板10可以是有機基板，亦可以是引線框架等金屬基板。基板10中，自抑制半導體裝置100的翹曲的觀點來看，基板10的厚度例如為90 μm～300 μm，亦可為90 μm～210 μm。
晶片T1例如是控制器晶片，藉由接著劑片T1c接著於基板10且藉由導線w與基板10電連接。俯視下的晶片T1的形狀例如為矩形（正方形或長方形）。晶片T1的一邊的長度例如為5 mm以下，亦可為2 mm～5 mm或1 mm～5 mm。晶片T1的厚度例如為10 μm～150 μm，亦可為20 μm～100 μm。
晶片T2例如是記憶體晶片，並經由接著劑片Tc而接著在支持片Dc上。俯視時，晶片T2具有大於晶片T1的尺寸。俯視下的晶片T2的形狀例如為矩形（正方形或長方形）。晶片T2的一邊的長度例如為20 mm以下，亦可為4 mm～20 mm或4 mm～12 mm。晶片T2的厚度例如是10 μm～170 μm，亦可為20 μm～120 μm。再者，晶片T3、晶片T4亦例如是記憶體晶片，經由接著劑片Tc接著在晶片T2上。晶片T3、晶片T4的一邊的長度只要與晶片T2相同即可，晶片T3、晶片T4的厚度亦與晶片T2相同即可。
支持片Dc發揮在晶片T1的周圍形成空間的間隔物的作用。支持片Dc由熱硬化性樹脂組成物的硬化物構成。再者，如圖2的（a）所示，可在晶片T1的兩側的隔開的位置配置兩個支持片Dc（形狀：長方形），亦可如圖2的（b）所示，在與晶片T1的角部對應的位置分別配置一個支持片Dc（形狀：正方形，共計4個）。俯視下的支持片Dc的一邊的長度例如為20 mm以下，亦可為1 mm～20 mm或1 mm～12 mm。支持片Dc的厚度（高度）例如為10 μm～180 μm，亦可為20 μm～120 μm。
（支持片的製造方法） 對支持片的製造方法的一例進行說明。再者，圖1所示的支持片Dc是熱硬化性樹脂組成物硬化後的支持片。另一方面，支持片Da是熱硬化性樹脂組成物完全硬化之前的狀態的支持片（例如，參照圖5的（b））。
首先，準備圖3的（a）及圖3的（b）所示的支持片形成用積層膜20（以下，視情況稱為「積層膜20」）。積層膜20具備基材膜1、黏著層2、及支持片形成用膜D。基材膜1例如為聚對苯二甲酸乙二酯膜（PET（polyethylene terephthalate）膜）。黏著層2藉由沖孔等形成為圓形（參照圖3的（a））。黏著層2由紫外線硬化型的黏著劑構成。即，黏著層2具有藉由照射紫外線而黏著性降低的性質。支持片形成用膜D藉由沖孔等形成為圓形，具有較黏著層2小的直徑（參照圖3的（a））。支持片形成用膜D由熱硬化性樹脂組成物構成。
構成支持片形成用膜D的熱硬化性樹脂組成物經過半硬化（B階段）狀態，藉由之後的硬化處理能夠成為完全硬化物（C階段）狀態。熱硬化性樹脂組成物含有環氧樹脂、硬化劑、彈性體（例如丙烯酸樹脂），並根據需要進一步含有無機填料及硬化促進劑等。對於構成支持片形成用膜D的熱硬化性樹脂組成物的詳細情況將在後面敘述。
積層膜20例如可藉由將第一積層膜與第二積層膜貼合來製造，所述第一積層膜具有基材膜1且在基材膜1的表面上具有黏著層2，所述第二積層膜具有覆蓋膜3且在覆蓋膜3的表面上具有支持片形成用膜D（參照圖4）。第一積層膜可經過如下步驟而獲得：在基材膜1的表面上藉由塗佈而形成黏著層的步驟、以及藉由沖孔等將黏著層加工成規定形狀（例如圓形）的步驟。第二積層膜可經過如下步驟而獲得：在覆蓋膜3（例如PET膜或聚乙烯膜）的表面上藉由塗佈而形成支持片形成用膜的步驟、及藉由沖孔等將支持片形成用膜加工成規定的形狀（例如、圓形）的步驟。當使用積層膜20時，覆蓋膜3在適當的時機被剝離。
如圖5的（a）所示，將切割環DR貼附於積層膜20。即，將切割環DR貼附於積層膜20的黏著層2，成為在切割環DR的內側配置有支持片形成用膜D的狀態。藉由切割將支持片形成用膜D單片化（參照圖5的（b））。藉此，可自支持片形成用膜D獲得多個支持片Da。其後，藉由對黏著層2照射紫外線，使黏著層2與支持片Da之間的黏著力下降。紫外線照射後，如圖5的（c）所示，藉由擴展基材膜1，使支持片Da相互分離。如圖5的（d）所示，藉由用上推夾具42上推支持片Da，自黏著層2剝離支持片Da，並且用抽吸夾頭44進行抽吸來拾取支持片Da。再者，亦可藉由對切割前的支持片形成用膜D或拾取前的支持片Da進行加熱，使熱硬化性樹脂的硬化反應進行。在拾取時藉由支持片Da適度地硬化而能夠實現優異的拾取性。較佳為將用於單片化的切口形成至支持片形成用膜D的外緣。支持片形成用膜D的直徑例如可為300 mm～310 mm或300 mm～305 mm。支持片形成用膜D的俯視下的形狀不限於圖3的（a）所示的圓形，亦可為矩形（正方形或長方形）。
（半導體裝置的製造方法） 對半導體裝置100的製造方法進行說明。本實施方式的製造方法包括以下的（A）～（H）的步驟。 （A）準備積層膜20的步驟（參照圖4）； （B）藉由將支持片形成用膜D單片化，在黏著層2的表面上形成多個支持片Da的步驟（參照圖5的（b））； （C）自黏著層2拾取支持片Da的步驟（參照圖5的（d））； （D）在基板10上配置第一晶片T1的步驟； （E）在基板10上且為第一晶片T1的周圍配置多個支持片Da的步驟（參照圖6）； （F）準備帶接著劑片的晶片T2a的步驟，所述帶接著劑片的晶片T2a具備第二晶片T2、及設置在第二晶片T2的一個面上的接著劑片Ta（參照圖7）； （G）藉由在多個支持片Dc的表面上配置帶接著劑片的晶片T2a來構築支石墓結構的步驟（參照圖8）； （H）用密封材50密封晶片T1與晶片T2之間的間隙等的步驟（參照圖1）。
（A）步驟～（C）步驟是製作多個支持片Da的製程，已經說明完畢。（D）步驟～（H）步驟是使用多個支持片Da在基板10上構築支石墓結構的製程。以下，參照圖6～圖8對（D）步驟～（H）步驟進行說明。
[（D）步驟] （D）步驟是在基板10上配置第一晶片T1的步驟。例如，首先，經由接著劑層T1c將晶片T1配置在基板10上的規定位置。然後，晶片T1藉由導線w與基板10電連接。（D）步驟可為在（E）步驟之前進行的步驟，亦可在（A）步驟之前、（A）步驟與（B）步驟之間、（B）步驟與（C）步驟之間、或者（C）步驟與（E）步驟之間。
[（E）步驟] （E）步驟是在基板10上且為第一晶片T1的周圍配置多個支持片Da的步驟。經過所述步驟製作圖6所示的結構體30。結構體30包括基板10、配置在基板10的表面上的晶片T1、及多個支持片Da。支持片Da的配置藉由壓接處理進行即可。壓接處理例如較佳為在80℃～180℃、0.01 MPa～0.50 Mpa的條件下實施0.5秒～3.0秒。再者，支持片Da可在（E）步驟的時刻完全硬化而成為支持片Dc，亦可不在該時刻完全硬化。較佳為支持片Da在（G）步驟開始前的時刻完全硬化而成為支持片Dc。
[（F）步驟] （F）步驟是準備圖7所示的帶接著劑片的晶片T2a的步驟。帶接著劑片的晶片T2a包括晶片T2、及設置在晶片T2的一個表面的接著劑片Ta。帶接著劑片的晶片T2a例如能夠使用半導體晶圓及切割-黏晶一體型膜，經過切割步驟及拾取步驟而獲得。
[（G）步驟] （G）步驟是以接著劑片Ta與多個支持片Dc的上表面接觸的方式，在晶片T1的上方配置帶接著劑片的晶片T2a的步驟。具體而言，經由接著劑片Ta將晶片T2壓接於支持片Dc的上表面。該壓接處理例如較佳為在80℃～180℃、0.01 MPa～0.50 MPa的條件下實施0.5秒～3.0秒。繼而，藉由加熱使接著劑片Ta硬化。該硬化處理例如較佳為在60℃～175℃、0.01 MPa～1.0 MPa的條件下實施5分鐘以上。藉此，接著劑片Ta硬化而成為接著劑片Tc。經過該步驟，在基板10上構築支石墓結構（參照圖8）。藉由使晶片T1與帶接著劑片的晶片T2a分離，能夠防止因導線w的上部與晶片T2接觸而引起的導線w的短路。另外，由於無需在與晶片T2接觸的接著劑片Ta中埋入導線，故具有能夠使接著劑片Ta變薄的優點。
在（G）步驟後、（H）步驟前，經由接著劑片在晶片T2上配置晶片T3，進而，經由接著劑片在晶片T3上配置晶片T4。接著劑片只要是與上述接著劑片Ta同樣的熱硬化性樹脂組成物即可，藉由加熱硬化而成為接著劑片Tc（參照圖1）。另一方面，藉由導線w分別將晶片T2、晶片T3、晶片T4與基板10電連接。再者，積層在晶片T1上方的晶片的數量不限於本實施方式中的三個，適當設定即可。
[（H）步驟] （H）步驟是用密封材50將晶片T1與晶片T2之間的間隙等密封的步驟。經過該步驟，完成圖1所示的半導體裝置100。
（構成支持片形成用膜的熱硬化性樹脂組成物） 如上所述，構成支持片形成用膜D的熱硬化性樹脂組成物含有環氧樹脂、硬化劑及彈性體，根據需要更含有無機填料及硬化促進劑等。根據本發明者等人的研究，較佳為支持片Da及硬化後的支持片Dc具有以下特性。 ·特性1：在基板10的規定位置熱壓接支持片Da時不易產生位置偏移（120℃下的支持片Da的熔融黏度例如為4300 Pa·s～50000 Pa·s或5000 Pa·s～40000 Pa·s）； ·特性2：在半導體裝置100內支持片Dc發揮應力緩和性（熱硬化性樹脂組成物含有彈性體（橡膠成分））； ·特性3：與帶接著劑片的晶片的接著劑片Tc的接著強度充分高（支持片Dc相對於接著劑片Tc的晶粒剪切（dieshear）強度例如為2.0 Mpa～7.0 Mpa或3.0 Mpa～6.0 Mpa）； ·特性4：伴隨硬化的收縮率充分小； ·特性5：在拾取步驟中基於照相機的支持片Da的視認性良好（熱硬化性樹脂組成物例如含有著色劑）； ·特性6：支持片Dc具有充分的機械強度。
[環氧樹脂] 環氧樹脂若為進行硬化而具有接著作用者，則並無特別限定。可使用：雙酚A型環氧樹脂、雙酚F型環氧樹脂、雙酚S型環氧樹脂等二官能環氧樹脂；苯酚酚醛清漆型環氧樹脂、甲酚酚醛清漆型環氧樹脂等酚醛清漆型環氧樹脂等。另外，可應用多官能環氧樹脂、縮水甘油胺型環氧樹脂、含雜環的環氧樹脂或脂環式環氧樹脂等普遍已知的樹脂。該些可單獨使用一種，亦可併用兩種以上。
[硬化劑] 作為硬化劑，例如可列舉酚樹脂、酯化合物、芳香族胺、脂肪族胺及酸酐。其中，自實現高的晶粒剪切強度的觀點而言，較佳為酚樹脂。作為酚樹脂的市售品，例如可列舉：迪愛生（DIC）（股）製造的LF-4871（商品名，BPA酚醛清漆型酚樹脂）、愛沃特（AIR WATER）（股）製造的HE-100C-30（商品名，苯基芳烷基型酚樹脂）、迪愛生（DIC）（股）製造的菲諾萊特（Phenolite）KA及TD系列、三井化學（股）製造的美萊克（Milex）XLC-系列及XL系列（例如美萊克（Milex）XLC-LL）、愛沃特（AIR WATER）（股）製造的HE系列（例如HE100C-30）、明和化成（股）製造的MEHC-7800系列（例如MEHC-7800-4S）、JEF化學（JFE Chemical）（股）的JDPP系列。該些可單獨使用一種，亦可併用兩種以上。
關於環氧樹脂與酚樹脂的調配量，自實現高的晶粒剪切強度的觀點而言，環氧當量與羥基當量的當量比分別較佳為0.6～1.5，更佳為0.7～1.4，進而佳為0.8～1.3。藉由使調配比在上述範圍內，容易將硬化性及流動性雙方達到充分高的水準。
[彈性體] 作為彈性體，例如可列舉：丙烯酸樹脂、聚酯樹脂、聚醯胺樹脂、聚醯亞胺樹脂、矽酮樹脂、聚丁二烯、丙烯腈、環氧改質聚丁二烯、順丁烯二酸酐改質聚丁二烯、酚改質聚丁二烯及羧基改質丙烯腈。
自實現高的晶粒剪切強度的觀點而言，作為彈性體較佳為丙烯酸系樹脂，進而，更佳為將丙烯酸縮水甘油酯或甲基丙烯酸縮水甘油酯等具有環氧基或縮水甘油基作為交聯性官能基的官能性單體聚合而得到的含環氧基的(甲基)丙烯酸共聚物等丙烯酸系樹脂。在丙烯酸系樹脂中，較佳為含環氧基的(甲基)丙烯酸酯共聚物以及含環氧基的丙烯酸橡膠，更佳為含環氧基的丙烯酸橡膠。含環氧基的丙烯酸橡膠是以丙烯酸酯為主要成分，主要由丙烯酸丁酯與丙烯腈等共聚物、丙烯酸乙酯與丙烯腈等共聚物構成的具有環氧基的橡膠。再者，丙烯酸系樹脂不僅可具有環氧基，亦可具有醇性或酚性羥基、羧基等交聯性官能基。
作為丙烯酸樹脂的市售品，可列舉：長瀨化成（Nagase ChemteX）（股）製造的SG-70L、SG-708-6、WS-023 EK30、SG-280 EK23、SG-P3溶劑變更品（商品名，丙烯酸橡膠，重量平均分子量：80萬，Tg：12℃，溶劑為環己酮）等。
自實現高的晶粒剪切強度的觀點而言，丙烯酸樹脂的玻璃轉移溫度（Tg）較佳為-50℃～50℃，更佳為-30℃～30℃。自實現高的晶粒剪切強度的觀點而言，丙烯酸樹脂的重量平均分子量（Mw）較佳為10萬～300萬，更佳為50萬～200萬。此處，Mw是指藉由凝膠滲透層析法（Gel Permeation Chromatography，GPC）測定，使用基於標準聚苯乙烯的標準曲線進行換算而得到的值。再者，藉由使用分子量分佈窄的丙烯酸樹脂，具有能夠形成高彈性的接著劑片的傾向。
自實現高的晶粒剪切強度的觀點而言，相對於環氧樹脂及環氧樹脂硬化劑的合計100質量份，熱硬化性樹脂組成物中所含的丙烯酸樹脂的量較佳為10質量份～200質量份，更佳為20質量份～100質量份。
[無機填料] 作為無機填料，例如可列舉：氫氧化鋁、氫氧化鎂、碳酸鈣、碳酸鎂、矽酸鈣、矽酸鎂、氧化鈣、氧化鎂、氧化鋁、氮化鋁、硼酸鋁晶須、氮化硼及結晶性二氧化矽、非晶性二氧化矽。該些可單獨使用一種，亦可併用兩種以上。
就實現高的晶粒剪切強度的觀點而言，無機填料的平均粒徑較佳為0.005 μm～1.0 μm，更佳為0.05 μm～0.5 μm。就實現高的晶粒剪切強度的觀點而言，無機填料的表面較佳為經化學修飾。適合作為對表面進行化學修飾的材料者可列舉矽烷偶合劑。作為矽烷偶合劑的官能基的種類，例如可列舉乙烯基、丙烯醯基、環氧基、巰基、胺基、二胺基、烷氧基、乙氧基。
就實現高的晶粒剪切強度的觀點而言，相對於熱硬化性樹脂組成物的樹脂成分100質量份，無機填料的含量較佳為20質量份～200質量份，更佳為30質量份～100質量份。
[硬化促進劑] 作為硬化促進劑，例如可列舉：咪唑類及其衍生物、有機磷系化合物、二級胺類、三級胺類、及四級銨鹽。就實現高的晶粒剪切強度的觀點而言，較佳為咪唑系的化合物。作為咪唑類，可列舉2-甲基咪唑、1-苄基-2-甲基咪唑、1-氰基乙基-2-苯基咪唑、1-氰基乙基-2-甲基咪唑等。該些可單獨使用一種，亦可併用兩種以上。
就實現高的晶粒剪切強度的觀點而言，相對於環氧樹脂及環氧樹脂硬化劑的合計100質量份，熱硬化性樹脂組成物的硬化促進劑的含量較佳為0.04質量份～3質量份，更佳為0.04質量份～0.2質量份。
＜第二實施方式＞ 圖9是示意性地表示第二實施方式的半導體裝置的剖面圖。第一實施方式所涉及的半導體裝置100是晶片T1與接著劑片Tc分離的形態，相對於此，本實施方式所涉及的半導體裝置200中，晶片T1與接著劑片Tc接觸。即，接著劑片Tc與晶片T1的上表面及支持片Dc的上表面接觸。例如，藉由適當設定支持片形成用膜D的厚度，能夠使晶片T1的上表面的位置與支持片Dc的上表面的位置一致。
在半導體裝置200中，晶片T1相對於基板10並非打線接合連接，而是經倒裝晶片（flip chip）連接。再者，只要設為導線w嵌入接著劑片Ta的構成，則即使是將晶片T1打線接合到基板10的形態，晶片T1亦可為與接著劑片Tc接觸的狀態。接著劑片Ta與晶片T2一起構成帶接著劑片的晶片T2a（參照圖8）。
如圖9所示，晶片T1與晶片T2之間的接著劑片Tc覆蓋晶片T2中的與晶片T1相對的區域R，並且自區域R連續地延伸至晶片T2的周緣側。所述一個接著劑片Tc覆蓋晶片T2的區域R，並夾設在晶片T2與多個支持片之間而將該些接著。圖9中的晶片T2的下表面相當於背面。如上所述，近年來晶片的背面多形成有凹凸。藉由晶片T2背面的實質上的整體被接著劑片Tc覆蓋，即使晶片T1的上表面接觸接著劑片Tc，亦能夠抑制晶片T2產生裂縫或破裂。
以上，詳細地說明了本揭示的實施方式，但本發明並不限定於上述實施方式。例如，在所述實施方式中，例示了具有紫外線硬化型的黏著層2的積層膜20，但黏著層2亦可為感壓型。
在所述實施方式中，如圖3的（b）所示，例示了具備由熱硬化性樹脂層構成的支持片形成用膜D的支持片形成用積層膜20，但支持片形成用積層膜可具備具有熱硬化性樹脂層及較該熱硬化性樹脂層具有更高剛性的樹脂層或金屬層的多層膜。圖10的（a）所示的支持片形成用積層膜20A具有包括熱硬化性樹脂層5、及較熱硬化性樹脂層5具有更高剛性的樹脂層6的雙層膜D2（支持片形成用膜）。即，在支持片形成用積層膜20A中，在黏著層2與最外面的樹脂層6之間配置有熱硬化性樹脂層5。再者，熱硬化性樹脂層5由構成第一實施方式的支持片形成用膜D的熱硬化性樹脂組成物構成。樹脂層6的厚度例如為5 μm～100 μm，亦可為10 μm～90 μm或20 μm～80 μm。樹脂層6例如為聚醯亞胺層。熱硬化性樹脂層5為由與樹脂層6不同的材質構成。
熱硬化性樹脂層5的厚度相對於雙層膜D2的厚度的比率較佳為0.1～0.8，更佳為0.2～0.7，進而佳為0.2～0.6。藉由該比率為0.1以上，接著劑片5p、接著劑片5c能夠更高度地發揮其作用（例如，支持晶片T2及防止樹脂片6p的位置偏移）。另一方面，若比率為0.8以下，則樹脂片6p具有充分的厚度，因此樹脂片6p起到如彈簧板般的作用，能夠實現更優異的拾取性（參照圖5的（d））。自該些觀點出發，樹脂層6的厚度例如為20 μm～80 μm，亦可為20 μm～60 μm。熱硬化性樹脂層5的厚度例如為5 μm～120 μm，亦可為10 μm～60 μm。
圖10的（b）所示的支持片形成用積層膜20B具有三層膜D3（支持片形成用膜），該三層膜D3包括：較熱硬化性樹脂層具有更高剛性的樹脂層6、及夾持樹脂層6的二層的熱硬化性樹脂層5。在支持片形成用積層膜20B中，在黏著層2的表面上配置有三層膜D3。熱硬化性樹脂層5為由與樹脂層6不同的材質構成。
支持片形成用積層膜20A、支持片形成用積層膜20B包含較熱硬化性樹脂層5具有更高剛性的樹脂層6，藉此即使在藉由切割而被單片化之後不實施熱硬化性樹脂層5的熱硬化處理，亦能夠實現優異的拾取性。在支持片形成用積層膜20A、支持片形成用積層膜20B中，可採用較熱硬化性樹脂層高的金屬層（例如、銅層或鋁層）來代替樹脂層6。金屬層的厚度例如為5 μm～100 μm，亦可為10 μm～90 μm或20 μm～80 μm。藉由使支持片形成用積層膜20A、支持片形成用積層膜20B包含金屬層，除了優異的拾取性以外，藉由樹脂材料與金屬材料的光學對比度，還能夠在拾取步驟中實現支持片的優異的視認性。
兩個熱硬化性樹脂層5、熱硬化性樹脂層5的厚度的合計相對於三層膜D3的厚度的比率較佳為0.1～0.9，更佳為0.2～0.8，進而佳為0.2～0.7。藉由該比率在上述範圍內，在支持片的製造過程中能夠實現拾取性（參照圖5的（d））。即，藉由比率為0.1以上，即使在採用金屬層代替樹脂層6的情況下，亦能夠更高度地抑制由金屬片（金屬層被單片化而成者）的邊緣進入黏著層2引起的支持片的拾取性降低。另一方面，若比率為0.9以下，則樹脂片（樹脂層6被單片化而成者）或金屬片具有足夠的厚度，因此該些發揮如彈簧板般的作用，能夠實現更優異的拾取性。自該些觀點出發，樹脂層6或金屬層的厚度例如為10 μm～80 μm，亦可為20 μm～60 μm。熱硬化性樹脂層5（一層）的厚度例如為5 μm～120 μm，亦可為10 μm～60 μm。
如上述膜D2、膜D3般，藉由支持片形成用膜具有由相互不同的材質構成的多個層，能夠使各層分擔功能，從而能夠實現膜的高功能化。藉由將該多層結構的膜單片化，能夠製作更適合支石墓結構的支持片Da。
支持片形成用積層膜20A例如可經過以下步驟來製造。 ·準備依次具備基材膜1、黏著層2、及熱硬化性樹脂層5的積層膜的步驟； ·在所述積層膜的表面貼合較熱硬化性樹脂層5具有更高剛性的樹脂層6或金屬層的步驟。 [實施例]
以下，藉由實施例對本揭示進行說明，但本發明並不限定於該些實施例。
（清漆A的製備） 使用以下的材料製備了用於支持片形成用膜的清漆A。 ·環氧樹脂1：YDCN-700-10：（商品名、新日鐵住金化學（股）製造，甲酚酚醛清漆型環氧樹脂，25℃下為固體）5.4質量份 ·環氧樹脂2：YDF-8170C：（商品名、新日鐵住金化學（股）製造，液態雙酚F型環氧樹脂，25℃下為液態）16.2質量份 ·酚樹脂（硬化劑）：LF-4871：（商品名、迪愛生（DIC）（股）製造，BPA酚醛清漆型酚樹脂）13.3質量份 ·無機填料：SC2050-HLG：（商品名、（股）雅都瑪（ADMATECHS）製造，二氧化矽填料分散液、平均粒徑0.50 μm）49.8質量份 ·彈性體：SG-P3溶劑變更品（商品名，長瀨化成（Nagase ChemteX）（股）製造，丙烯酸橡膠，重量平均分子量：80萬、Tg：12℃，溶劑為環己酮）14.9質量份 ·偶合劑1：A-189：（商品名，通用電氣（General Electric，GE）東芝（股）製造，γ-巰基丙基三甲氧基矽烷）0.1質量份 ·偶合劑2：A-1160：（商品名，通用電氣（General Electric，GE）東芝（股）製造，γ-脲基丙基三乙氧基矽烷）0.3質量份 ·硬化促進劑：固唑（Curezol）2PZ-CN：（商品名，四國化成工業（股）製造，1-氰基乙基-2-苯基咪唑）0.05質量份 ·溶媒：環己烷
（清漆B的製備） 使用以下的材料製備了用於支持片形成用膜的清漆B。 ·環氧樹脂：YDCN-700-10：（商品名，新日鐵住金化學（股）製造，甲酚酚醛清漆型環氧樹脂，25℃下為固體）13.2質量份 ·酚樹脂（硬化劑）：HE-100C-30：（商品名、愛沃特（AIR WATER）（股）製造、苯基芳烷基型酚樹脂）11.0質量份 ·無機填料：艾羅西爾（Aerosil）R972：（商品名、日本艾羅西爾（Aerosil）（股）製造、二氧化矽、平均粒徑0.016 μm）7.8質量份 ·彈性體：SG-P3溶劑變更品（商品名、長瀨化成（Nagase ChemteX）（股）製造、丙烯酸橡膠、重量平均分子量：80萬、Tg：12℃、溶劑為環己酮）66.4質量份 ·偶合劑1：A-189：（商品名，通用電氣（General Electric，GE）東芝（股）製造，γ-巰基丙基三甲氧基矽烷）0.4質量份 ·偶合劑2：A-1160：（商品名、通用電氣（General Electric，GE）東芝（股）製造，γ-脲基丙基三乙氧基矽烷）1.15質量份 ·硬化促進劑：固唑（Curezol）2PZ-CN：（商品名、四國化成工業（股）製造，1-氰基乙基-2-苯基咪唑）0.03質量份 ·溶媒：環己烷
＜實施例1＞ 如上所述，使用環己酮作為溶媒，將清漆A的固體成分比例調整為40質量%。用100目的過濾器過濾清漆A的同時進行真空脫泡。作為塗佈清漆A的膜，準備實施有脫模處理的聚對苯二甲酸乙二酯（PET）膜（厚度38 μm）。將真空脫泡後的清漆A塗佈於PET膜的實施了脫模處理的面上。對塗佈的清漆A以90℃5分鐘、繼而140℃5分鐘的兩階段進行加熱乾燥。如此，在PET膜的表面上製作B階段狀態（半硬化狀態）的熱硬化性樹脂層A。
按照以下順序製作了具有紫外線硬化型黏著層的積層膜（切割帶）。首先，以丙烯酸2-乙基己酯83質量份、丙烯酸2-羥基乙酯15質量份、甲基丙烯酸2質量份為原料，溶媒使用乙酸乙酯，藉由溶液自由基聚合得到共聚物。使12質量份2-甲基丙烯醯氧基乙基異氰酸酯與該丙烯酸共聚物反應，合成了具有碳-碳雙鍵的紫外線照射型丙烯酸共聚物。在所述反應時，作為聚合抑制劑使用0.05份氫醌-單甲醚。用GPC測定合成的丙烯酸共聚物的重量平均分子量，結果為30萬～70萬。將如此得到的丙烯酸共聚物、以固體成分換算計為2.0份的作為硬化劑的聚異氰酸酯化合物（日本聚胺基甲酸酯（股）製造，商品名：科羅耐特（Coronate）L）、作為光聚合起始劑的1-羥基環己基苯基酮0.5份混合，製備紫外線照射型黏著劑溶液。將該紫外線照射型黏著劑溶液以乾燥後的厚度為10 μm的方式塗佈在聚對苯二甲酸乙二酯製的剝離膜（厚度：38 μm）上，並進行乾燥。然後，在黏著劑層上貼合單面實施了電暈放電處理的聚烯烴製膜（厚度：90 μm）。將得到的積層膜在40℃的恆溫槽中進行72小時老化，製作切割帶。
將厚度為50 μm的熱硬化性樹脂層A在110℃下加熱1小時後，在130℃下加熱3小時使其硬化，得到硬化樹脂層A。在70℃加熱板上使用橡膠輥將硬化樹脂層A貼合在切割帶的黏著層上。經過該步驟得到支持片形成用膜與切割帶的積層體。
＜實施例2＞ 代替將熱硬化性樹脂層A在110℃下加熱1小時後，在130℃下加熱3小時，而是藉由在110℃下加熱2小時使熱硬化性樹脂層A硬化，除此之外與實施例1同樣地得到支持片形成用膜與切割帶的積層體。
＜實施例3＞ 使用清漆B代替清漆A而在PET膜的表面上形成熱硬化性樹脂層B，並且在70℃的加熱板上，用橡膠輥將熱硬化性樹脂層B貼合於切割帶的黏著層之後，用橡膠輥將聚醯亞胺膜（厚度25 μm）貼合於熱硬化性樹脂層B。經過所述步驟得到支持片形成用膜與切割帶的積層體。
對實施例1～實施例3的支持片形成用膜進行以下的評價。 （1）剝離強度 將包含實施例1～實施例3的支持片形成用膜的積層體分別切成寬25 mm、長100 mm的長度，來製作試驗片。其後，用鹵素燈在80 mW/cm2 、200 mJ/cm2 的條件下自切割帶側照射紫外線。測定紫外線照射的黏著層與支持片形成用膜的界面的剝離強度（剝離角度：180°、剝離速度：300 mm/分鐘）。對各實施例進行3次測定，其平均值如下所示。 ·實施例1…0.03 N/25 mm ·實施例2…0.04 N/25 mm ·實施例3…0.05 N/25 mm
（2）拾取性 準備實施例1～實施例3的支持片形成用膜（形狀：直徑320 mm的圓形）與和所述同樣製作的切割帶（形狀：直徑335 mm的圓形）的積層體。在70℃的條件下在該積層體的切割帶上層壓切割環。使用切割機在高度55 μm的條件下將支持片形成用膜單片化。藉此，得到了尺寸為10 mm×10 mm的支持片。用鹵素燈在80 mW/cm2 、200 mJ/cm2 的條件下自切割帶側向支持片的黏著層照射紫外線。之後，用黏晶機在擴展（擴展量：3 mm）的狀態下拾取支持片。作為上推夾具，使用三段上推台，條件為上推速度10 mm/秒及上推高度1200 μm。當針對各實施例、對6個支持片嘗試拾取時，在實施例1～實施例3的任何一個中都能夠拾取6個支持片全部。 [產業上之可利用性]
根據本揭示，提供一種在具有支石墓結構的半導體裝置的製造製程中，能夠簡化製作支持片的步驟的半導體裝置的製造方法。另外，根據本揭示，提供一種具有支石墓結構的半導體裝置、以及支持片形成用積層膜及其製造方法。
1:基材膜 2:黏著層 3:覆蓋層 5:熱硬化性樹脂層 6:樹脂層 10:基板 20、20A、20B:支持片形成用積層膜 30:結構體 42:上推夾具 44:抽吸夾頭 50:密封材 100、200:半導體裝置 D:支持片形成用膜 D2:雙層膜（支持片形成用膜） D3:三層膜（支持片形成用膜） Da:支持片 Dc:支持片（硬化物） DR:切割環 R:區域 T1:第一晶片（晶片） T2:第二晶片（晶片） T3、T4:晶片 T1c:接著劑片/接著劑層 T2a:帶接著劑片的晶片 Ta:接著劑片 Tc:接著劑片（硬化物） w:導線
圖1是示意性地表示本揭示的半導體裝置的第一實施方式的剖面圖。 圖2的（a）及圖2的（b）是示意性地表示第一晶片與多個支持片的位置關係的例子的平面圖。 圖3的（a）是示意性地表示支持片形成用積層膜的一實施方式的平面圖，圖3的（b）是圖3的（a）的b-b線處的剖面圖。 圖4是示意性地表示貼合黏著層與支持片形成用膜的步驟的剖面圖。 圖5的（a）～圖5的（d）是示意性地表示支持片的製作過程的剖面圖。 圖6是示意性地表示在基板上且為第一晶片周圍配置有多個支持片的狀態的剖面圖。 圖7是示意地表示帶接著劑片的晶片一例的剖面圖。 圖8是示意性地表示形成在基板上的支石墓結構的剖面圖。 圖9是示意性地表示本揭示的半導體裝置的第二實施方式的剖面圖。 圖10的（a）及圖10的（b）是分別示意性地表示支持片形成用積層膜的另一實施方式的剖面圖。
10:基板
50:密封材
100:半導體裝置
Dc:支持片(硬化物)
R:區域
T1:第一晶片(晶片)
T1c:接著劑片/接著劑層
T2:第二晶片(晶片)
T3、T4:晶片
Tc:接著劑片(硬化物)
w:導線

Claims (20)

  1. 一種半導體裝置的製造方法，其為製造具有支石墓結構的半導體裝置的方法，所述支石墓結構包括：基板；第一晶片，配置於所述基板上；多個支持片，配置於所述基板上且為所述第一晶片的周圍；以及第二晶片，由所述多個支持片支持且配置成覆蓋所述第一晶片，其中所述半導體裝置的製造方法包括以下步驟： （A）準備依次具備基材膜、黏著層、及支持片形成用膜的積層膜的步驟； （B）藉由將所述支持片形成用膜單片化，而在所述黏著層的表面上形成多個支持片的步驟； （C）自所述黏著層拾取所述支持片的步驟； （D）在基板上配置第一晶片的步驟； （E）在所述基板上且為所述第一晶片的周圍或應配置所述第一晶片的區域的周圍，配置所述多個支持片的步驟； （F）準備帶接著劑片的晶片的步驟，所述帶接著劑片的晶片具備第二晶片、及設置在所述第二晶片的一個面上的接著劑片；以及 （G）藉由在所述多個支持片的表面上配置所述帶接著劑片的晶片來構築支石墓結構的步驟， 所述支持片形成用膜為由熱硬化性樹脂層構成的膜、或為由使熱硬化性樹脂層中的至少一部分硬化而成的層構成的膜、或者為包括熱硬化性樹脂層、以及較所述熱硬化性樹脂層具有更高剛性的樹脂層或金屬層的多層膜。
  2. 如請求項1所述的半導體裝置的製造方法，其中所述黏著層為紫外線硬化型，且 在（B）步驟與（C）步驟之間，包括對所述黏著層照射紫外線的步驟。
  3. 如請求項1或請求項2所述的半導體裝置的製造方法，其在（G）步驟之前，包括對所述支持片形成用膜或所述支持片進行加熱的步驟。
  4. 一種半導體裝置，具有支石墓結構，所述支石墓結構包括： 基板； 第一晶片，配置於所述基板上； 多個支持片，配置於所述基板上且為所述第一晶片的周圍；以及 第二晶片，由所述多個支持片支持且配置成覆蓋所述第一晶片，且 所述支持片由熱硬化性樹脂組成物的硬化物構成，或者包括由熱硬化性樹脂組成物的硬化物構成的層、以及樹脂層或金屬層。
  5. 如請求項4所述的半導體裝置，其中，所述第一晶片與所述第二晶片分離。
  6. 如請求項4或請求項5所述的半導體裝置，其更包括接著劑片，所述接著劑片設置在所述第二晶片的一個面上並且被所述第二晶片與所述多個支持片夾持。
  7. 如請求項6所述的半導體裝置，其中，所述第一晶片與所述接著劑片分離。
  8. 如請求項4或請求項5所述的半導體裝置，其更包括接著劑片，所述接著劑片以至少覆蓋所述第二晶片中的與所述第一晶片相對的區域的方式設置，且 所述第一晶片與所述接著劑片分離。
  9. 如請求項8所述的半導體裝置，其中，所述接著劑片自所述第二晶片的所述區域連續地延伸至所述第二晶片的周緣側，並且被所述第二晶片與所述多個支持片夾持。
  10. 如請求項6所述的半導體裝置，其中，所述第一晶片與所述接著劑片接觸。
  11. 如請求項10所述的半導體裝置，其中，所述接著劑片覆蓋所述第二晶片中的與所述第一晶片相對的區域，並且自所述第二晶片的所述區域連續地延伸至所述第二晶片的周緣側，且被所述第二晶片與所述多個支持片夾持。
  12. 一種支持片形成用積層膜，用於具有支石墓結構的半導體裝置的製造製程，所述支石墓結構包括：基板；第一晶片，配置於所述基板上；多個支持片，配置於所述基板上且為所述第一晶片的周圍；以及第二晶片，由所述多個支持片支持且配置成覆蓋所述第一晶片，且所述支持片形成用積層膜依次包括： 基材膜、 黏著層、以及 支持片形成用膜，且 所述支持片形成用膜為由熱硬化性樹脂層構成的膜、或為由使熱硬化性樹脂層中的至少一部分硬化而成的層構成的膜、或者為包括熱硬化性樹脂層、以及較所述熱硬化性樹脂層具有更高剛性的樹脂層或金屬層的多層膜。
  13. 如請求項12所述的支持片形成用積層膜，其中所述支持片形成用膜的厚度為5 μm～180 μm。
  14. 如請求項12或請求項13所述的支持片形成用積層膜，其中所述黏著層為感壓型或紫外線硬化型。
  15. 如請求項12至請求項14中任一項所述的支持片形成用積層膜，其中所述熱硬化性樹脂層含有環氧樹脂。
  16. 如請求項12至請求項15中任一項所述的支持片形成用積層膜，其中所述熱硬化性樹脂層含有彈性體。
  17. 如請求項12至請求項16中任一項所述的支持片形成用積層膜，其中所述樹脂層為聚醯亞胺層。
  18. 如請求項12至請求項17中任一項所述的支持片形成用積層膜，其中所述金屬層為銅層或鋁層。
  19. 一種支持片形成用積層膜的製造方法，其為具有支石墓結構的半導體裝置的製造製程中所使用的支持片形成用積層膜的製造方法，所述支石墓結構包括：基板；第一晶片，配置於所述基板上；多個支持片，配置於所述基板上且為所述第一晶片的周圍；以及第二晶片，由所述多個支持片支持且配置成覆蓋所述第一晶片，且所述支持片形成用積層膜的製造方法包括： 準備黏著膜的步驟，所述黏著膜具有基材膜、及形成在所述基材膜的一個面上的黏著層；以及 在所述黏著層的表面上積層支持片形成用膜的步驟，且 所述支持片形成用膜為由熱硬化性樹脂層構成的膜、或為由使熱硬化性樹脂層中的至少一部分硬化而成的層構成的膜、或者為包括熱硬化性樹脂層、以及較所述熱硬化性樹脂層具有更高剛性的樹脂層或金屬層的多層膜。
  20. 一種支持片形成用積層膜的製造方法，其為具有支石墓結構的半導體裝置的製造製程中所使用的支持片形成用積層膜的製造方法，所述支石墓結構包括：基板；第一晶片，配置於所述基板上；多個支持片，配置於所述基板上且為所述第一晶片的周圍；以及第二晶片，由所述多個支持片支持且配置成覆蓋所述第一晶片，且所述支持片形成用積層膜的製造方法包括： 準備積層膜的步驟，所述積層膜依次具備基材膜、黏著層、及熱硬化性樹脂層；以及 在所述熱硬化性樹脂層的表面貼合較所述熱硬化性樹脂層具有更高剛性的樹脂層或金屬層的步驟。
TW109113932A 2019-04-25 2020-04-24 具有支石墓結構的半導體裝置及其製造方法以及支持片形成用積層膜及其製造方法 TW202107670A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
WOPCT/JP2019/017688 2019-04-25
PCT/JP2019/017688 WO2020217394A1 (ja) 2019-04-25 2019-04-25 ドルメン構造を有する半導体装置及びその製造方法、並びに、支持片形成用積層フィルム及びその製造方法

Publications (1)

Publication Number Publication Date
TW202107670A true TW202107670A (zh) 2021-02-16

Family

ID=72940649

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109113932A TW202107670A (zh) 2019-04-25 2020-04-24 具有支石墓結構的半導體裝置及其製造方法以及支持片形成用積層膜及其製造方法

Country Status (7)

Country Link
US (1) US20220149031A1 (zh)
JP (1) JP7494843B2 (zh)
KR (1) KR20220002255A (zh)
CN (1) CN113574665A (zh)
SG (1) SG11202110148YA (zh)
TW (1) TW202107670A (zh)
WO (2) WO2020217394A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023102570A (ja) * 2022-01-12 2023-07-25 株式会社レゾナック 個片化体形成用積層フィルム及びその製造方法、並びに半導体装置の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002222889A (ja) * 2001-01-24 2002-08-09 Nec Kyushu Ltd 半導体装置及びその製造方法
KR20030018204A (ko) * 2001-08-27 2003-03-06 삼성전자주식회사 스페이서를 갖는 멀티 칩 패키지
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
JP4188337B2 (ja) * 2004-05-20 2008-11-26 株式会社東芝 積層型電子部品の製造方法
TWI292617B (en) * 2006-02-03 2008-01-11 Siliconware Precision Industries Co Ltd Stacked semiconductor structure and fabrication method thereof
US20080029885A1 (en) * 2006-08-07 2008-02-07 Sandisk Il Ltd. Inverted Pyramid Multi-Die Package Reducing Wire Sweep And Weakening Torques
JP5791866B2 (ja) * 2009-03-06 2015-10-07 株式会社ディスコ ワーク分割装置
JP5840479B2 (ja) * 2011-12-20 2016-01-06 株式会社東芝 半導体装置およびその製造方法
KR101906269B1 (ko) * 2012-04-17 2018-10-10 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
JP2015176906A (ja) * 2014-03-13 2015-10-05 株式会社東芝 半導体装置および半導体装置の製造方法
US9418974B2 (en) * 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods

Also Published As

Publication number Publication date
KR20220002255A (ko) 2022-01-06
JPWO2020218526A1 (zh) 2020-10-29
WO2020218526A1 (ja) 2020-10-29
WO2020217394A1 (ja) 2020-10-29
SG11202110148YA (en) 2021-11-29
JP7494843B2 (ja) 2024-06-04
US20220149031A1 (en) 2022-05-12
CN113574665A (zh) 2021-10-29

Similar Documents

Publication Publication Date Title
US11935870B2 (en) Method for manufacturing semiconductor device having dolmen structure, method for manufacturing support piece, and laminated film
JP7247733B2 (ja) ドルメン構造を有する半導体装置の製造方法
WO2020100998A1 (ja) 半導体装置及びその製造方法、並びに半導体装置の製造に使用される構造体
TW202107670A (zh) 具有支石墓結構的半導體裝置及其製造方法以及支持片形成用積層膜及其製造方法
JP7494841B2 (ja) ドルメン構造を有する半導体装置及びその製造方法、並びに、支持片形成用積層フィルム及びその製造方法
TWI833985B (zh) 支撐片的製造方法、半導體裝置的製造方法及支撐片形成用積層膜
TWI830905B (zh) 具有支石墓結構的半導體裝置及其製造方法以及支持片形成用積層膜及其製造方法
WO2020218530A1 (ja) ドルメン構造を有する半導体装置の製造方法及び支持片の製造方法
TWI844668B (zh) 具有支石墓結構的半導體裝置的製造方法、支撐片的製造方法、以及支撐片形成用積層膜
TWI830901B (zh) 半導體裝置的製造方法
TW202107668A (zh) 具有支石墓結構的半導體裝置的製造方法及支持片的製造方法
JP7351335B2 (ja) ドルメン構造を有する半導体装置及びその製造方法、支持片の製造方法、並びに、支持片形成用積層フィルム
JP7482112B2 (ja) ドルメン構造を有する半導体装置の製造方法、支持片の製造方法、及び支持片形成用積層フィルム
TW202420557A (zh) 具有支石墓結構的半導體裝置的製造方法
JP2022153830A (ja) 支持部材の製造方法、及び、半導体装置の製造方法