TW202018898A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TW202018898A TW202018898A TW108124032A TW108124032A TW202018898A TW 202018898 A TW202018898 A TW 202018898A TW 108124032 A TW108124032 A TW 108124032A TW 108124032 A TW108124032 A TW 108124032A TW 202018898 A TW202018898 A TW 202018898A
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- hole electrode
- semiconductor
- hole
- wafer
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
- H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/811—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/81101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a bump connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
一種半導體封裝包括基底晶圓以及第一半導體晶片,所述基底晶圓包括第一基板以及延伸穿過所述第一基板的至少一個第一貫通孔電極,所述第一半導體晶片設置於所述基底晶圓上。所述第一半導體晶片包括第二基板以及延伸穿過所述第二基板的至少一個第二貫通孔電極。所述至少一個第二貫通孔電極設置於所述至少一個第一貫通孔電極上以電性連接至所述至少一個第一貫通孔電極。所述至少一個第一貫通孔電極在第一方向上的第一直徑大於所述至少一個第二貫通孔電極在所述第一方向上的第二直徑。
Description
示例性實施例是有關於一種半導體封裝,且更具體而言,是有關於一種包括貫通孔電極的半導體封裝。
在半導體封裝中,高頻寬記憶體(high bandwidth memory,HBM)可藉由晶圓上晶片(chip-on-wafer,CoW)製程堆疊於晶圓上。另外,可在晶圓上形成穿透矽通孔(through-silicon via,TSV),所述穿透矽通孔是穿過晶圓的電性連接。隨著TSV的大小及晶圓的厚度變小而仍然需要確保高速度及高容量,在CoW製程之後的後續製程中晶圓可能更容易因翹曲而受到損壞。
一或多個示例性實施例提供一種具有高可靠性的半導體封裝。
根據示例性實施例的態樣,提供一種半導體封裝。所述半導體封裝可包括基底晶圓以及第一半導體晶片,所述基底晶圓包括第一基板以及延伸穿過所述第一基板的至少一個第一貫通孔電極,所述第一半導體晶片設置於所述基底晶圓上。所述第一半導體晶片包括第二基板以及延伸穿過所述第二基板的至少一個第二貫通孔電極。所述至少一個第二貫通孔電極設置於所述至少一個第一貫通孔電極上以電性連接至所述至少一個第一貫通孔電極。所述至少一個第一貫通孔電極在第一方向上的第一直徑大於所述至少一個第二貫通孔電極在所述第一方向上的第二直徑。
根據另一示例性實施例的態樣,提供一種半導體封裝。所述半導體封裝可包括基底晶圓以及半導體晶片,所述基底晶圓包括第一基板以及延伸穿過所述第一基板的第一貫通孔電極,所述半導體晶片設置於所述基底晶圓上且包括第二基板以及延伸穿過所述第二基板的第二貫通孔電極。所述第一貫通孔電極在第一方向上的第一直徑不同於所述第二貫通孔電極在所述第一方向上的第二直徑。所述第一貫通孔電極的第一長寬比等於或大於所述第二貫通孔電極的第二長寬比。
根據另一示例性實施例的態樣,提供一種半導體封裝。所述半導體封裝可包括封裝基板、中介層、基底晶片、第一半導體晶片以及處理器晶片,所述中介層設置於所述封裝基板上,所述基底晶片包括第一基板以及延伸穿過所述第一基板的至少一個第一貫通孔電極,所述第一半導體晶片設置於所述基底晶片上且包括第二基板以及延伸穿過所述第二基板的至少一個第二貫通孔電極,所述處理器晶片設置於所述中介層上且在第一方向上與所述基底晶片間隔開。所述至少一個第二貫通孔電極設置於所述至少一個第一貫通孔電極上以電性連接至所述至少一個貫通孔電極。所述至少一個第一貫通孔電極在所述第一方向上的第一直徑大於所述至少一個第二貫通孔電極在所述第一方向上的第二直徑。
圖1是示出根據示例性實施例的半導體封裝10的剖視圖。
參照圖1,半導體封裝10可包括依序堆疊於基底晶圓250上的多個第一半導體晶片455及第二半導體晶片555。所述多個第一半導體晶片455及第二半導體晶片555的側壁可被基底晶圓250上的模製元件600覆蓋。
基底晶圓250可包括第一絕緣中介層110、第二絕緣中介層150及第一導電凸塊180,第一絕緣中介層110、第二絕緣中介層150及第一導電凸塊180向下依序堆疊於第一基板100的下表面(或第一表面101)上。亦即,參照圖1,第一絕緣中介層110堆疊於第一基板100的下表面101下方,第二絕緣中介層150堆疊於第一絕緣中介層110下方,且第一導電凸塊180堆疊於第二絕緣中介層150下方。基底晶圓250可更包括延伸穿過第一基板100及第一絕緣中介層110的第一貫通孔電極145、設置於第二絕緣中介層150中的第一配線結構170、設置於第一基板100的頂表面(或第二表面102)上且亦覆蓋第一貫通孔電極145的上側壁的第一鈍化層210以及設置於第一鈍化層210上並接觸第一貫通孔電極145的上表面的第一導電焊墊220。
第一基板100可包括矽(Si)、鍺(Ge)、矽鍺(SiGe)或III-V族化合物(例如,磷化鎵(GaP)、砷化鎵(GaAs)、銻化鎵(GaSb)等)。在一些示例性實施例中,第一基板100可為絕緣體上矽(silicon-on-insulator,SOI)基板或絕緣體上鍺(germanium-on-insulator,GeOI)基板。
第一基板100可具有第一表面(例如,底表面)101及與第一表面101相對的第二表面(例如,頂表面)102,且第一表面101與第二表面102之間的距離(即,第一基板100在實質上垂直於第一表面101的垂直方向上的厚度)可為第一厚度T1。
在示例性實施例中,在第一基板100的第一表面101下方可形成有電路元件,第一基板100的第一表面101可被第一絕緣中介層110覆蓋。亦即,在第一基板100與第一絕緣中介層110之間可設置有電路元件。舉例來說,在第一基板100與第一絕緣中介層110之間可形成有作為電路元件的電晶體。電晶體可包括位於第一基板100的第一表面101下面的閘極結構以及在與閘極結構相鄰的第一基板100的下部部分處的雜質區。然而,實施例並非僅限於此,且舉例來說,可形成二極體、電阻器、電感器、電容器等作為第一基板100與第一絕緣中介層110之間的電路元件。
第一絕緣中介層110可包含氧化物(O2-
),例如氧化矽(SiO2
)。可穿過第一絕緣中介層110形成接觸插塞以接觸上述雜質區及/或閘極結構。接觸插塞可包含金屬、金屬氮化物、金屬矽化物等。
第一貫通孔電極145可延伸穿過第一基板100及第一絕緣中介層110二者以自第一基板100的第二表面102向外(如圖1所示向上)突出。在示例性實施例中,第一貫通孔電極145可包括第一導電層130及設置於第一導電層130的外側壁上的第一絕緣圖案125,且可更包括設置於第一導電層130與第一絕緣圖案125之間的第一障壁圖案。
第一絕緣圖案125可包含氧化物(O2-
)(例如氧化矽(SiO2
)),第一導電層130可包含金屬(例如鎢(W)、銅(Cu)、鋁(Al)等),且第一障壁圖案可包含金屬氮化物(例如氮化鈦(TiN)、氮化鉭(TaN)等)。
在示例性實施例中,第一貫通孔電極145可在水平方向(在圖1中;即,實質上平行於第一基板100的第一表面101)上具有第一直徑D1,且在垂直方向(即,實質上垂直於第一表面101的方向)上具有第一長度L1。
作為示例性實施例,圖1示出彼此間隔開的六個第一貫通孔電極145,然而,示例性實施例可並非僅限於此,且在半導體封裝10中可形成有任何數目的多個第一貫通孔電極145。
第二絕緣中介層150可包含例如摻雜有氟(F)或碳(C)的氧化矽(SiO2
)、多孔SiO2
、旋塗有機聚合物或無機聚合物(例如氫倍半矽氧烷(hydrogen silsesquioxane,HSSQ)、甲基倍半矽氧烷(methyl silsesquioxane,MSSQ)等)。
在示例性實施例中,第一配線結構170可包括設置於第二絕緣中介層150中的至少一個第一配線165以及連接至第一配線165或者將第一配線165與第一貫通孔電極145連接至彼此的至少一個第一通孔160。圖1示出依序堆疊於第一貫通孔電極145的下表面下方的一個第一通孔160及一個第一配線165。第一配線165及第一通孔160中的每一者可包含金屬、金屬氮化物、金屬矽化物等。
第一導電凸塊180可形成於第二絕緣中介層150下方以接觸第一配線165的下表面。第一導電凸塊180可包含金屬(例如,銀(Ag)、銅(Cu)等)或合金,且可形成為焊料。
第一鈍化層210可形成於第一基板100的第二表面(即,頂表面)102上,且可覆蓋第一貫通孔電極145的側壁的上部部分。第一鈍化層210可包含O2-
及/或氮化物(N-3
)。在示例性實施例中,第一鈍化層210可包括多個不同的層,所述多個不同的層包括依序堆疊的第一氧化物層、氮化物層及第二氧化物層。
第一導電焊墊220可形成於第一鈍化層210上以接觸第一貫通孔電極145的上表面。第一導電焊墊220可包含金屬、金屬氮化物、金屬矽化物等。
另外,在第一貫通孔電極145與第一導電焊墊220之間可進一步形成有重佈線層。
在示例性實施例中,基底晶圓250可包括邏輯裝置或控制器。作為另一選擇,基底晶圓250可包括記憶體裝置,例如,動態隨機存取記憶體(dynamic random access memory,DRAM)裝置。
第一半導體晶片455的結構可與基底晶圓250的結構實質上相同或相似,不同之處在於第一半導體晶片455包括第二基板300及第二貫通孔電極345而非第一基板100及第一貫通孔電極145。
更詳細而言,第一半導體晶片455可包括向下依序堆疊於第二基板300的下表面下方的第三絕緣中介層310、第四絕緣中介層350及第二導電凸塊380,此相似於上述基底晶圓250。除了延伸穿過上述第二基板300及第三絕緣中介層310的第二貫通孔電極345之外,第一半導體晶片455可更包括設置於第四絕緣中介層350中的第二配線結構370、設置於第二基板300上並覆蓋第二貫通孔電極345的側壁的上部部分的第二鈍化層410以及設置於第二鈍化層410上並接觸第二貫通孔電極345的上表面的第二導電焊墊420。
第二基板300可具有第一表面(即,下表面)301及與第一表面301相對的第二表面(即,上表面/頂表面)302,且第一表面301與第二表面302之間的距離(即,第二基板300在垂直方向上(即,在垂直於第一表面301及第二表面302的延伸方向的方向上)的厚度)可為第二厚度T2。在示例性實施例中,第二厚度T2可小於第一厚度T1。
在示例性實施例中,在第二基板300的第一表面301下方可形成有電路元件,第二基板300的第一表面301可被第三絕緣中介層310覆蓋。亦即,在第二基板300與第三絕緣層310之間可形成有電路元件。另外,可穿過第三絕緣中介層310形成接觸插塞。
第一貫通孔電極345可延伸穿過第二基板300及第三絕緣中介層310以自第二基板300的第二表面(即,頂表面)302向外突出。在示例性實施例中,第二貫通孔電極345可包括第二導電層330及設置於第二導電層330的外側壁上的第二絕緣圖案325,且可更包括位於第二導電層330與第二絕緣圖案325之間的第二障壁圖案。
第二貫通孔電極345可在水平方向上具有第二直徑D2且在垂直方向上具有第二長度L2。在示例性實施例中,第二貫通孔電極345的第二直徑D2可小於第一貫通孔電極145的第一直徑D1,且第二貫通孔電極345的第二長度L2可小於第一貫通孔電極145的第一長度L1。
然而,第一長度L1相對於第一直徑D1的比率(例如,第一長寬比)可實質上等於或大於第二長度L2相對於第二直徑D2的比率(例如,第二長寬比)。
在圖1所示的示例性實施例中,半導體封裝10包括彼此間隔開的三個第二貫通孔電極345,然而,示例性實施例可並非僅限於此,且可形成任何數目的多個第二貫通孔電極345。
在示例性實施例中,第二配線結構370可包括設置於第四絕緣中介層350中的至少一個第二配線365及連接至第二配線365或者將第二配線365與第二貫通孔電極345連接至彼此的至少一個第二通孔360。
在示例性實施例中,可在基底晶圓250上以垂直方向堆疊一或多個第一半導體晶片455。圖1示出堆疊於基底晶圓250上的三個第一半導體晶片455,然而,示例性實施例可並非僅限於此。舉例來說,第一半導體晶片455可以七個層階堆疊。
在示例性實施例中,第一半導體晶片455可為記憶體晶片,例如,DRAM晶片。
另外,多個第一半導體晶片455可在水平方向上彼此間隔開。
第二半導體晶片555可堆疊於堆疊的第一半導體晶片455中的最上部的一個第一半導體晶片455上或第一半導體晶片455中的一者上。在示例性實施例中,不同於第一半導體晶片455,第二半導體晶片555可不包括任何貫通孔電極,且第二半導體晶片555中的第三基板500可在垂直方向上具有第三厚度T3。第三基板500的第三厚度T3可大於第一半導體晶片455的第二厚度T2。
在示例性實施例中,第二半導體晶片555可為記憶體晶片,例如DRAM晶片。
在示例性實施例中,在基底晶圓250與所述多個第一半導體晶片455中的最下部的一個第一半導體晶片455之間、在堆疊於垂直方向上的兩個相鄰的第一半導體晶片445之間以及在所述多個第一半導體晶片455中的最上部的一個第一半導體晶片455與第二半導體晶片555之間可形成有第三黏附層440。所述多個第一半導體晶片455及第二半導體晶片555可藉由第一導電焊墊220及第二導電焊墊420以及第二導電凸塊380電性連接至彼此。
在示例性實施例中,模製元件600可包括環氧模製化合物(epoxy molding compound,EMC)。
在示例性實施例中,在半導體封裝10中,基底晶圓250中的第一基板100的第一厚度T1可大於堆疊於第一基板100上的所述多個第一半導體晶片455中的每一者的第二厚度T2,且因此,由於潛在的翹曲導致的半導體封裝10的損壞可減小。因此,半導體封裝10可以增強的可靠性及更少的報廢與重工來製造。
設置於所述多個第一半導體晶片455中的每一者中的第二貫通孔電極345的第二直徑D2可小於設置於基底晶圓250中的第一貫通孔電極145的第一直徑D1,且因此就第一半導體晶片455在電路圖案或配線的佈局中的放置而言,第一半導體晶片455可具有增大的誤差裕度。
另外,在示例性實施例中,第二貫通孔電極345的第二長寬比可實質上等於或小於第一貫通孔電極145的第一長寬比,且因此,即使第二貫通孔電極345具有相對小的直徑,亦可藉由相應地減小第二貫通孔電極345的垂直長度來使第二貫通孔電極345的特性不劣化。
另外,第一半導體晶片455中的每一者中的第二基板300的第二厚度T2可小於基底晶圓250中的第一基板100的第一厚度T1,且因此在基底晶圓250上可堆疊有更大數目的第一半導體晶片455,且半導體封裝10可具有增大的容量以及增強的效能。
圖2至圖9是示出根據示例性實施例的製造圖1所示半導體封裝10的方法的剖視圖。
參照圖2,可在第一基板100的第一表面101(即,圖1所示底表面101)上形成電路元件,且可在第一基板100的第一表面101上形成第一絕緣中介層110以覆蓋電路元件/使電路元件絕緣。
舉例而言,可在第一基板100的第一表面101上形成電晶體作為電路元件。電晶體可包括位於第一基板100的第一表面101上的閘極結構及位於第一基板100的上部部分處的雜質區。
可穿過第一絕緣中介層110形成接觸插塞以接觸雜質區及/或閘極結構。
可部分地穿過第一基板100形成第一初步貫通孔電極140。
具體而言,可使用第一蝕刻遮罩對第一絕緣中介層110及第一基板100的上部部分進行蝕刻以形成第一溝渠,可在第一溝渠的內壁、第一絕緣中介層110及接觸插塞上形成第一絕緣層120,可在第一絕緣層120上形成第一導電層130以填充第一溝渠。可對第一導電層130及第一絕緣層120進行平坦化直至暴露出第一絕緣中介層110的上表面以形成包括第一絕緣層120及第一導電層130並填充第一溝渠的第一初步貫通孔電極140。第一初步貫通孔電極140可更包括位於第一導電層130與第一絕緣層120之間的第一障壁層。
可在第一絕緣中介層110、接觸插塞及第一初步貫通孔電極140上設置包含形成於其中的第一配線結構170的第二絕緣中介層150。
在示例性實施例中,第一配線結構170可包括至少一個第一配線165及連接至第一配線165或者將第一配線165與第一初步貫通孔電極140連接至彼此的至少一個第一通孔160。圖2示出依序堆疊於第一初步貫通孔電極140上的一個第一通孔160及一個第一配線165。然而,示例性實施例並非僅限於單個第一配線165及單個第一通孔160。
在示例性實施例中,第一配線165及第一通孔160可藉由雙鑲嵌製程或單鑲嵌製程形成。
可在第二絕緣中介層150上形成第一導電凸塊180以接觸第一配線165的上表面(或暴露出的表面)。
參照圖3,可在第二絕緣中介層150及第一配線165上形成第一黏附層190以覆蓋第一導電凸塊180,且可將第一操持基板200貼合至第一黏附層190。
可依序堆疊第一黏附層190及第一操持基板200以形成晶圓支撐系統(wafer support system WSS)。
可使用WSS使第一基板100上下翻轉以使第一基板100的第二表面102可如圖中所示面朝上,且可將第一基板100的與第二表面102相鄰的一部分移除以暴露出第一初步貫通孔電極140的上部部分。可藉由回蝕製程及/或研磨製程移除第一基板100的所述部分。
參照圖4,可在第一基板100的第二表面(即,頂表面)102以及第一初步貫通孔電極140的暴露出的部分上形成第一鈍化層210,且可對第一鈍化層210的上部部分進行平坦化直至暴露出第一初步貫通孔電極140的第一導電層130的上表面。
因此,可移除第一初步貫通孔電極140的第一導電層130上的第一絕緣層120的部分以形成第一絕緣圖案125,且可形成包括第一導電層130以及位於第一導電層130的側壁上的第一絕緣圖案125的第一貫通孔電極145。
在示例性實施例中,可藉由化學機械研磨(chemical mechanical polishing,CMP)製程及/或回蝕製程來執行平坦化製程。
在示例性實施例中,第一鈍化層210可包括依序堆疊的第一氧化物層、氮化物層及第二氧化物層。
參照圖5,可在第一鈍化層210上形成第一導電焊墊220以接觸暴露出的第一貫通孔電極145的上表面。
可在第一貫通孔電極145與第一導電焊墊220之間進一步形成重佈線層。
藉由上述製程,可形成基底晶圓250,基底晶圓250可由WSS支撐且可包括第一貫通孔電極145。
在示例性實施例中,第一貫通孔電極145可在實質上平行於第一基板100的第一表面101的水平方向上具有第一直徑D1,且在實質上垂直於第一基板100的第一表面101的垂直方向上具有第一長度L1。另外,基底晶圓250中的第一基板100可在垂直方向上具有第一厚度T1。
參照圖6,可執行與參照圖2至圖5所示製程實質上相同或相似的製程以形成第一半導體晶片455。
亦即,可在第二基板300的第一表面301上形成電路元件,且可在第二基板300的第一表面301上形成第三絕緣中介層310以覆蓋電路元件。可穿過第三絕緣中介層310形成接觸插塞以接觸雜質區及/或閘極結構。可部分地穿過第二基板300形成包括第二絕緣層及第二導電層330的第二初步貫通孔電極。
可在第三絕緣中介層310、接觸插塞及第二初步貫通孔電極上形成其中包含第二配線結構270的第四絕緣中介層350。第二配線結構370可包括至少一個第二配線365及至少一個第二通孔360。
可在第四絕緣中介層350上形成第二導電凸塊380以接觸第二配線365的上表面。可在第四絕緣中介層350及第二配線365上形成第二黏附層以覆蓋第二導電凸塊380,且可將第二操持基板貼合至第二黏附層。可使用第二操持基板使第二基板300上下翻轉以使第二基板300的第二表面302可面朝上,且可移除第二基板300的與第二表面302相鄰的上部部分以暴露出第二初步貫通孔電極的一部分。
可在第二基板300的第二表面302及第二初步貫通孔電極的被暴露出的部分上形成第二鈍化層410,且可對第二鈍化層410的上部部分進行平坦化直至可暴露出第二初步貫通孔電極的第二導電層330的上表面。因此,可移除第二初步貫通孔電極的第二導電層330上的第二絕緣層的部分以形成第二絕緣圖案325,且可形成包括第二導電層330及位於第二導電層330的側壁上的第二絕緣圖案325的第二貫通孔電極345。可在第二鈍化層410上形成第二導電焊墊420以接觸第二貫通孔電極345的上表面。
可在第二導電焊墊420及第二鈍化層410上形成膠布430,可使用膠布430將第二基板300翻轉以使第二基板300的第一表面301可面朝上,且可移除第二黏附層及第二操持基板以暴露出第二導電凸塊380及第四絕緣中介層350。
可在暴露出的第二導電凸塊380及第四絕緣中介層350上形成第三黏附層440。
藉由上述製程,可在膠布430上形成包括第二貫通孔電極345的堆疊晶圓450,且可藉由第三黏附層440覆蓋堆疊晶圓450的上表面。
在示例性實施例中,第二貫通孔電極345可在水平方向上具有小於第一貫通孔電極145的第一直徑D1的第二直徑D2,且因此就第二穿孔貫通孔電極345在電路圖案或配線的佈局中的放置而言可具有相對高的誤差裕度。
另外,第二貫通孔電極345的第二長度L2可小於第一貫通孔電極145的第一長度L1,且堆疊晶圓450中的第二基板300的第二厚度T2可小於基底晶圓250中的第一基板100的第一厚度T1。
然而,在示例性實施例中,第一長度L1相對於第一直徑D1的比率(即,第一長寬比)可實質上等於或大於第二長寬比(即,第二長度L2相對於第二直徑D2的比率)。因此,即使第二貫通孔電極345具有相對小的直徑,用於形成第二初步貫通孔電極的第二溝渠亦可被第二導電層330充分填充而其中不具有空隙,且第二貫通孔電極345的特性可不劣化。
在示例性實施例中,參照圖7,可藉由例如切割製程將堆疊晶圓450劃分成多個半導體晶片455,且可將所述多個第一半導體晶片455(圖7中的兩個第一半導體晶片455)安裝成使所述多個第一半導體晶片455中的每一者的第二導電凸塊380可接觸基底晶圓250的第一導電焊墊220的上表面。
在示例性實施例中,可藉由熱壓非導電膏(thermal compression non-conductive paste,TCNCP)製程將所述多個第一半導體晶片455結合至基底晶圓250上。亦即,可將所述多個第一半導體晶片455中的每一者的第二導電凸塊380放置成接觸基底晶圓250的各別第一導電焊墊220並且以適當的貼合溫度按壓以使第二導電凸塊380可貼合至第一導電焊墊220。另外,可在第一半導體晶片455與基底晶圓250之間形成第三黏附層440以有助於將第一半導體晶片455與基底晶圓250貼合至彼此。
當將第一半導體晶片455安裝至基底晶圓250上時,可移除膠布430。
參照圖8,可在初始的兩個第一半導體晶片455上分別堆疊另外的第一半導體晶片455,且可在第一半導體晶片455的最上部的一個第一半導體晶片455上堆疊第二半導體晶片555。
亦可藉由TCNCP製程將在垂直方向上堆疊的包括第一半導體晶片455中的最上部的一個第一半導體晶片455在內的所述多個第一半導體晶片455與第二半導體晶片555彼此結合。
圖8示出所述多個第一半導體晶片455分別以三個層階堆疊,且第二半導體晶片555在基底晶圓250上以一個層階形成,然而,示例性實施例可並非僅限於此。舉例而言,所述多個第一半導體晶片455可分別以七個層階堆疊,且第二半導體晶片555可以一個層階形成。
在示例性實施例中,與第一半導體晶片455不同,第二半導體晶片555可不包括任何設置於其中的貫通孔電極,且第二半導體晶片555中的第三基板500在垂直方向上的第三厚度T3可大於第一半導體晶片455中的每一者在垂直方向上的第二厚度T2。
參照圖9,可在基底晶圓250上形成模製元件600以覆蓋第一半導體晶片455及第二半導體晶片555。
返回參照圖1,自圖9所示實施例中看出,可移除模製元件600直至可暴露出第二半導體晶片555的上表面,且可移除基底晶圓250下方的包括WSS的第一操持基板200及第一黏附層190以形成晶圓上晶片(CoW)封裝。
可對CoW封裝執行各種電性測試,且在測試期間,CoW封裝可能由於例如翹曲而損壞。然而,在示例性實施例中,基底晶圓250中的第一基板100的第一厚度T1可大於可堆疊於基底晶圓250上的所述多個第一半導體晶片455中的每一者的第二厚度T2,且因此,可減少由於翹曲引起的CoW封裝的損壞。
另外,第一半導體晶片455中的每一者中的第二貫通孔電極345的第二直徑D2可小於基底晶圓250中的第一貫通孔電極145的第一直徑D1,且因此第一半導體晶片455中的每一者在電路圖案或配線的佈局方面可具有高自由度。
第二貫通孔電極345的第二長寬比可等於或小於第一貫通孔電極145的第一長寬比,且因此,即使第二貫通孔電極345具有相對小的直徑,第二貫通孔電極345的特徵亦可不劣化。
另外,第一半導體晶片455中的每一者中的第二基板300的第二厚度T2可小於基底晶圓250中的第一基板100的第一厚度T1,且因此可在基底晶圓250上堆疊更多的第一半導體晶片455,且包括第一半導體晶片455的CoW封裝可具有高容量及高效能。
圖10是示出根據示例性實施例的半導體封裝11的剖視圖,在半導體封裝11中半導體晶片的貫通孔電極的節距實質上等於基底晶圓的貫通孔電極的節距。
參照圖10,多個第一半導體晶片455可在基底晶圓250上在水平方向上設置成彼此間隔開,可將再兩個第一半導體晶片455在垂直方向上堆疊於第一半導體晶片455中的每一者上,且第二半導體晶片555可堆疊於第一半導體晶片455的最上部的一個第一半導體晶片455上。然而,在垂直方向上堆疊的第一半導體晶片455的數目可並非僅限於此。
在示例性實施例中,基底晶圓250的第一厚度T1可大於第一半導體晶片455中的每一者的第二厚度T2。另外,第二貫通孔電極345的第二直徑D2及第二長度L2可分別小於第一貫通孔電極145的第一直徑D1及第一長度L1。然而,第一貫通孔電極145的第一長寬比可等於或大於第二貫通孔電極345的第二長寬比。
第二貫通孔電極345之間的第二節距P2可實質上等於第一貫通孔電極145的第一節距P1。亦即,各別第二貫通孔電極345的中心之間的距離可實質上等於各別第一貫通孔電極145的中心之間的距離。
圖11是示出根據示例性實施例的半導體封裝12的剖視圖,在半導體封裝12中半導體晶片的貫通孔電極的節距不同於基底晶圓的貫通孔電極的節距。
參照圖11,相鄰的第二貫通孔電極345之間的第三節距P3可小於相鄰的第一貫通孔電極145的第一節距P1。
因此,可在同一區域中形成更多第二貫通孔電極345,且第一半導體晶片455中的每一者的積體度可增強。
然而,可在基底晶圓250與第一導電焊墊220之間另外形成重佈線層230以調整第一導電焊墊220的位置,且因此第一導電焊墊220可高效地連接至第一半導體晶片455的第二導電凸塊380。
重佈線層230可包括金屬、金屬氮化物、金屬矽化物等。
圖12是根據示例性實施例的半導體封裝13。
此半導體封裝13可為高頻寬記憶體(HBM)封裝,且可包括與參照圖1所示半導體封裝10的元件實質上相同或相似的元件。因此,本文中省略對相同元件的詳細說明。
參照圖12,半導體封裝可包括封裝基板900、中介層800、基底晶片255、多個第一半導體晶片455及第二半導體晶片555。半導體封裝13可更包括與在中介層800上與基底晶片255間隔開的處理器晶片700。
在所述圖中,示出一個基底晶片255以及依序堆疊於基底晶片255上的所述多個第一半導體晶片455及第二半導體晶片455,然而,示例性實施例可並非僅限於此。舉例而言,半導體封裝13可包括圍繞一個處理器晶片700的四個基底晶片255以及位於基底晶片255中的每一者上的所述多個第一半導體晶片455及第二半導體晶片555。
封裝基板900可包括例如印刷電路板(printed circuit board,PCB)。在封裝基板900下面可形成有外部連接端子980,且因此半導體封裝可藉由外部連接端子980安裝於模組基板或主板上。
在封裝基板900與中介層800之間可形成有第三導電凸塊880,在中介層800與基底晶片255之間可形成有第一導電凸塊180,且在中介層800與處理器晶片700之間可形成有第四導電凸塊780。另外,第二導電凸塊380可形成於基底晶片255與第一半導體晶片455之間,第一半導體晶片455之間,以及第一半導體晶片455與第二半導體晶片555之間。
在中介層800中可形成有第三配線810、第四配線820及第五配線830。第三配線810可將第一導電凸塊180中的一些第一導電凸塊180電性連接至第三導電凸塊880中的一些第三導電凸塊880,第四配線820可將第四導電凸塊780中的一些第四導電凸塊780電性連接至第三導電凸塊880中的一些第三導電凸塊880,且第五配線830可將第一導電凸塊180中的一些第一導電凸塊180電性連接至第四導電凸塊780中的一些第四導電凸塊780。
可藉由切割製程切割基底晶圓250來形成基底晶片255。因此,基底晶片255可包括第一基板100、第一貫通孔電極145、第一配線結構170、第一導電焊墊220及第一鈍化層210。
在示例性實施例中,基底晶片255可包括邏輯晶片或控制器晶片。作為另一選擇,基底晶片255可包括記憶體晶片,例如DRAM晶片。
所述多個第一半導體晶片455可以多個層階堆疊於基底晶片255上。第二半導體晶片555可堆疊於所述多個第一半導體晶片455中的最上部的一個第一半導體晶片455上。
第三黏附層440可形成於第一半導體晶片455與基底晶片255之間、第一半導體晶片455之間以及第一半導體晶片455與第二半導體晶片555之間。
在示例性實施例中,處理器晶片700可包括圖形處理單元(graphic processing unit,GPU)晶片或中央處理單元(central processing unit,CPU)晶片。
類似於參照圖1所示半導體封裝10,圖12中的半導體封裝13可具有高容量及高效能。
根據示例性實施例的半導體封裝可具有高容量及高效能,且更具有增強的可靠性。另外,根據示例性實施例的半導體封裝在電路圖案或配線的佈局方面可具有高自由度。
上述是對示例性實施例的說明且並非被視為對示例性實施例進行限制。儘管已闡述了幾個示例性實施例,然而熟習此項技術者應容易地理解,在示例性實施例中可存在諸多變型及修改而此並不實質上背離本揭露的新穎教示內容及優點。因此,所有該些潤飾皆預期被包括於申請專利範圍所界定的本揭露的範圍內。
10、11、12、13:半導體封裝
100:第一基板
101:第一表面/下表面/底表面
102、302:第二表面
110:第一絕緣中介層
120:第一絕緣層
125:第一絕緣圖案
130:第一導電層
140:第一初步貫通孔電極
145:第一貫通孔電極
150:第二絕緣中介層
160:第一通孔
165:第一配線
170:第一配線結構
180:第一導電凸塊
190:第一黏附層
200:第一操持基板
210:第一鈍化層
220:第一導電焊墊
230:重佈線層
250:基底晶圓
255:基底晶片
300:第二基板
301:第一表面
310:第三絕緣中介層
325:第二絕緣圖案
330:第二導電層
345:第二貫通孔電極
350:第四絕緣中介層
360:第二通孔
365:第二配線
370:第二配線結構
380:第二導電凸塊
410:第二鈍化層
420:第二導電焊墊
430:膠布
440:第三黏附層
450:堆疊晶圓
455:第一半導體晶片
500:第三基板
555:第二半導體晶片
600:模製元件
700:處理器晶片
780:第四導電凸塊
800:中介層
810:第三配線
820:第四配線
830:第五配線
880:第三導電凸塊
900:封裝基板
980:外部連接端子
D1:第一直徑
D2:第二直徑
L1:第一長度
L2:第二長度
P1:第一節距
P2:第二節距
P3:第三節距
T1:第一厚度
T2:第二厚度
T3:第三厚度
結合附圖閱讀以下詳細說明,將更清楚地理解以上及/或其他態樣,在附圖中:
圖1是示出根據示例性實施例的半導體封裝的剖視圖。
圖2至圖9是示出根據示例性實施例的製造圖1所示半導體封裝的方法的剖視圖。
圖10是示出根據示例性實施例的半導體封裝的剖視圖,在所述半導體封裝中,半導體晶片的貫通孔電極的節距實質上等於基底晶圓的貫通孔電極的節距。
圖11是示出根據示例性實施例的半導體封裝的剖視圖,在所述半導體封裝中,半導體晶片的貫通孔電極的節距與基底晶圓的貫通孔電極的節距不同。
圖12是根據示例性實施例的半導體封裝。
10:半導體封裝
100:第一基板
101:第一表面/下表面/底表面
102、302:第二表面
110:第一絕緣中介層
125:第一絕緣圖案
130:第一導電層
145:第一貫通孔電極
150:第二絕緣中介層
160:第一通孔
165:第一配線
170:第一配線結構
180:第一導電凸塊
190:第一黏附層
200:第一操持基板
210:第一鈍化層
220:第一導電焊墊
250:基底晶圓
300:第二基板
301:第一表面
310:第三絕緣中介層
325:第二絕緣圖案
330:第二導電層
345:第二貫通孔電極
350:第四絕緣中介層
360:第二通孔
365:第二配線
370:第二配線結構
380:第二導電凸塊
410:第二鈍化層
420:第二導電焊墊
440:第三黏附層
455:第一半導體晶片
500:第三基板
555:第二半導體晶片
600:模製元件
D1:第一直徑
D2:第二直徑
L1:第一長度
L2:第二長度
T1:第一厚度
T2:第二厚度
T3:第三厚度
Claims (25)
- 一種半導體封裝,包括: 基底晶圓,包括: 第一基板;以及 至少一個第一貫通孔電極,延伸穿過所述第一基板;以及 第一半導體晶片,設置於所述基底晶圓上,所述第一半導體晶片包括: 第二基板;以及 至少一個第二貫通孔電極,延伸穿過所述第二基板, 其中所述至少一個第二貫通孔電極設置於所述至少一個第一貫通孔電極上以電性連接至所述至少一個第一貫通孔電極,且 其中所述至少一個第一貫通孔電極在第一方向上的第一直徑大於所述至少一個第二貫通孔電極在所述第一方向上的第二直徑。
- 如申請專利範圍第1項所述的半導體封裝,其中所述第一基板在第二方向上的第一厚度大於所述第二基板在所述第二方向上的第二厚度,所述第二方向實質上垂直於所述第一方向。
- 如申請專利範圍第1項所述的半導體封裝,其中所述至少一個第一貫通孔電極在第二方向上的第一長度大於所述至少一個第二貫通孔電極在所述第二方向上的第二長度。
- 如申請專利範圍第1項所述的半導體封裝,其中所述至少一個第一貫通孔電極的第一長寬比實質上等於或大於所述至少一個第二貫通孔電極的第二長寬比。
- 一種半導體封裝,包括: 基底晶圓,包括: 第一基板;以及 第一貫通孔電極,延伸穿過所述第一基板;以及 半導體晶片,設置於所述基底晶圓上,所述半導體晶片包括: 第二基板;以及 第二貫通孔電極,延伸穿過所述第二基板, 其中所述第一貫通孔電極在第一方向上的第一直徑不同於所述第二貫通孔電極在所述第一方向上的第二直徑,且 其中所述第一貫通孔電極的第一長寬比等於或大於所述第二貫通孔電極的第二長寬比。
- 如申請專利範圍第5項所述的半導體封裝,更包括: 包括所述第一貫通孔電極在內的多個第一貫通孔電極,所述多個第一貫通孔電極在所述第一方向上彼此間隔開;以及 包括所述第二貫通孔電極在內的多個第二貫通孔電極,所述多個第二貫通孔電極在所述第一方向上彼此間隔開, 其中所述多個第一貫通孔電極的第一節距實質上等於所述多個第二貫通孔電極的第二節距。
- 如申請專利範圍第6項所述的半導體封裝,其中所述多個第二貫通孔電極分別設置於所述多個第一貫通孔電極上以電性連接至所述多個第一貫通孔電極。
- 如申請專利範圍第5項所述的半導體封裝,更包括:包括所述第一貫通孔電極在內的多個第一貫通孔電極,所述多個第一貫通孔電極在所述第一方向上彼此間隔開;以及 包括所述第二貫通孔電極在內的多個第二貫通孔電極,所述多個第二貫通孔電極在所述第一方向上彼此間隔開, 其中所述多個第一貫通孔電極的第一節距不同於所述多個第二貫通孔電極的第二節距。
- 如申請專利範圍第5項所述的半導體封裝,其中所述第一基板在第二方向上的第一厚度大於所述第二基板在所述第二方向上的第二厚度,所述第二方向實質上垂直於所述第一方向。
- 一種半導體封裝,包括: 封裝基板; 中介層,設置於所述封裝基板上; 基底晶片,包括: 第一基板;以及 至少一個第一貫通孔電極,延伸穿過所述第一基板; 第一半導體晶片,設置於所述基底晶片上,所述第一半導體晶片包括: 第二基板;以及 至少一個第二貫通孔電極,延伸穿過所述第二基板;以及 處理器晶片,設置於所述中介層上且在第一方向上與所述基底晶片間隔開, 其中所述至少一個第二貫通孔電極設置於所述至少一個第一貫通孔電極上以電性連接至所述至少一個貫通孔電極,且 其中所述至少一個第一貫通孔電極在所述第一方向上的第一直徑大於所述至少一個第二貫通孔電極在所述第一方向上的第二直徑。
- 如申請專利範圍第10項所述的半導體封裝,其中所述基底晶片包括圖形處理單元(GPU)晶片或中央處理單元(CPU)晶片。
- 如申請專利範圍第10項所述的半導體封裝,其中所述基底晶片包括邏輯裝置或控制器,且 其中所述第一半導體晶片包括記憶體裝置。
- 如申請專利範圍第10項所述的半導體封裝,其中所述中介層包括: 第一配線,將所述基底晶片與所述封裝基板電性連接至彼此; 第二配線,將所述處理器晶片與所述封裝基板電性連接至彼此;以及 第三配線,將所述基底晶片與所述處理器晶片電性連接至彼此。
- 如申請專利範圍第10項所述的半導體封裝,其中所述第一基板在第二方向上的第一厚度大於所述第二基板在所述第二方向上的第二厚度,所述第二方向實質上垂直於所述第一方向。
- 如申請專利範圍第10項所述的半導體封裝,其中所述至少一個第一貫通孔電極在第二方向上的第一長度大於所述至少一個第二貫通孔電極在所述第二方向上的第二長度,所述第二方向實質上垂直於所述第一方向。
- 如申請專利範圍第10項所述的半導體封裝,其中所述至少一個第一貫通孔電極的第一長寬比實質上等於或大於所述至少一個第二貫通孔電極的第二長寬比。
- 如申請專利範圍第10項所述的半導體封裝,其中所述至少一個第一貫通孔電極的第一節距實質上等於所述至少一個第二貫通孔電極的第二節距。
- 如申請專利範圍第10項所述的半導體封裝,更包括:包括所述第一半導體晶片在內的多個第一半導體晶片,所述多個第一半導體晶片在第二方向上堆疊,所述第二方向實質上垂直於所述第一方向。
- 如申請專利範圍第18項所述的半導體封裝,更包括第二半導體晶片,所述第二半導體晶片設置於所述多個第一半導體晶片中在所述第二方向上的最上第一半導體晶片上,所述第二半導體晶片包括第三基板。
- 如申請專利範圍第19項所述的半導體封裝,其中所述第三基板在所述第二方向上的第三厚度大於所述第二基板在所述第二方向上的第二厚度。
- 如申請專利範圍第10項所述的半導體封裝,更包括:包括所述第一半導體晶片在內的多個第一半導體晶片,所述多個第一半導體晶片在所述基底晶片上在所述第一方向上彼此間隔開。
- 一種半導體封裝,包括: 封裝基板; 中介層,設置於所述封裝基板上; 基底晶片,包括: 第一基板;以及 至少一個第一貫通孔電極,延伸穿過所述第一基板; 第一半導體晶片,設置於所述基底晶片上,所述第一半導體晶片包括: 第二基板;以及 至少一個第二貫通孔電極,延伸穿過所述第二基板;以及 處理器晶片,設置於所述中介層上且在第一方向上與所述基底晶片間隔開, 其中所述至少一個第一貫通孔電極在所述第一方向上的第一直徑不同於所述至少一個第二貫通孔電極在所述第一方向上的第二直徑,且 其中所述第一貫通孔電極的第一長寬比等於或大於所述第二貫通孔電極的第二長寬比。
- 如申請專利範圍第22項所述的半導體封裝,其中所述第一基板在第二方向上的第一厚度大於所述第二基板在所述第二方向上的第二厚度,所述第二方向實質上垂直於所述第一方向。
- 如申請專利範圍第22項所述的半導體封裝,其中所述至少一個第一貫通孔電極在第二方向上的第一長度大於所述至少一個第二貫通孔電極在所述第二方向上的第二長度,所述第二方向實質上垂直於所述第一方向。
- 如申請專利範圍第22項所述的半導體封裝,其中所述至少一個第一貫通孔電極的第一節距實質上等於所述至少一個第二貫通孔電極的第二節距。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2018-0135462 | 2018-11-06 | ||
KR1020180135462A KR102551751B1 (ko) | 2018-11-06 | 2018-11-06 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202018898A true TW202018898A (zh) | 2020-05-16 |
TWI805802B TWI805802B (zh) | 2023-06-21 |
Family
ID=67180534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108124032A TWI805802B (zh) | 2018-11-06 | 2019-07-09 | 半導體封裝 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11081425B2 (zh) |
EP (1) | EP3651197A1 (zh) |
KR (1) | KR102551751B1 (zh) |
CN (1) | CN111146191A (zh) |
TW (1) | TWI805802B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI753561B (zh) * | 2020-09-02 | 2022-01-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11600526B2 (en) * | 2020-01-22 | 2023-03-07 | iCometrue Company Ltd. | Chip package based on through-silicon-via connector and silicon interconnection bridge |
KR20220122155A (ko) * | 2021-02-26 | 2022-09-02 | 삼성전자주식회사 | 더미 칩을 포함하는 반도체 패키지 |
CN117650126A (zh) * | 2022-08-10 | 2024-03-05 | 长鑫存储技术有限公司 | 一种半导体封装结构及其制备方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4917225B2 (ja) | 2001-09-28 | 2012-04-18 | ローム株式会社 | 半導体装置 |
JP4507101B2 (ja) | 2005-06-30 | 2010-07-21 | エルピーダメモリ株式会社 | 半導体記憶装置及びその製造方法 |
US9219023B2 (en) * | 2010-01-19 | 2015-12-22 | Globalfoundries Inc. | 3D chip stack having encapsulated chip-in-chip |
KR101624972B1 (ko) | 2010-02-05 | 2016-05-31 | 삼성전자주식회사 | 서로 다른 두께의 반도체 칩들을 갖는 멀티 칩 패키지 및 관련된 장치 |
KR101683814B1 (ko) * | 2010-07-26 | 2016-12-08 | 삼성전자주식회사 | 관통 전극을 구비하는 반도체 장치 |
KR20120057693A (ko) | 2010-08-12 | 2012-06-07 | 삼성전자주식회사 | 적층 반도체 장치 및 적층 반도체 장치의 제조 방법 |
KR101719636B1 (ko) | 2011-01-28 | 2017-04-05 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US20140159231A1 (en) * | 2011-08-04 | 2014-06-12 | Sony Mobile Communications Ab | Semiconductor assembly |
JP5936968B2 (ja) * | 2011-09-22 | 2016-06-22 | 株式会社東芝 | 半導体装置とその製造方法 |
KR101906408B1 (ko) * | 2011-10-04 | 2018-10-11 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
US8963336B2 (en) * | 2012-08-03 | 2015-02-24 | Samsung Electronics Co., Ltd. | Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same |
US20150236003A1 (en) | 2012-09-14 | 2015-08-20 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
US9087821B2 (en) * | 2013-07-16 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
JP2015046569A (ja) * | 2013-07-31 | 2015-03-12 | マイクロン テクノロジー, インク. | 半導体装置の製造方法 |
KR20150066184A (ko) | 2013-12-06 | 2015-06-16 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
KR102411064B1 (ko) * | 2015-03-10 | 2022-06-21 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그의 제조방법 |
KR102650497B1 (ko) * | 2017-02-28 | 2024-03-25 | 에스케이하이닉스 주식회사 | 적층형 반도체 장치 |
-
2018
- 2018-11-06 KR KR1020180135462A patent/KR102551751B1/ko active IP Right Grant
-
2019
- 2019-07-03 EP EP19184105.5A patent/EP3651197A1/en active Pending
- 2019-07-08 US US16/505,040 patent/US11081425B2/en active Active
- 2019-07-09 TW TW108124032A patent/TWI805802B/zh active
- 2019-09-10 CN CN201910851819.1A patent/CN111146191A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI753561B (zh) * | 2020-09-02 | 2022-01-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
Also Published As
Publication number | Publication date |
---|---|
KR102551751B1 (ko) | 2023-07-05 |
US11081425B2 (en) | 2021-08-03 |
US20200144159A1 (en) | 2020-05-07 |
TWI805802B (zh) | 2023-06-21 |
KR20200052181A (ko) | 2020-05-14 |
CN111146191A (zh) | 2020-05-12 |
EP3651197A1 (en) | 2020-05-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI805802B (zh) | 半導體封裝 | |
US9099541B2 (en) | Method of manufacturing semiconductor device | |
CN111211102A (zh) | 半导体装置及半导体封装 | |
US20160351472A1 (en) | Integrated circuit device and method of manufacturing the same | |
US20170025384A1 (en) | Semiconductor chip and semiconductor package having the same | |
JP2009010311A (ja) | スルーシリコンビアスタックパッケージ及びその製造方法 | |
US11362069B2 (en) | Three-dimensional stacking structure and manufacturing method thereof | |
TWI812168B (zh) | 三維元件結構及其形成方法 | |
US11211351B2 (en) | Apparatuses including redistribution layers and related microelectronic devices | |
US20240021584A1 (en) | Methods of fabricating the same die stack structure and semiconductor structure | |
KR20200052536A (ko) | 관통 실리콘 비아를 포함하는 반도체 소자 및 그 제조 방법 | |
US20230133116A1 (en) | Semiconductor package having stacked semiconductor chips | |
TW202316599A (zh) | 半導體封裝 | |
TW202141689A (zh) | 具有通孔保護層的半導體裝置 | |
US20230140683A1 (en) | Dummy pattern structure for reducing dishing | |
US11081467B2 (en) | Apparatuses and methods for arranging through-silicon vias and pads in a semiconductor device | |
US20240055406A1 (en) | Semiconductor package and method of manufacturing the same | |
US20230074933A1 (en) | Semiconductor package | |
US20220278010A1 (en) | Semiconductor package including a dummy chip | |
US11935871B2 (en) | Semiconductor package and method of fabricating the same | |
US20230112006A1 (en) | Semiconductor package and method of manufacturing the same | |
US20240096851A1 (en) | Semiconductor package and method of manufacturing the same | |
TW202315033A (zh) | 半導體封裝 | |
KR20230129742A (ko) | 반도체 패키지 | |
KR20230059653A (ko) | 반도체 장치 제조 방법 |