CN111146191A - 半导体封装件 - Google Patents
半导体封装件 Download PDFInfo
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- CN111146191A CN111146191A CN201910851819.1A CN201910851819A CN111146191A CN 111146191 A CN111146191 A CN 111146191A CN 201910851819 A CN201910851819 A CN 201910851819A CN 111146191 A CN111146191 A CN 111146191A
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Abstract
一种半导体封装件包括:基础晶圆,其包括第一衬底和延伸穿过第一衬底的至少一个第一贯通过孔电极;以及第一半导体芯片,其设置在基础晶圆上。第一半导体芯片包括第二衬底;以及延伸穿过第二衬底的至少一个第二贯通过孔电极。所述至少一个第二贯通过孔电极设置在所述至少一个第一贯通过孔电极上,以电连接到所述至少一个第一贯通过孔电极。所述至少一个第一贯通过孔电极在第一方向上的第一直径大于所述至少一个第二贯通过孔电极在第一方向上的第二直径。
Description
相关申请的交叉引用
本申请要求于2018年11月6日在韩国知识产权局提交的韩国专利申请No.10-2018-0135462的优先权,其公开内容通过引用整体并入本文。
技术领域
示例实施例涉及半导体封装件,并且更具体地,涉及包括贯通过孔电极的半导体封装件。
背景技术
在半导体封装件中,高带宽存储器(HBM)可通过晶圆上芯片(CoW)工艺堆叠在晶圆上。另外,可在晶圆上形成穿硅过孔(TSV),其是穿过晶圆的电连接。随着TSV的尺寸和晶圆的厚度变小而仍需要确保高速和高容量,在CoW工艺之后的后续工艺中晶圆可能更容易被翘曲损坏。
发明内容
一个或多个示例实施例提供了具有高可靠性的半导体封装件。
根据示例实施例的一方面,提供了一种半导体封装件。半导体封装件可包括:基础晶圆,其包括第一衬底和延伸穿过第一衬底的至少一个第一贯通过孔电极;以及第一半导体芯片,其设置在基础晶圆上。第一半导体芯片包括:第二衬底;以及延伸穿过第二衬底的至少一个第二贯通过孔电极。所述至少一个第二贯通过孔电极设置在所述至少一个第一贯通过孔电极上,以电连接到所述至少一个第一贯通过孔电极。所述至少一个第一贯通过孔电极在第一方向上的第一直径大于所述至少一个第二贯通过孔电极在第一方向上的第二直径。
根据另一示例实施例的一方面,提供了一种半导体封装件。半导体封装件可包括:基础晶圆,其包括第一衬底和延伸穿过第一衬底的第一贯通过孔电极;以及半导体芯片,其设置在基础晶圆上,并且包括第二衬底和延伸穿过第二衬底的第二贯通过孔电极。第一贯通过孔电极在第一方向上的第一直径与第二贯通过孔电极在第一方向上的第二直径不同。第一贯通过孔电极的第一纵横比等于或大于第二贯通过孔电极的第二纵横比。
根据另一示例实施例的一方面,提供了一种半导体封装件。半导体封装件可包括:封装衬底;中介层,其设置在封装衬底上;基础芯片,其包括第一衬底和延伸穿过第一衬底的至少一个第一贯通过孔电极;第一半导体芯片,其设置在基础芯片上,并且包括第二衬底和延伸穿过第二衬底的至少一个第二贯通过孔电极;以及处理器芯片,其设置在中介层上并且在第一方向上与基础芯片间隔开。所述至少一个第二贯通过孔电极设置在所述至少一个第一贯通过孔电极上,以电连接到所述至少一个第一贯通过孔电极。所述至少一个第一贯通过孔电极在第一方向上的第一直径大于所述至少一个第二贯通过孔电极在第一方向上的第二直径。
附图说明
通过以下结合附图的详细描述,将更清楚地理解以上和/或其他方面,附图中:
图1是示出根据示例实施例的半导体封装件的截面图;
图2至图9是示出根据示例实施例的制造图1的半导体封装件的方法的截面图;
图10是示出根据示例实施例的其中半导体芯片的贯通过孔电极的间距实质上等于基础晶圆的贯通过孔电极的间距的半导体封装件的截面图。
图11是示出根据示例实施例的其中半导体芯片的贯通过孔电极的间距与基础晶圆的贯通过孔电极的间距不同的半导体封装件的截面图;和
图12是根据示例实施例的半导体封装件。
具体实施方式
图1是示出根据示例实施例的半导体封装件10的截面图。
参考图1,半导体封装件10可包括顺序堆叠在基础晶圆250上的多个第一半导体芯片455和第二半导体芯片555。多个第一半导体芯片455和第二半导体芯片555的侧壁可由基础晶圆250上的模制元件600覆盖。
基础晶圆250可包括向下顺序地堆叠在第一衬底100的下表面(或第一表面101)上的第一绝缘中间层110、第二绝缘中间层150和第一导电凸块180。即,参考图1,第一绝缘中间层110堆叠在第一衬底100的下表面101下方,第二绝缘中间层150堆叠在第一绝缘中间层110下方,并且第一导电凸块180堆叠在第二绝缘中间层150下方。基础晶圆250还可包括延伸穿过第一衬底100和第一绝缘中间层110的第一贯通过孔电极145、设置在第二绝缘中间层150中的第一布线结构170、设置在第一衬底100的顶表面(或第二表面102)上并且还覆盖第一贯通过孔电极145的上侧壁的第一钝化层210、以及设置在第一钝化层210上并且接触第一贯通过孔电极145的上表面的第一导电焊盘220。
第一衬底100可包括硅(Si)、锗(Ge)、硅锗(SiGe)、或III-V族化合物,例如磷化镓(GaP)、砷化镓(GaAs)、锑化镓(GaSb)等。在一些示例实施例中,第一衬底100可为绝缘体上硅(SOI)衬底、或绝缘体上锗(GeOI)衬底。
第一衬底100可具有第一表面(例如,底表面)101和与第一表面101相对的第二表面(例如,顶表面)102,并且第一表面101和第二表面102之间的距离(即,第一衬底100在实质上垂直于第一表面101的竖直方向上的厚度)可为第一厚度T1。
在示例实施例中,电路元件可形成在第一衬底100的第一表面101下方,第一表面101可被第一绝缘中间层110覆盖。即,电路元件可设置在第一衬底100和第一绝缘中间层110之间。例如,可在第一衬底100和第一绝缘中间层110之间形成作为电路元件的晶体管。晶体管可包括在第一衬底100的第一表面101下方的栅结构和在第一衬底100的与栅结构相邻的下部处的杂质区域。然而,实施例不限于此,并且例如,可形成二极管、电阻器、电感器、电容器等作为第一衬底100和第一绝缘中间层110之间的电路元件。
第一绝缘中间层110可包括氧化物(O2-),例如氧化硅(SiO2)。可穿过第一绝缘中间层110形成接触插塞,以接触上述杂质区域和/或栅结构。接触插塞可包括金属、金属氮化物、金属硅化物等。
第一贯通过孔电极145可延伸穿过第一衬底100和第一绝缘中间层110二者以从第一衬底100的第二表面102向外突出(如图1所示向上突出)。在示例实施例中,第一贯通过孔电极145可包括第一导电层130和设置在第一导电层130的外侧壁上的第一绝缘图案125,并且还可包括设置在第一导电层130和第一绝缘图案125之间的第一阻挡图案。
第一绝缘图案125可包括氧化物(O2-),例如氧化硅(SiO2),第一导电层130可包括金属,例如钨(W)、铜(Cu)、铝(Al)等,并且第一阻挡图案可包括金属氮化物,例如氮化钛(TiN)、氮化钽(TaN)等。
在示例实施例中,第一贯通过孔电极145可在水平方向(在图1中;即,实质上平行于第一衬底100的第一表面101)上具有第一直径D1,并且在竖直方向(即,实质上垂直于第一表面101的方向)上具有第一长度L1。
作为示例实施例,图1示出了彼此间隔开的六个第一贯通过孔电极145,然而,示例实施例可不限于此,并且可在半导体封装件10中形成任意数量的多个第一贯通过孔电极145。
第二绝缘中间层150可包括例如掺杂有氟(F)或碳(C)的氧化硅(SiO2)、多孔SiO2、旋涂有机聚合物、或无机聚合物,例如氢倍半硅氧烷(HSSQ)、甲基倍半硅氧烷(MSSQ)等。
在示例实施例中,第一布线结构170可包括设置在第二绝缘中间层150中的至少一个第一布线165、和连接到第一布线165或者将第一布线165和第一贯通过孔电极145彼此连接的至少一个第一过孔160。图1示出了顺序堆叠在第一贯通过孔电极145的下表面下方的一个第一过孔160和一个第一布线165。第一布线165和第一过孔160中的每一个可包括金属、金属氮化物、金属硅化物等。
第一导电凸块180可形成在第二绝缘中间层150下方以接触第一布线165的下表面。第一导电凸块180可包括金属(例如银(Ag)、铜(Cu)等)或合金,并且可形成为焊料。
第一钝化层210可形成在第一衬底100的第二表面(即,顶表面)102上,并且可覆盖第一贯通过孔电极145的侧壁的上部。第一钝化层210可包括氧化物和/或氮化物。在示例实施例中,第一钝化层210可包括多个不同的层,包括顺序堆叠的第一氧化物层、氮化物层和第二氧化物层。
第一导电焊盘220可形成在第一钝化层210上以接触第一贯通过孔电极145的上表面。第一导电焊盘220可包括金属、金属氮化物、金属硅化物等。
此外,可在第一贯通过孔电极145和第一导电焊盘220之间进一步形成再分布层。
在示例实施例中,基础晶圆250可包括逻辑器件或控制器。或者,基础晶圆250可包括存储器件,例如动态随机存取存储器(DRAM)器件。
除了第一半导体芯片455包括第二衬底300和第二贯通过孔电极345而不是第一衬底100和第一贯通过孔电极145之外,第一半导体芯片455的结构可与基础晶圆250的结构实质上相同或相似。
更详细地,类似于上述基础晶圆250,第一半导体芯片455可包括向下顺序地堆叠在第二衬底300的下表面下方的第三绝缘中间层310、第四绝缘中间层350和第二导电凸块380。除了上述延伸穿过第二衬底300和第三绝缘中间层310的第二贯通过孔电极345之外,第一半导体芯片455还可包括设置在第四绝缘中间层350中的第二布线结构370、设置在第二衬底300上并且覆盖第二贯通过孔电极345的侧壁的上部的第二钝化层410、以及设置在第二钝化层410上并且接触第二贯通过孔电极345的上表面的第二导电焊盘420。
第二衬底300可具有第一表面(即,下表面)301和与第一表面301相对的第二表面(即,上/顶表面)302,并且第一表面301和第二表面302之间的距离(即,第二衬底300在竖直方向上(即,在与第一表面301和第二表面302的延伸方向垂直的方向上)的厚度)可为第二厚度T2。在示例实施例中,第二厚度T2可小于第一厚度T1。
在示例实施例中,电路元件可形成在第二衬底300的第一表面301下方,第一表面301可被第三绝缘中间层310覆盖。即,电路元件可形成在第二衬底300和第三绝缘中间层310之间。另外,可穿过第三绝缘中间层310形成接触插塞。
第一贯通过孔电极345可延伸穿过第二衬底300和第三绝缘中间层310以从第二衬底300的第二表面(即,顶表面)302突出。在示例实施例中,第二贯通过孔电极345可包括第二导电层330和设置在第二导电层330的外侧壁上的第二绝缘图案325,并且还可包括在第二导电层330和第二绝缘图案325之间的第二阻挡图案。
第一贯通过孔电极345可在水平方向上具有第二直径D2并且在竖直方向上具有第二长度L2。在示例实施例中,第二贯通过孔电极345的第二直径D2可小于第一贯通过孔电极145的第一直径D1,并且第二贯通过孔电极345的第二长度L2可小于第一贯通过孔电极145的第一长度L1。
然而,第一长度L1相对于第一直径D1的比率(例如,第一纵横比)可实质上等于或大于第二长度L2相对于第二直径D2的比率(例如,第二纵横比)。
在图1所示的示例实施例中,半导体封装件10包括彼此间隔开的六个第二贯通过孔电极345,然而,示例实施例可不限于此,并且可形成任何数量的多个第二贯通过孔电极345。
在示例实施例中,第二布线结构370可包括设置在第四绝缘中间层350中的至少一个第二布线365、和连接到第二布线365或将第二布线365和第二贯通过孔电极345彼此连接的至少一个第二过孔360。
在示例实施例中,一个或多个第一半导体芯片455可在竖直方向上堆叠在基础晶圆250上。图1示出了堆叠在基础晶圆250上的三个第一半导体芯片455,然而,示例实施例可不限于此。例如,第一半导体芯片455可以七个层级堆叠。
在示例实施例中,第一半导体芯片455可为存储器芯片,例如DRAM芯片。
另外,多个第一半导体芯片455可在水平方向上彼此间隔开。
第二半导体芯片555可堆叠在堆叠的第一半导体芯片455中的最上面的一个上,或者堆叠在第一半导体芯片455中的一个上。在示例实施例中,第二半导体芯片555可不同于第一半导体芯片455而不包括任何贯通过孔电极,并且第二半导体芯片555中的第三衬底500可在竖直方向上具有第三厚度T3。第三衬底500的第三厚度T3可大于第一半导体芯片455中的第二衬底300的第二厚度T2。
在示例实施例中,第二半导体芯片555可为存储器芯片,例如DRAM芯片。
在示例实施例中,第三粘附层440可形成在基础晶圆250和多个第一半导体芯片455中的最下面的一个之间、在竖直方向上堆叠的两个相邻的第一半导体芯片445之间、以及多个第一半导体芯片455中的最上面的一个和第二半导体芯片555之间。可通过第二导电焊盘420及第二导电凸块380将多个第一半导体芯片455和第二半导体芯片555彼此电连接。
在示例实施例中,模制元件600可包括环氧树脂模塑料(EMC)。
在示例实施例中,在半导体封装件10中,基础晶圆250中的第一衬底100的第一厚度T1可大于堆叠在第一衬底100上的多个第一半导体芯片455中的每一个中的第二衬底300的第二厚度T2,因此,可减小由于潜在翘曲导致的半导体封装件10的损坏。因此,半导体封装件10可以以增强的可靠性和更少的废料和返工来制造。
设置在多个第一半导体芯片455中的每一个中的第二贯通过孔电极345的第二直径D2可小于设置在基础晶圆250中的第一贯通过孔电极145的第一直径D1,因此第一半导体芯片455相对于它们在电路图案或布线的布局中的定位可具有增加的误差裕度。
另外,在示例实施例中,第二贯通过孔电极345的第二纵横比可实质上等于或小于第一贯通过孔电极145的第一纵横比,因此,即使第二贯通过孔电极345具有相对小的直径,第二贯通过孔电极345的特性可通过相应地减小其竖直长度而不会劣化。
此外,每个第一半导体芯片455中的第二衬底300的第二厚度T2可小于基础晶圆250中的第一衬底100的第一厚度T1,因此更多数量的第一半导体芯片455可堆叠在基础晶圆250上,并且半导体封装件10可具有增加的容量以及增强的性能。
图2至图9是示出根据示例实施例的制造图1的半导体封装件10的方法的截面图。
参考图2,电路元件可形成在第一衬底100的第一表面101(即,图1中示出的底表面101)上,并且第一绝缘中间层110可形成在第一衬底100的第一表面101上以覆盖/绝缘电路元件。
例如,晶体管可形成在第一衬底100的第一表面101上作为电路元件。晶体管可包括在第一衬底100的第一表面101上的栅结构和在第一衬底100的上部处的杂质区域。
可穿过第一绝缘中间层110形成接触插塞以接触杂质区域和/或栅结构。
可部分地穿过第一衬底100形成第一初级贯通过孔电极140。
具体地,可使用第一蚀刻掩模蚀刻第一绝缘中间层110和第一衬底100的上部以形成第一沟槽,可在第一沟槽、第一绝缘中间层110和接触插塞的内壁上形成第一绝缘层120,可在第一绝缘层120上形成第一导电层130以填充第一沟槽。可平坦化第一导电层130和第一绝缘层120,直到暴露第一绝缘中间层110的上表面以形成包括第一绝缘层120和第一导电层130并填充第一沟槽的第一初级贯通过孔电极140。第一初级贯通过孔电极140还可包括在第一导电层130和第一绝缘层120之间的第一阻挡层。
包含形成在其中的第一布线结构170的第二绝缘中间层150可设置在第一绝缘中间层110、接触插塞和第一初级贯通过孔电极140上。
在示例实施例中,第一布线结构170可包括至少一个第一布线165和至少一个第一过孔160,该至少一个第一过孔160连接到第一布线165或者将第一布线165和第一初级贯通过孔电极140彼此连接。图2示出了顺序堆叠在第一初级贯通过孔电极140上的一个第一过孔160和一个第一布线165。然而,示例实施例不限于单个第一布线165和单个第一过孔160。
在示例实施例中,第一布线165和第一过孔160可通过双镶嵌工艺或单镶嵌工艺形成。
可在第二绝缘中间层150上形成第一导电凸块180,以接触第一布线165的上表面(或暴露表面)。
参考图3,可在第二绝缘中间层150和第一布线165上形成第一粘附层190以覆盖第一导电凸块180,并且可将第一处理衬底200附接到第一粘附层190上。
可顺序堆叠第一粘附层190和第一处理衬底200以形成晶圆支撑系统(WSS)。
可使用WSS使第一衬底100上下颠倒,使得第一衬底100的第二表面102可面向上,如图中所示,并且可去除第一衬底100的与第二表面102相邻的部分以暴露第一初级贯通过孔电极140的上部。可通过回蚀工艺和/或研磨工艺去除第一衬底100的所述部分。
参考图4,可在第一衬底100的第二表面(即,顶表面)102和第一初级贯通过孔电极140的暴露部分上形成第一钝化层210,并且可平坦化第一钝化层210的上部,直到暴露第一初级贯通过孔电极140的第一导电层130的上表面。
因此,可去除第一绝缘层120的在第一初始贯通过孔电极140的第一导电层130上的部分以形成第一绝缘图案125,并且可形成包括第一导电层130和在第一导电层130的侧壁上的第一绝缘图案125的第一贯通过孔电极145。
在示例实施例中,可通过化学机械抛光(CMP)工艺和/或回蚀工艺来执行平坦化工艺。
在示例实施例中,第一钝化层210可包括顺序堆叠的第一氧化物层、氮化物层和第二氧化物层。
参考图5,可在第一钝化层210上形成第一导电焊盘220,以接触暴露的第一贯通过孔电极145的上表面。
可在第一贯通过孔电极145和第一导电焊盘220之间进一步形成再分布层。
通过上述工艺,可形成可由WSS支撑并且可包括第一贯通过孔电极145的基础晶圆250。
在示例实施例中,第一贯通过孔电极145可在实质上平行于第一衬底100的第一表面101的水平方向上具有第一直径D1,并且在与第一衬底100的第一表面101实质上垂直的竖直方向上具有第一长度L1。另外,基础晶圆250中的第一衬底100可在竖直方向上具有第一厚度T1。
参考图6,可执行与参考图2至图5所示的处理实质上相同或相似的处理,以形成第一半导体芯片455。
也就是说,可在第二衬底300的第一表面301上形成电路元件,并且可在第二衬底300的第一表面301上形成第三绝缘中间层310以覆盖电路元件。可穿过第三绝缘中间层310形成接触插塞以接触杂质区域和/或栅结构。可部分地穿过第二衬底300形成包括第二绝缘层和第二导电层330的第二初级贯通过孔电极。
可在第三绝缘中间层310、接触插塞和第二初级贯通过孔电极上形成其中包含第二布线结构370的第四绝缘中间层350。第二布线结构370可包括至少一个第二布线365和至少一个第二过孔360。
可在第四绝缘中间层350上形成第二导电凸块380以接触第二布线365的上表面。可在第四绝缘中间层350和第二布线365上形成第二粘附层以覆盖第二导电凸块380,并且第二处理衬底可附接到第二粘附层。可使用第二处理衬底使第二衬底300上下颠倒,使得第二衬底300的第二表面302可面向上,并且可去除第二衬底300的与第二表面302相邻的上部以暴露第二初级贯通过孔电极的一部分。
可在第二衬底300的第二表面302和第二初级贯通过孔电极的暴露部分上形成第二钝化层410,并且可将第二钝化层410的上部平坦化直到可暴露第二初级贯通过孔电极的第二导电层330的上表面。因此,可去除第二绝缘层的在第二初级贯通过孔电极的第二导电层330上的部分以形成第二绝缘图案325,并且可形成包括第二导电层330和在第二导电层330的侧壁上的第二绝缘图案325的第二贯通过孔电极345。可在第二钝化层410上形成第二导电焊盘420,以接触第二贯通过孔电极345的上表面。
可在第二导电焊盘420和第二钝化层410上形成带430,可使用带430翻转第二衬底300,使得第二衬底300的第一表面301可面向上,并且可去除第二粘附层和第二处理衬底以暴露第二导电凸块380和第四绝缘中间层350。
可在暴露的第二导电凸块380和第四绝缘中间层350上形成第三粘附层440。
通过上述工艺,可在带430上形成包括第二贯通过孔电极345的堆叠晶圆450,并且可通过第三粘附层440覆盖堆叠晶圆450的上表面。
在示例实施例中,第二贯通过孔电极345在水平方向上的第二直径D2可小于第一贯通过孔电极145的第一直径D1,因此相对于它们在电路图案或布线布局中的定位可具有相对高的误差裕度。
另外,第二贯通过孔电极345的第二长度L2可小于第一贯通过孔电极145的第一长度L1,并且堆叠晶圆450中的第二衬底300的第二厚度T2可小于基础晶圆250中的第一衬底100的第一厚度T1。
然而,在示例实施例中,第一长度L1相对于第一直径D1的比率(即,第一纵横比)可实质上等于或大于第二纵横比,即,第二长度L2相对于第二直径D2的比率。因此,即使第二贯通过孔电极345具有相对小的直径,用于形成第二初级贯通过孔电极的第二沟槽也可用第二导电层330充分填充而其中没有空隙,并且第二贯通过孔电极345的特性可不会劣化。
在示例实施例中,参考图7,可通过例如切割工艺将堆叠晶圆450划分为多个第一半导体芯片455,并且可安装多个第一半导体芯片455(图7中的两个第一半导体芯片455),使得多个第一半导体芯片455中的每一个的第二导电凸块380可接触基础晶圆250的第一导电焊盘220的上表面。
在示例实施例中,可通过热压非导电膏(TCNCP)工艺将多个第一半导体芯片455接合到基础晶圆250上。也就是说,多个第一半导体芯片455中的每一个的第二导电凸块380可被放置为接触基础晶圆250的相应第一导电焊盘220并且以适当的附接温度按压,使得第二导电凸块380可附接到第一导电焊盘220上。另外,第三粘附层440可形成在第一半导体芯片455和基础晶圆250之间,以便有助于将第一半导体芯片455和基础晶圆250彼此附接。
当将第一半导体芯片455安装到基础晶圆250上时,可去除带430。
参考图8,另外的第一半导体芯片455可进一步分别堆叠在初始的两个第一半导体芯片455上,并且第二半导体芯片555可堆叠在第一半导体芯片455的最上面的一个上。
包括在竖直方向上堆叠的多个第一半导体芯片455(包括第一半导体芯片455的最上面的一个)和第二半导体芯片555也可通过TCNCP工艺彼此接合。
图8示出了分别以三个层级堆叠多个第一半导体芯片455,并且在基础晶圆250上以一个层级形成第二半导体芯片555,然而,示例实施例可不限于此。例如,多个第一半导体芯片455可分别以七个层级堆叠,并且可以一个层级形成第二半导体芯片555。
在示例实施例中,与第一半导体芯片455不同,第二半导体芯片555可不包括设置在其中的任何贯通过孔电极,并且第二半导体芯片555中的第三衬底500的在竖直方向上的第三厚度T3可大于第一半导体芯片455中的每一个中的第二衬底300的在竖直方向上的第二厚度T2。
参考图9,可在基础晶圆250上形成模制元件600,以覆盖第一半导体芯片455和第二半导体芯片555。
返回参考图1,从图9中所示的实施例,可去除模制元件600,直到可暴露第二半导体芯片555的上表面,并且可去除包括基础晶圆250下方的WSS的第一粘附层190和第一处理衬底200以形成晶圆上芯片(CoW)封装件。
可对CoW封装件执行各种电测试,并且在测试期间,CoW封装件可能由于例如翘曲而损坏。然而,在示例实施例中,基础晶圆250中的第一衬底100的第一厚度T1可大于可堆叠在基础晶圆250上的多个第一半导体芯片455中的每一个的第二厚度T2,因此,可减少由于翘曲引起的CoW封装件的损坏。
另外,每个第一半导体芯片455中的第二贯通过孔电极345的第二直径D2可小于基础晶圆250中的第一贯通过孔电极145的第一直径D1,因此每个第一半导体芯片455可具有电路图案或布线的布局的高自由度。
第二贯通过孔电极345的第二纵横比可等于或小于第一贯通过孔电极145的第一纵横比,因此,即使第二贯通过孔电极345具有相对小的直径,其特征可能不会劣化。
此外,每个第一半导体芯片455中的第二衬底300的第二厚度T2可小于基础晶圆250中的第一衬底100的第一厚度T1,因此可在基础晶圆250上堆叠更多的第一半导体芯片455,并且包括第一半导体芯片455的CoW封装件可具有高容量和高性能。
图10是示出根据示例实施例的其中半导体芯片的贯通过孔电极的间距实质上等于基础晶圆的贯通过孔电极的间距的半导体封装件11的截面图。
参考图10,多个第一半导体芯片455可在水平方向上设置为在基础晶圆250上彼此间隔开,另外两个第一半导体芯片455可在竖直方向上堆叠在第一半导体芯片455的每一个上,并且第二半导体芯片555可堆叠在第一半导体芯片455的最上面的一个上。然而,在竖直方向上堆叠的第一半导体芯片455的数量可不限于此。
在示例实施例中,基础晶圆250的第一厚度T1可大于第一半导体芯片455中的每一个的第二厚度T2。另外,第二贯通过孔电极345的第二直径D2和第二长度L2可分别小于第一贯通过孔电极145的第一直径D1和第一长度L1。然而,第一贯通过孔电极145的第一纵横比可等于或大于第二贯通过孔电极345的第二纵横比。
第二贯通过孔电极345之间的第二间距P2可实质上等于第一贯通过孔电极145的第一间距P1。也就是说,相应的第二贯通过孔电极345的中心之间的距离可实质上等于相应的第一贯通过孔电极145的中心之间的距离。
图11是示出根据示例实施例的其中半导体芯片的贯通过孔电极的间距与基础晶圆的贯通过孔电极的间距不同的半导体封装件12的截面图。
参考图11,相邻的第二贯通过孔电极345之间的第三间距P3可小于相邻的第一贯通过孔电极145的第一间距P1。
因此,可在同一区域中形成更多的第二贯通过孔电极345,并且可增强每个第一半导体芯片455的集成度。
然而,可在基础晶圆250和第一导电焊盘220之间另外形成再分布层230,以便调整第一导电焊盘220的位置,因此第一导电焊盘220可有效地连接到第一半导体芯片455的第二导电凸块380。
再分布层230可包括金属、金属氮化物、金属硅化物等。
图12是根据示例实施例的半导体封装件13。
半导体封装件13可为高带宽存储器(HBM)封装件,并且可包括与参考图1所示的半导体封装件10的元件实质上相同或相似的元件。因此,对相同元件的详细描述在此省略。
参考图12,半导体封装件可包括封装衬底900、中介层800、基础芯片255、多个第一半导体芯片455和第二半导体芯片555。半导体封装件13还可包括与中介层800上的基础芯片255间隔开的处理器芯片700。
在该图中,示出了一个基础芯片255和顺序堆叠在基础芯片255上的多个第一半导体芯片455和第二半导体芯片555,然而,示例实施例可不限于此。例如,半导体封装件13可包括围绕一个处理器芯片700的四个基础芯片255、以及每个基础芯片255上的多个第一半导体芯片455和第二半导体芯片555。
封装衬底900可包括例如印刷电路板(PCB)。外部连接端子980可形成在封装衬底900下方,因此半导体封装件可通过外部连接端子980安装在模块衬底或主板上。
可在封装衬底900和中介层800之间形成第三导电凸块880,可在中介层800和基础芯片255之间形成第一导电凸块180,并且可在中介层800和处理器芯片700之间形成第四导电凸块780。另外,可在基础芯片255和第一半导体芯片455之间、第一半导体芯片455之间、以及第一半导体芯片455和第二半导体芯片555之间形成第二导电凸块380。
可在中介层800中形成第三布线810、第四布线820和第五布线830。第三布线810可将第一导电凸块180中的一些电连接到第三导电凸块880中的一些,第四布线820可将第四导电凸块780中的一些电连接到第三导电凸块880中的一些,并且第五布线830可将第一导电凸块180中的一些电连接到第四导电凸块780中的一些。
可通过切割工艺切割基础晶圆250来形成基础芯片255。因此,基础芯片255可包括第一衬底100、第一贯通过孔电极145、第一布线结构170、第一导电焊盘220和第一钝化层210。
在示例实施例中,基础芯片255可包括逻辑芯片或控制器芯片。或者,基础芯片255可包括存储器芯片,例如DRAM芯片。
多个第一半导体芯片455可以以多个层级堆叠在基础芯片255上。第二半导体芯片555可堆叠在多个第一半导体芯片455中的最上面的一个上。
第三粘附层440可形成在第一半导体芯片455和基础芯片255之间、第一半导体芯片455之间、以及第一半导体芯片455和第二半导体芯片555之间。
在示例实施例中,处理器芯片700可包括图形处理单元(GPU)芯片或中央处理单元(CPU)芯片。
与参考图1所示的半导体封装件10类似,图12中的半导体封装件13可具有高容量和高性能。
根据示例实施例的半导体封装件可具有高容量和高性能,并且还提高了可靠性。此外,根据示例实施例的半导体封装件可具有电路图案或布线的布局的高自由度。
前述内容是对示例实施例的说明,而不应解释为对其进行限制。尽管已经描述了一些示例实施例,但是本领域技术人员将容易理解,在示例实施例中可进行许多变化和修改而不实质上脱离本公开的新颖教导和优点。因此,所有这些修改旨在包括在权利要求中限定的本公开的范围内。
Claims (25)
1.一种半导体封装件,包括:
基础晶圆,其包括:
第一衬底;和
至少一个第一贯通过孔电极,其延伸穿过所述第一衬底;和
第一半导体芯片,其设置在所述基础晶圆上,所述第一半导体芯片包括:
第二衬底;和
至少一个第二贯通过孔电极,其延伸穿过所述第二衬底,其中,所述至少一个第二贯通过孔电极设置在所述至少一个第一贯通过孔电极上,以电连接到所述至少一个第一贯通过孔电极,并且
其中,所述至少一个第一贯通过孔电极在第一方向上的第一直径大于所述至少一个第二贯通过孔电极在所述第一方向上的第二直径。
2.根据权利要求1所述的半导体封装件,其中,所述第一衬底在实质上垂直于所述第一方向的第二方向上的第一厚度大于所述第二衬底在所述第二方向上的第二厚度。
3.根据权利要求1所述的半导体封装件,其中,所述至少一个第一贯通过孔电极在第二方向上的第一长度大于所述至少一个第二贯通过孔电极在所述第二方向上的第二长度。
4.根据权利要求1所述的半导体封装件,其中,所述至少一个第一贯通过孔电极的第一纵横比实质上等于或大于所述至少一个第二贯通过孔电极的第二纵横比。
5.一种半导体封装件,包括:
基础晶圆,其包括:
第一衬底;和
第一贯通过孔电极,其延伸穿过所述第一衬底;和
半导体芯片,其设置在所述基础晶圆上,所述半导体芯片包括:
第二衬底;和
第二贯通过孔电极,其延伸穿过所述第二衬底,
其中,所述第一贯通过孔电极在第一方向上的第一直径与所述第二贯通过孔电极在所述第一方向上的第二直径不同,并且
其中,所述第一贯通过孔电极的第一纵横比等于或大于所述第二贯通过孔电极的第二纵横比。
6.根据权利要求5所述的半导体封装件,还包括:
多个第一贯通过孔电极,其包括所述第一贯通过孔电极,所述多个第一贯通过孔电极在所述第一方向上彼此间隔开;和
多个第二贯通过孔电极,其包括所述第二贯通过孔电极,所述多个第二贯通过孔电极在所述第一方向上彼此间隔开,
其中,所述多个第一贯通过孔电极的第一间距实质上等于所述多个第二贯通过孔电极的第二间距。
7.根据权利要求6所述的半导体封装件,其中,所述多个第二贯通过孔电极分别设置在所述多个第一贯通过孔电极上,以电连接到所述多个第一贯通过孔电极。
8.根据权利要求5所述的半导体封装件,还包括:多个第一贯通过孔电极,其包括所述第一贯通过孔电极,所述多个第一贯通过孔电极在所述第一方向上彼此间隔开;和
多个第二贯通过孔电极,其包括所述第二贯通过孔电极,所述多个第二贯通过孔电极在第一方向上彼此间隔开,
其中,所述多个第一贯通过孔电极的第一间距与所述多个第二贯通过孔电极的第二间距不同。
9.根据权利要求5所述的半导体封装件,其中,所述第一衬底在实质上垂直于所述第一方向的第二方向上的第一厚度大于所述第二衬底在所述第二方向上的第二厚度。
10.一种半导体封装件,包括:
封装衬底;
中介层,其设置在所述封装衬底上;
基础芯片,其包括:
第一衬底;和
至少一个第一贯通过孔电极,其延伸穿过所述第一衬底;
第一半导体芯片,其设置在所述基础芯片上,所述第一半导体芯片包括:
第二衬底;和
至少一个第二贯通过孔电极,其延伸穿过所述第二衬底;和
处理器芯片,其设置在所述中介层上并且沿所述第一方向与所述基础芯片间隔开,
其中,所述至少一个第二贯通过孔电极设置在所述至少一个第一贯通过孔电极上,以电连接到所述至少一个第一贯通过孔电极,并且
其中,所述至少一个第一贯通过孔电极在所述第一方向上的第一直径大于所述至少一个第二贯通过孔电极在所述第一方向上的第二直径。
11.根据权利要求10所述的半导体封装件,其中,所述基础芯片包括图形处理单元(GPU)芯片或中央处理单元(CPU)芯片。
12.根据权利要求10所述的半导体封装件,其中,所述基础芯片包括逻辑器件或控制器,并且
其中,所述第一半导体芯片包括存储器件。
13.根据权利要求10所述的半导体封装件,其中所述中介层包括:
第一布线,其将所述基础芯片和所述封装衬底彼此电连接;
第二布线,其将所述处理器芯片和所述封装衬底彼此电连接;和
第三布线,其将所述基础芯片和所述处理器芯片彼此电连接。
14.根据权利要求10所述的半导体封装件,其中,所述第一衬底在实质上垂直于所述第一方向的第二方向上的第一厚度大于所述第二衬底在所述第二方向上的第二厚度。
15.根据权利要求10所述的半导体封装件,其中,所述至少一个第一贯通过孔电极在实质上垂直于所述第一方向的第二方向上的第一长度大于所述至少一个第二贯通过孔电极在所述第二方向上的第二长度。
16.根据权利要求10所述的半导体封装件,其中,所述至少一个第一贯通过孔电极的第一纵横比实质上等于或大于所述至少一个第二贯通过孔电极的第二纵横比。
17.根据权利要求10所述的半导体封装件,其中,所述至少一个第一贯通过孔电极的第一间距实质上等于所述至少一个第二贯通过孔电极的第二间距。
18.根据权利要求10所述的半导体封装件,还包括:多个第一半导体芯片,其包括所述第一半导体芯片,所述多个第一半导体芯片堆叠在实质上垂直于所述第一方向的第二方向上。
19.根据权利要求18所述的半导体封装件,还包括:第二半导体芯片,其设置在所述多个第一半导体芯片在所述第二方向上的最上面的第一半导体芯片上,所述第二半导体芯片包括第三衬底。
20.根据权利要求19所述的半导体封装件,其中,所述第三衬底在所述第二方向上的第三厚度大于所述第二衬底在所述第二方向上的第二厚度。
21.根据权利要求10所述的半导体封装件,还包括:多个第一半导体芯片,其包括所述第一半导体芯片,所述多个第一半导体芯片在所述基础芯片上在所述第一方向上彼此间隔开。
22.一种半导体封装件,包括:
封装衬底;
中介层,其设置在所述封装衬底上;
基础芯片,其包括:
第一衬底;和
至少一个第一贯通过孔电极,其延伸穿过所述第一衬底;
第一半导体芯片,其设置在所述基础芯片上,所述第一半导体芯片包括:
第二衬底;和
至少一个第二贯通过孔电极,其延伸穿过所述第二衬底;和
处理器芯片,其设置在所述中介层上并且在第一方向上与所述基础芯片间隔开,
其中,所述至少一个第一贯通过孔电极在所述第一方向上的第一直径与所述至少一个第二贯通过孔电极在所述第一方向上的第二直径不同,并且
其中,所述第一贯通过孔电极的第一纵横比等于或大于所述第二贯通过孔电极的第二纵横比。
23.根据权利要求22所述的半导体封装件,其中,所述第一衬底在实质上垂直于所述第一方向的第二方向上的第一厚度大于所述第二衬底在所述第二方向上的第二厚度。
24.根据权利要求22所述的半导体封装件,其中,所述至少一个第一贯通过孔电极在实质上垂直于所述第一方向的第二方向上的第一长度大于所述至少一个第二贯通过孔电极在所述第二方向上的第二长度。
25.根据权利要求22所述的半导体封装件,其中,所述至少一个第一贯通过孔电极的第一间距实质上等于所述至少一个第二贯通过孔电极的第二间距。
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KR20150066184A (ko) | 2013-12-06 | 2015-06-16 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
KR102411064B1 (ko) * | 2015-03-10 | 2022-06-21 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그의 제조방법 |
KR102650497B1 (ko) * | 2017-02-28 | 2024-03-25 | 에스케이하이닉스 주식회사 | 적층형 반도체 장치 |
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2018
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- 2019-07-08 US US16/505,040 patent/US11081425B2/en active Active
- 2019-07-09 TW TW108124032A patent/TWI805802B/zh active
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US20200144159A1 (en) | 2020-05-07 |
TWI805802B (zh) | 2023-06-21 |
US11081425B2 (en) | 2021-08-03 |
EP3651197A1 (en) | 2020-05-13 |
TW202018898A (zh) | 2020-05-16 |
KR20200052181A (ko) | 2020-05-14 |
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