TW202010083A - 半導體裝置之封裝結構及其製造方法 - Google Patents

半導體裝置之封裝結構及其製造方法 Download PDF

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TW202010083A
TW202010083A TW107130072A TW107130072A TW202010083A TW 202010083 A TW202010083 A TW 202010083A TW 107130072 A TW107130072 A TW 107130072A TW 107130072 A TW107130072 A TW 107130072A TW 202010083 A TW202010083 A TW 202010083A
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conductive layer
die
conductive
layer
pillars
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TW107130072A
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TWI691040B (zh
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許哲瑋
許詩濱
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英屬開曼群島商鳳凰先驅股份有限公司
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Priority to TW107130072A priority Critical patent/TWI691040B/zh
Priority to US16/537,694 priority patent/US11222880B2/en
Publication of TW202010083A publication Critical patent/TW202010083A/zh
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Abstract

一種半導體裝置之封裝結構包括一第一導電層、一第二導電層、一第一晶粒、一第二晶粒、複數個第一盲孔柱與一導電結構。第一導電層具有一第一表面與一第二表面，且第二導電層位於第一導電層之下方。此外，第一晶粒具有相對設置之一主動面與一背面，其主動面具有複數個金屬襯墊，且第一晶粒係以其背面接置於第一導電層之第一表面。同樣的，第二晶粒具有相對設置之一主動面與一背面，其主動面具有複數個金屬襯墊，且第二晶粒係以其背面接置於第一導電層之第二表面。再者，第一盲孔柱設置於第二導電層與第一晶粒之對應金屬襯墊之間，以傳遞第一晶粒之訊號。導電結構係電性連接第一導電層與第二晶粒之對應金屬襯墊，以傳遞第二晶粒之訊號。第一導電層與第二導電層分別具有預定之線路佈局圖案。第一導電層、第二導電層、第一晶粒、第二晶粒、第一盲孔柱與導電結構係包覆於一介電材料內。

Description

半導體裝置之封裝結構及其製造方法
本發明係關於一種半導體裝置之封裝結構及其製造方法，特別關於一種立體堆疊之半導體封裝結構及其製造方法。
科技日新月異，複合功能(多功能)之裝置已廣泛使用於日常生活中；其係將多種用途或功能整合於單一裝置之中，例如智慧型手機。其除了通話及網路數據傳輸之功能外，亦具有辨識或感測之功能。
欲以單一裝置執行複合功能，通常於單一裝置內需包括兩顆以上之晶片(chip)或晶粒(die)，以分別執行其專司之功能；例如：包括一控制器(controller)晶粒與另一感測器(sensor)晶粒。控制器晶粒維持裝置之系統整體運作，感測器晶粒則專司其感測功能。並且，為了更進一步縮小體積，上述之控制器晶粒與感測器晶粒可整合於單一封裝(package)之中。而為了於單一封裝中容納並整合複數個晶粒，於先前技術中通常係使用立體堆疊之封裝結構。
第1圖為先前技術之立體堆疊之封裝結構單位1-1之剖面圖。參見第1圖，先前技術之立體堆疊封裝結構之每一單位1-1包括一基板(substrate)10、一控制器晶粒11與一感測器晶粒12。基於立體堆疊之方式，係先於基板10上設置控制器晶粒11，再於控制器晶粒11上設置感測器晶粒12。更特定而言，於先前技術之立體堆疊方式中，控制器晶粒11係以其背面112貼附或接置於基板10之第一表面101；同樣的，感測器晶粒12亦以其背面122貼附或接置於控制器晶粒11之主動面111。換言之，控制器晶粒11之主動 面111與感測器晶粒12之主動面121皆朝向上方。
控制器晶粒11之主動面111具有複數個金屬襯墊113(metal pad)，其為控制器晶粒11之訊號之輸入/輸出介面。為了使控制器晶粒11之訊號能夠進一步與周邊層件或其他電路元件進行傳遞，更於該等金屬襯墊113上設置導線13(“wire”，或稱為「引線」)以進一步扇出(fan-out)或扇入(fan-in)其訊號；而導線13之設置係以打線(wire bonding)工序來達成。同樣的，感測器晶粒12之主動面121亦具有複數個金屬襯墊123；並且亦以打線工序於其上分別設置導線14，以進行感測器晶粒12之訊號之扇出/扇入。
然而，如第1圖所示，於先前技術之立體堆疊方式中，感測器晶粒12係接置於控制器晶粒11之主動面111上，因而佔據其主動面111之相當比例之面積，進而排擠到導線13之設置與線路佈局之空間。
此外，兩個晶粒之主動面111與121係朝向同一方向(朝向上方)，意味著其各別之導線13與14必須於同一方向規劃其線路佈局，因而導致導線13與14之線路佈局互相限制或干擾。
並且，由於係以打線工序而接合或設置，導線13與14本身即具有較大之高度。另外，估算封裝結構單位1-1之整體高度時，亦需將基板10之厚度列入考量。
受限於上述諸多限制條件，設計者難以降低先前技術之封裝結構單位1-1之整體高度，導致採用封裝結構單位1-1之裝置與終端產品難以微型化；此為先前技術之封裝結構所具有之缺陷與其面臨之技術問題。
因此，亟需提出一種技術方案，其能夠有效降低整合複數個晶粒之立體堆疊封裝結構之整體高度，以及提供更充分的線路佈線空間與線路佈線的設計彈性，以克服先前技術中存在之上述技術問題。
針對於先前技術所存在之：立體堆疊封裝結構之整 體高度難以降低以及線路佈設互相干擾、受限等之技術問題，本發明係提供一種技術方案；其中，係採用背對背(back to back)堆疊之封裝結構，將兩個晶粒(第一晶粒與第二晶粒)以其背面分別接置於同一導電層(第一導電層)之第一表面與第二表面。基於上述之背對背堆疊設置方式，兩個晶粒各自之主動面係朝向不同方向(分別朝向第一導電層之下方與上方)，以使兩者能夠各自專司於第一導電層下方與上方之空間，各自規劃其扇入/扇出之線路佈局。
更進一步闡述本發明之上述技術方案，本發明係提供一種半導體裝置之封裝結構，該封裝結構之每一單位包括一第一導電層、一第二導電層、一第一晶粒、一第二晶粒、複數個第一盲孔柱與一導電結構。其中，第一導電層、第二導電層均具有相對設置之一第一表面與一第二表面，並且第二導電層位於第一導電層之第一表面下方。此外，第一晶粒具有相對設置之一主動面與一背面，其主動面具有複數個金屬襯墊，並且該第一晶粒係以其背面接置於該第一導電層之第一表面。同樣的，第二晶粒具有相對設置之一主動面與一背面，其主動面具有複數個金屬襯墊，並且該第二晶粒係以其背面接置於該第一導電層之第二表面。再者，第一盲孔柱設置於該第二導電層與該第一晶粒之對應金屬襯墊之間，以傳遞該第一晶粒之訊號。類似的，導電結構係電性連接第一導電層與第二晶粒之對應金屬襯墊，以傳遞該第二晶粒之訊號。並且，該第一導電層與該第二導電層分別具有預定之線路佈局圖案。再者，該第一導電層、第二導電層、第一晶粒、第二晶粒、第一盲孔柱與導電結構係包覆於一介電材料內。
依據本發明之一實施例，其中，本發明之封裝結構更包括一第一貼附層與一第二貼附層，並且該第一晶粒與該第二晶粒係分別經由該第一貼附層與該第二貼附層而分別接置於該第一導電層之第一表面與第二表面。
依據本發明之一實施例，其中，本發明之封裝結構之該第二晶粒係為主動面更具有一感測區域之光學感測晶片，並 且該介電材料對應於該感測區域之部分係選擇性的具有一開口，以暴露出該感測區域。
依據本發明之一實施例，其中，本發明之封裝結構更包括複數個第一層間柱，其設置於該第一導電層與該第二導電層之間，以傳遞該第一導電層與該第二導電層之間的訊號。
依據本發明之一實施例，其中，本發明之封裝結構更包括複數個導電柱，其設置於該第二導電層之第一表面，並且分別連接於複數個對應之外部導電凸塊，該等外部導電凸塊更連接於一外部電路基板。
依據本發明之一實施例，其中，本發明之封裝結構之該等外部導電凸塊分別具有延伸部分，該等延伸部分係選擇性的置換該等導電柱。
依據本發明之一實施例，其中，本發明之封裝結構之導電結構包括複數個第二層間柱、一第三導電層及複數個第二盲孔柱而構成一重佈層線路，以傳遞該第二晶粒之訊號。
依據本發明之一實施例，其中，本發明之封裝結構該第三導電層係位於該第一導電層與該第二晶粒之主動面之上方，該等第二層間柱係設置於該第三導電層與該第一導電層之間，並且該等第二盲孔柱係設置於該第三導電層與該第二晶粒之對應金屬襯墊之間。
另外，依據本發明之一實施例，其中，本發明之封裝結構之導電結構包括複數個導線。各導線之一端接合於該第一導電層之該第二表面，並且各導線之另一端接合於與該第二晶粒之對應金屬襯墊，以傳遞該第二晶粒之訊號。
針對於先前技術所存在之上述技術問題，本發明亦提供一種半導體裝置之封裝結構之製造方法，包括以下各步驟：首先，提供一第一載板。而後，於該第一載板上形成一具有相對設置之一第一表面與一第二表面之第一導電層。而後，將複數個具有相對設置之一主動面與一背面之第一晶粒，以其背面接置於該第一導電層之第一表面。而後，形成一第一介電層包覆該等第 一晶粒與該第一導電層上。而後，於該第一介電層中形成複數個第一盲孔，以分別暴露出該等第一晶粒之主動面之對應金屬襯墊。而後，於該第一介電層上形成一具有相對設置之一第一表面與一第二表面之第二導電層，該第二導電層並向下填充該等第一盲孔而形成複數個第一盲孔柱。而後，形成一第二介電層包覆該第二導電層，以形成一封裝結構半成品。而後，上、下翻轉上述該封裝結構半成品，並於翻轉後之該第二介電層之下方接置一第二載板，且移除該第一載板。而後，將複數個具有相對設置一主動面與一背面之第二晶粒以其背面接置於該第一導電層之第二表面，其中該第一導電層係位於翻轉後之該封裝結構半成品之最上層。而後，形成一導電結構，以電性連接該第一導電層與該等第二晶粒之主動面之對應金屬襯墊。而後，形成一第三介電層包覆該等第一導電層、第二晶粒與導電結構。而後，移除該第二載板。最後，切割上述之封裝結構成為複數個封裝單元。
依據本發明之一實施例，於本發明之製造方法中，該第一載板與該第二載板之面積係為單一晶圓之複數倍，並且該等第一晶粒與第二晶粒係切割自複數個晶圓。
依據本發明之一實施例，於本發明之製造方法中，該等第二晶粒係為主動面具有一感測區域之光學感測晶片，並且選擇性的於該第三介電層形成一開口以暴露出該感測區域。
依據本發明之一實施例，於本發明之製造方法中，於該等第一晶粒與該第一導電層上形成一第一介電層之步驟前，更包括：於該第一導電層之第一表面形成複數個第一層間柱之步驟，該等第一層間柱係連接於後續形成之該第二導電層之第二表面。
依據本發明之一實施例，於本發明之製造方法中，於該第一介電層上形成該第二導電層之步驟後，更包括：於該第二導電層之第一表面形成複數個導電柱之步驟，並可於該封裝結構製造完成後，將該等導電柱分別連接於複數個對應之外部導電凸塊。
依據本發明之一實施例，於本發明之製造方法中，形成該導電結構之步驟包括：形成複數個第二層間柱、一第三導電層及複數個第二盲孔柱以構成一重佈層線路之步驟，以將該等第二晶粒之該等金屬襯墊電性連接於該第一導電層。
依據本發明之一實施例，於本發明之製造方法中，形成該等第二層間柱、該第三導電層及該等第二盲孔柱之步驟包括：首先，於第一導電層之第二表面形成該等第二層間柱。而後，形成一第三介電層包覆該第一導電層、該等第二晶粒以及該等第二層間柱。而後，於該第三介電層中形成複數個第二盲孔，以分別暴露出該等第二晶粒之對應金屬襯墊。而後，於該第三介電層上形成該第三導電層，該第三導電層並向下填充該等第二盲孔而形成該等第二盲孔柱，其中該第三導電層連接該等第二層間柱。
另外，依據本發明之一實施例，於本發明之製造方法中，其中形成該導電結構之步驟係包括執行打線工序，以將複數個導線之一端接合於該第一導電層之第二表面，並將其另一端接合於與該等第二晶粒之主動面之對應金屬襯墊。
基於上述各技術特徵，於本發明之封裝結構中，第一晶粒係於第一導電層下方之空間，以第一盲孔柱連接至第二導電層而作為其扇入/扇出之重佈層線路。另一方面，第二晶粒係於第一導電層上方之空間，以第二盲孔柱連接至第三導電層，並再經由第二層間柱連接至第一導電層而作為其扇入/扇出之重佈層線路(或者，於另一實施例中，第二晶粒係以導線直接連接至第一導電層而作為其扇入/扇出之線路)。承上，兩晶粒各自於第一導電層下方與上方之空間佈局其扇入/扇出之線路，兩者之間得以免除互相限制與干擾，因而能夠大幅提升佈線設計之彈性與有效降低立體堆疊封裝結構之整體高度。此為本發明之主要技術功效或功能，其能夠克服先前技術所存在之技術問題。
1-1、38-1、38-2、38-3、38-1b、38-1c、38-1d、38-1e、38-1f、54-1、54-2、54-3、54-1b、54-1c、54-1d‧‧‧封裝結構單位
10‧‧‧基板
101、201、213、251、262、281、341、351、362、511、531‧‧‧第一表面
11‧‧‧控制器晶粒
111、121、231、321‧‧‧主動面
112、122、232、322‧‧‧背面
113、123、233‧‧‧金屬襯墊
12‧‧‧感測器晶粒
13、14、52‧‧‧導線
20‧‧‧第一載板
21‧‧‧第一導電層
211‧‧‧置晶部
212‧‧‧線路部
214、263‧‧‧第二表面
22‧‧‧第一貼附層
23‧‧‧第一晶粒
24‧‧‧第一層間柱
241、271、331‧‧‧第一端面
25‧‧‧第一介電層
25a‧‧‧第一盲孔
26‧‧‧第二導電層
261‧‧‧第一盲孔柱
27‧‧‧導電柱
28‧‧‧第二介電層
29‧‧‧封裝結構半成品
30‧‧‧第二載板
31‧‧‧第二貼附層
32‧‧‧第二晶粒
321a‧‧‧感測區域
321b‧‧‧金屬襯墊區域
33‧‧‧第二層間柱
34、51‧‧‧保護層
35、53‧‧‧第三介電層
35a‧‧‧第二盲孔
36‧‧‧第三導電層
361‧‧‧第二盲孔柱
36a、37a、401、402、53a‧‧‧開口
37‧‧‧覆蓋層
38、54‧‧‧封裝結構
40‧‧‧介電材料
41‧‧‧電路基板
411‧‧‧導電凸塊
412‧‧‧導電凸塊之延伸部分
第1圖為先前技術之立體堆疊之封裝結構單位之剖面圖。
第2A至2K圖以及第3A至3H圖為根據本發明第一實施例之封裝結構製造方法之示意圖。
第4A-1至4C-2圖為根據本發明第一實施例之不同實施態樣之封裝結構單位之剖面圖。
第5A至5F圖為根據本發明第二實施例之封裝結構製造方法之後續步驟之示意圖。
第6A-1至6B-2圖為根據本發明第二實施例之不同實施態樣之封裝結構單位之剖面圖。
以下將透過實施例來解釋本發明內容，本發明的實施例並非用以限制本發明須在如實施例所述之任何特定的環境、應用或特殊方式方能實施。因此，關於實施例之說明僅為闡釋本發明之目的，而非用以限制本發明。須說明者，以下實施例及圖式中，與本發明非直接相關之元件已省略而未繪示；且圖式中各元件間之尺寸關係僅為求容易瞭解，非用以限制實際比例。另外，以下實施例中，相同的元件將以相同的元件符號加以說明。
第2A至2K圖以及第3A至3H圖為根據本發明第一實施例之封裝結構製造方法之示意圖。參見第2A圖，首先，係提供一第一載板(carrier)20，其可包括金屬板或絕緣板。若第一載板20採用金屬板，其可為銅。另一方面，若第一載板20採用絕緣板，則其可為陶瓷、環氧樹脂(epoxy resin)、聚乙醯胺(polyimide)、氰脂(cyanate ester)、碳纖維(carbon fiber)或玻璃纖維(glass fiber)與環氧樹脂所混合之材質所構成。
於傳統之晶圓型式(wafer type)之製程中，僅能對形成於單一晶圓內之晶粒(die)同時進行封裝製程，其較為耗時且具有製程上之諸多限制。相較於傳統之晶圓型式之封裝製程，本發明採用大板面型式(panel type)之封裝製程；其中，本發明之第一載板20之面積為單一晶圓面積之複數倍。據此，本發明之大尺寸第一載板20能夠對於切割自複數個晶圓之全部晶粒同時進行封裝製程，而能有效節省製造時程。
接下來，係於第一載板20之第一表面201形成第一導電層21。第一導電層21具有相對設置之一第一表面213及一第二表面214，其可包括導電金屬材料，例如銅、銀、鎳或其組成之合金。可配合額外之光阻層(圖中未顯示)執行曝光顯影工序，並執行電鍍工序，以將圖形化之第一導電層21形成於第一載板20之第一表面201。
圖形化之第一導電層21具有預定之線路佈局圖案(layout pattern)，其中，每一單位之第一導電層21可包括彼此電性分離之置晶部211、線路部212。然而本發明之製造方法中，第一導電層21之線路佈局圖案不限於圖式所示之電性連接方式。於其他實施態樣中，第一導電層21之各部分亦可具有其他電性連接方式，因而具有不同之線路佈局圖案。或者，針對於同一實施態樣之第一導電層21，若採取不同位置的剖面，亦將呈現出不同電性連接方式之各部分。
接下來，參見第2B圖，於第一導電層21之每一單位之置晶部211之第一表面213，形成第一貼附層(adhesive layer)22，其例如為高分子黏性材料或散熱型金屬材料。
接下來，參見第2C圖，將切割自複數個晶圓之各第一晶粒23貼附或接置於對應之第一貼附層22上。第一晶粒23可例如為控制器晶粒或處理器(processor)晶粒，其於整體電路中扮演主控者之角色。
更特定而言，各第一晶粒23具有主動面231(或正面)及背面232。主動面231具有複數個金屬襯墊233。各金屬襯墊233更可連接於例如為盲孔柱的導電結構或其他形式之電性連接路徑(例如：導線)，以扇入/扇出第一晶粒23之訊號。另一方面，背面232則貼附於第一貼附層22。
接下來，參見第2D圖，分別於第一導電層21之線路部212之第一表面213，向上形成柱體狀之第一層間柱24。第一層間柱24為導電金屬材料，例如銅；其可經由金屬電鍍工序而形成。並且，第一層間柱24之高度略高於各第一晶粒23之金屬襯墊233。
第一層間柱24之技術功效或功能在於：首先，作為不同導電層(第一導電層21與後續步驟中形成的第二導電層26)之間的電性連接路徑，以進行上述兩導電層之間的訊號傳遞。其次，可作為上述兩導電層之間的力學支撐。接下來，參見第2E圖，執行鑄模(molding)工序(亦可稱為「壓模」或「灌模」工序)，以形成第一介電層25(dielectric layer)。第一介電層25之材質為絕緣材料，其例如為酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)或矽基樹脂(Silicone-Based Resin)。上述之絕緣材料於液態時，填充於第一載板20之上、各第一層間柱24以及各第一晶粒23之間。而後，絕緣材料於固化後，形成第一介電層25，其包覆各第一晶粒23、各第一層間柱24以及第一導電層21。而後，並經由研磨(grinding)工序，使各第一層間柱24之第一端面241分別自第一介電層25之第一表面251中暴露出來。
接下來，參見第2F圖，執行雷射鑽孔(laser drilling)工序，於第一介電層25中形成複數個第一盲孔(blind via)25a。各第一盲孔25a係分別對應於第一晶粒23之各金屬襯墊233，以分別暴露出各金屬襯墊233。
接下來，參見第2G圖，係於第一介電層25之第一表面251上形成第二導電層26。第二導電層26具有相對設置之一第一表面262及一第二表面263，其材料可相同或不同於第一導電層21之導電金屬材料，例如為銅、銀、鎳或其組成之合金。並且，與第一導電層21之形成方式相同：係可配合額外之光阻層(圖中未顯示)執行曝光顯影工序，並執行電鍍工序，以將上述導電金屬材料選擇性的形成於第一介電層25之第一表面251上；上述導電金屬材料並向下填充第一介電層25之各第一盲孔25a，而形成填充各第一盲孔25a之柱體狀第一盲孔柱261。並且，各第一盲孔柱261分別連接至第一晶粒23之各金屬襯墊233。第一盲孔柱261之技術功效或功能在於：作為第一晶粒23之各金屬襯墊233與第二導電層26之間的電性連接路徑，以扇入/扇出第一晶粒23之訊號。
更特定而言，第二導電層26亦具有預定之線路佈局 圖案(不同或相同於第一導電層21之線路佈局圖案)。其中，每一單位之第二導電層26之第二表面263係分別連接至第一層間柱24、第一盲孔柱261。
接下來，參見第2H圖，係於第二導電層26之第一表面262，向上形成複數個導電柱27，以扇入/扇出第一晶粒23之訊號。導電柱27之材料可相同或不同於第一層間柱24之導電金屬材料，例如為銅；其亦可經由金屬電鍍工序而形成。
接下來，參見第2I圖，係於第一介電層25及第二導電層26之上，形成第二介電層28。第二介電層28之材質相同於第一介電層25，其為絕緣材料，可例如為酚醛基樹脂、環氧基樹脂或矽基樹脂。係以鑄模工序，將上述材料填充於第一介電層25及第二導電層26之上及各導電柱27之間。而後，於上述材料固化後執行研磨工序，使該等導電柱27之第一端面271能分別自第二介電層28之第一表面281中暴露出來。
由於第二介電層28與第一介電層25採用相同之材質，於本實施例中，亦可將第二介電層28與第一介電層25合併視為單一之介電層。換言之，並非形成具有不同材質之另一介電層；而是鑄模填充相同材質，以使第一介電層25之高度提升，使其與導電柱27之第一端面271齊平，並且使導電柱27之第一端面271暴露出來。
承上，本實施例(第一實施例)之封裝結構製造方法執行至此，前述各步驟中所形成之各結構層件(包括第一導電層21、第一貼附層22、第一晶粒23、第一層間柱24、第一介電層25、第二導電層26、導電柱27及第二介電層28)可統稱為「封裝結構半成品29」。
接下來，參見第2J圖，將第一載板20連同其上之封裝結構半成品29於垂直方向翻轉(即：上下翻轉)。然而，於其他實施態樣中，若製程上無特別需求，封裝結構半成品29亦可不進行翻轉。
接著，係將翻轉後之封裝結構半成品29接置於另一 第二載板30。而後，係將第一載板20自翻轉後之封裝結構半成品29上移除。
接下來，參見第2K圖，於第一導電層21之第二表面214，形成第二貼附層31。相同或不同於第一貼附層22，第二貼附層31亦可為高分子黏性材料或散熱型金屬材料。
更特定而言，於垂直方向上、下翻轉後，第一導電層21係位於封裝結構半成品29之最上層；而第二貼附層31則對應形成或貼附於第一導電層21之置晶部211之第二表面214。此外，於第2B圖所示之步驟中，第一貼附層22已形成於第一導電層21之置晶部211之第一表面213；因此，第二貼附層31與第一貼附層22係分別形成於第一導電層21之置晶部211之相對兩側(反向之兩側)之表面，其提供了本發明之背對背(back to back)堆疊之封裝結構之基本雛形。
而後，切割自複數個晶圓之各第二晶粒32係接置或貼附於對應之第二貼附層31上。相對於作為主控者角色的第一晶粒23，第二晶粒32則接收第一晶粒23之指令，以執行特定功能或特殊應用。
更具體而言，採用本發明之封裝結構之半導體裝置，其可應用於穿戴裝置或物聯網之感測模組，例如為光學感測模組。針對於此應用途徑，本實施例之第二晶粒32可為光學感測晶片(optical sensor Chip)。第二晶粒32可具有相對設置之主動面321(或正面)與背面322。其主動面321具有一感測區域321a以接收外界光線並據以感測外界之目標物。此外，其主動面321並具有複數金屬襯墊區域321b以設置複數個金屬襯墊(圖中未顯示)。另一方面，第二晶粒32之背面322則接置於第二貼附層31。
執行了第2A至2K圖所示之封裝結構製造方法之上述各步驟，係已建構了背對背堆疊之封裝結構之基礎架構。接下來，執行第3A至3H圖所示之本發明第一實施例之製造方法之後續步驟。其中，第3A圖至第3G圖主要係說明形成導電結構的方法。
首先參見第3A圖，形成導電結構的步驟係包括於第 一導電層21之線路部212之第二表面214，形成柱體狀之第二層間柱33。第二層間柱33之材料可相同或不同於第一層間柱24或導電柱27之導電金屬材料，例如為銅；其亦可經由金屬電鍍工序而形成。更特定而言，第二層間柱33之技術功效與功能在於：作為第一導電層21與後續步驟中形成之第三導電層36之間的電性連接路徑，以進行上述兩導電層之間的訊號傳遞；此外，並提供作為上述兩導電層之間的力學支撐。
於一種實施態樣中，第二層間柱33可與對應之第一層間柱24及導電柱27設於同一軸線上對齊。然而本發明之製造方法不限於上述設置方式；於其他實施態樣中，第二層間柱33、第一層間柱24及導電柱27亦可彼此偏離不在於同一軸線上。此外，於尺寸之考量上，第二層間柱33之高度略高於各第二晶粒32之主動面321。
特別注意的是，可等效置換的，於第一實施例之其他實施態樣中，第3A圖所示之形成第二層間柱33步驟，其亦可於第2K圖所示之接置第二晶粒32步驟之前執行。
接下來，參見第3B圖，形成導電結構的步驟還包括於各第二晶粒32之感測區域321a上形成保護層34，其可為絕緣材料或光阻。其經由曝光顯影工序而選擇性的覆蓋於各第二晶粒32之感測區域321a，並且暴露出其金屬襯墊區域321b。或者，於其他實施態樣中，保護層34亦可為保護膜(film)。
第一實施例之保護層34之技術功效或功能，係提供各第二晶粒32之感測區域321a所需之保護，以防止感測區域321a於後續步驟之各工序中遭到損壞。
接下來，參見第3C圖，形成導電結構的步驟還包括執行鑄模工序，係於封裝結構半成品29之上、各第二晶粒32之間及各第二層間柱33之間注入液態鑄模材料以形成第三介電層35，所形成之第三介電層35並包覆保護層34之側壁。第三介電層35之材質相同於第一介電層25與第二介電層28，其可例如為酚醛基樹脂、環氧基樹脂或矽基樹脂等等之絕緣材料。上述材料固化後進 行研磨工序，以使得各保護層34之第一表面341、各第二層間柱33之第一端面331分別自第三介電層35之第一表面351中暴露出來。由於第三介電層35之材質相同於第一介電層25與第二介電層28，因此可將上述三個介電層合併視為單一之介電層。
接下來，參見第3D圖，形成導電結構的步驟還包括對於第三介電層35執行雷射鑽孔工序，以於保護層34之兩側對應於金屬襯墊區域321b之處形成第二盲孔35a。各第二盲孔35a並分別暴露出各第二晶粒32之金屬襯墊區域321b之金屬襯墊。
接下來，參見第3E圖，形成導電結構的步驟還包括於第三介電層35上形成第三導電層36。類似於第一導電層21與第二導電層26之形成方法，係配合額外之光阻層(圖中未顯示)執行曝光顯影工序，並執行電鍍工序，以將例如為銅、銀、鎳或其組成之合金之導電金屬材料，選擇性的形成於第三介電層35之第一表面351。
類似於第一導電層21與第二導電層26，第三導電層36亦具有預定之線路佈局圖案。進一步而言，圖案化之第三導電層36覆蓋第三介電層35之部分第一表面351，並向下填充各第二盲孔35a，且覆蓋第二層間柱33之第一端面331。另一方面，圖案化之第三導電層36具有複數個開口36a，其暴露出保護層34(下方有感測區域321a)以及第三介電層35之部分第一表面351。
更進一步而言，第三導電層36向下填充各第二盲孔35a而形成柱體狀之第二盲孔柱361。並且，各第二盲孔柱361分別連接至第二晶粒32之金屬襯墊區域321b之各金屬襯墊。第二盲孔柱361之技術功效或功能在於：作為第二晶粒32之各金屬襯墊與第三導電層36之間的電性連接路徑，以扇入/扇出第二晶粒32之訊號。
接下來，參見第3F圖，形成導電結構的步驟還包括以咬蝕或其他切蝕方式移除保護層34之各部分。移除保護層34後，第三導電層36之各開口36a可進而暴露出各第二晶粒32之感測區域321a。
接下來，參見第3G圖，形成導電結構的步驟還包括 於第三導電層36上形成覆蓋層37。覆蓋層37為絕緣材質，其可例如為感光材料。覆蓋層37可覆蓋第三導電層36及第三介電層35之部分第一表面351。並且，覆蓋層37之各開口37a分別暴露出各第二晶粒32之感測區域321a。
特別注意的是，於第一實施例之其他實施態樣中，因應於其他型式之第二晶粒32或其他型式之終端產品，亦可省略形成覆蓋層37之步驟。
承上，第一實施例之製造方法執行至此，前述各步驟中所形成之各結構層件(包括封裝結構半成品29、第二貼附層31、第二晶粒32、第二層間柱33、第三介電層35、第三導電層36及覆蓋層37)可統稱為「封裝結構38」。而後，將封裝結構38與第二載板30分離。
接下來，參見第3H圖，係將分離後之封裝結構38切割成各個單位。例如，係執行雷射切割工序(或其他切割方式)，將封裝結構38切割成單位38-1、單位38-2及單位38-3等等。第一實施例之各個封裝結構單位之結構特徵之詳細說明，請參見下文之敘述並配合第4A-1至4C-2圖之圖示。
第4A-1至4C-2圖為根據本發明第一實施例之不同實施態樣之封裝結構單位之剖面圖。參見第4A-1圖，其中係以導電層搭配導電柱(盲孔柱與層間柱)作為第二晶粒32之扇出/扇入之重佈層線路。
其中，第三導電層36之材質相同或不同於第一導電層21或第二導電層26，其可例如為銅、銀、鎳或其組成之合金等等之導電金屬材料。第三導電層36設置於第一導電層21以及第二晶粒32之上方，並且略高於第二晶粒32之主動面321。此外，第三導電層36亦為圖案化導電層，其可具有預定之線路佈局圖案，且可選擇性的在對應於第二晶粒32之感測區域321a上方形成開口36a，因而能夠暴露出第二晶粒32之感測區域321a，以利第二晶粒32執行光學感測。
再者，第二層間柱33之材質相同或不同於第一層間 柱24，其為導電金屬材料，可例如為銅。第二層間柱33係分別形成於第一導電層21之線路部212之第二表面214，並向上延伸而分別連接至第三導電層36之第一表面362。因此，第二層間柱33形成第三導電層36與第一導電層21之間的電性連接路徑。
於一種實施態樣中，第二層間柱33可分別與第一層間柱24於同軸線方向上對齊(而於其他實施態樣中，第二層間柱33亦可形成於不同水平位置，而與第一層間柱24彼此偏離)。並且，第二層間柱33之高度略高於第二晶粒32之厚度。
另一方面，第二盲孔柱361係與第三導電層36於同一步驟中形成，因此其材質係與第三導電層36相同，其可例如為銅、銀、鎳或其組成之合金等等之導電金屬材料。其中，第二盲孔柱361分別形成於第三導電層36之第一表面362，並向下延伸而分別連接至第二晶粒32之金屬襯墊區域321b之對應金屬襯墊(圖中未顯示)，而形成第二晶粒32與第三導電層36之間的電性連接路徑。並且，第二盲孔柱361之側邊切齊覆蓋層37之開口37a。
承上，第三導電層36搭配對應之第二盲孔柱361與第二層間柱33，所整體形成之電性連接路徑(361-36-33)係作為第二晶粒32扇出/扇入之重佈層線路；如此，相對於傳統打線封裝結構而言即可有效降低封裝結構之整體厚度。
上述之電性連接路徑(361-36-33)係由導電層與導電柱形成，而能夠有效降低第一實施例之封裝結構單位38-1之高度。再者，第一實施例係以半導體製程構成導電層與導電柱而形成電性連接路徑(361-36-33)，其無須額外進行打線工序，因而能夠降低封裝結構之製造成本。
由上，可知本發明之主要技術特徵在於：基於背對背堆疊之設置方式，第一晶粒23與第二晶粒32分別於第一導電層21之下方與上方，各自具有足夠之空間以分別設置其扇出/扇入之線路，以滿足各種線路之彈性設計需求。其中，第一晶粒23係專司於第一導電層21與第二導電層26之間的空間，設置由第一盲孔柱261搭配第二導電層26所構成之扇出/扇入重佈層線路。因此，另 一方面，第二晶粒32能夠充裕的專司於第一導電層21上方，設置由第二盲孔柱361、第三導電層36、第二層間柱33搭配第一導電層21所構成之扇出/扇入線路。
基於上述技術特徵，第一晶粒23與第二晶粒32兩者之扇出/扇入線路具有各自之佈局空間，而得以避免互相干擾。因此能夠克服先前技術中，控制器晶粒11與感測器晶粒12各自之扇出/扇入線路之佈局相互牽制之窘境；此外，第二晶粒32於其上方亦具有專司之充足空間，以利第二晶粒32之感測區域321a進行感測，而免於遭遇第一晶粒23之扇出/扇入重佈層線路之干擾。如此，即能提供給第一晶粒23、第二晶粒32各自充足的線路佈設空間與設計彈性，更能有效降低封裝結構之整體厚度，進而滿足薄型化之半導體封裝需求。
第4A-2圖為根據本發明第一實施例之另一實施態樣之封裝結構單位38-1b之剖面圖。參見第4A-2圖，本實施態樣之封裝結構單位38-1b類似於第4A-1圖所示之封裝結構單位38-1；而差異之處在於：本實施態樣之封裝結構單位38-1b不包括導電柱27，而係以導電凸塊411之延伸部分412取代之。
第4B-1及4B-2圖分別為根據本發明第一實施例之另一實施態樣之封裝結構單位38-1c及38-1d之剖面圖。參見第4B-1及4B-2圖，本實施態樣之封裝結構單位38-1c及38-1d分別類似於第4A-1及4A-2圖所示之封裝結構單位38-1及38-1b；而差異之處在於：本實施態樣之第二晶粒32為光學感測晶片以外之其他型式晶粒，其不具光學感測功能，因此其主動面321無須暴露於外界；因而本實施態樣之覆蓋層37於第二晶粒32上方無須形成開口。
第4C-1及4C-2圖分別為根據本發明第一實施例之又一實施態樣之封裝結構單位38-1e及38-1f之剖面圖。參見第4C-1及4C-2圖，本實施態樣之封裝結構單位38-1e及38-1f分別類似於第4A-1及4A-2圖所示之封裝結構單位38-1及38-1b；而差異之處在於：本實施態樣之介電材料40、第二晶粒32、及第三導電層36之上無須形成覆蓋層。
再者，執行了第2A至2K圖所示之封裝結構製造方法之上述各步驟，係已建構了背對背堆疊之封裝結構之基礎架構。接下來，執行第5A至5F圖所示之本發明第二實施例之製造方法之後續步驟。其中，第5A圖至第5F圖主要係說明形成導電結構的另一種方法。
首先參見第5A圖，經由曝光顯影工序，將材質為絕緣材料或光阻之保護層51，選擇性的僅覆蓋於各第二晶粒32之主動面321之感測區域321a，而暴露出主動面321之金屬襯墊區域321b。保護層51之技術功效或功能在於，保護各第二晶粒32之感測區域321a，防止該區域於後續步驟之工序(特別是打線工序)中遭到損壞。此外，保護層51亦可使各第二晶粒32之感測區域321a上方能夠預留空間；詳言之，在完成後續之打線及鑄模步驟後將移除各保護層51，而移除保護層51後所遺留之預留空間可形成開口，藉其可將各第二晶粒32之感測區域321a暴露於外界而得以感測外界之目標物。
於本實施態樣中，係於各第二晶粒32接置於第二載板30上之封裝結構半成品29(如第2K圖所示)之步驟後，始於其主動面321形成保護層51。換句話說，係於各第二晶粒32接置於第二載板30後之大板面型式製程中，始執行形成保護層51之步驟。
而於另一實施態樣中，亦可於各第二晶粒32接置於第二載板30上之封裝結構半成品29之步驟前，先行於其主動面321形成保護層51。換句話說，可於接置於第二載板30之前，各第二晶粒32仍處於晶圓型式製程之狀態下，先行於第二晶粒32上形成保護層51。
此外，於其他實施態樣中，若各第二晶粒32為光學感測晶片以外之其他型式晶粒，其不具有感測區域，因而無須對其主動面321進行保護，亦無須於最終封裝結構中暴露出其主動面321；則於此實施條件下可省略形成保護層51之步驟。
接下來，參見第5B圖，係形成一導電結構，在本實施例中，其包括執行打線工序。具體而言，係將導線52之一端接 合(bonding)於各第二晶粒32之金屬襯墊區域321b之各對應金屬襯墊，並將導線52之另一端接合於第一導電層21之線路部212之第二表面214。
進一步而言，本實施例之導電結構係以打線工序將導線52之一端接合於第二晶粒32之金屬襯墊區域321b之對應金屬襯墊，並將導線52之另一端接合於第一導電層21之線路部212之第二表面214。導線52之技術功效或功能在於：提供第二晶粒32與第一導電層21之間的電性連接路徑，以將第二晶粒32之內部訊號扇出至第一導電層21，或將來自第一導電層21之外部訊號扇入至第二晶粒32。換言之，導線52與第一導電層21係作為第二晶粒32與周邊層件傳遞訊號之扇出/扇入之線路。
接下來，參見第5C圖，係執行鑄模工序，係於封裝結構半成品29之上、各第二晶粒32之間、以及各保護層51之間形成第三介電層53，所形成之第三介電層53並且完整覆蓋或包覆各導線52。第三介電層53之材質相同於第一介電層25與第二介電層28，其可例如為酚醛基樹脂、環氧基樹脂或矽基樹脂等等之絕緣材料。上述材料於液態時進行鑄模填充，並於上述材料固化後進行研磨工序，以使得各保護層51之第一表面511分別自第三介電層53之第一表面531中暴露出來。
由於第三介電層53之材質相同於第一介電層25與第二介電層28，於本實施例中，亦可將上述三個介電層合併視為單一之介電層。換句話說，可視為將已經形成之第一介電層25之範圍向上擴充，使其得以完整覆蓋各第二晶粒32及各導線52，並且得以包覆各保護層51之側壁。
接下來，參見第5D圖，係以咬蝕或其他切蝕方式，將各保護層51移除。移除保護層51後所遺留下之空間則成為開口53a，其可將各第二晶粒32之感測區域321a暴露於外界，以感測外界光線，並據此對於外界目標物施行感測。
承上，第一實施例之製造方法執行至此，前述各步驟中所形成之各結構層件(包括封裝結構半成品29、第二貼附層 31、第二晶粒32、導線52以及第三介電層53)可統稱為「封裝結構54」。
接下來，參見第5E圖，係將第二載板30移除，使其與封裝結構54分離。於本步驟中，可使用如第2J圖所示之分離第一載板20步驟之相同方式，以將封裝結構54與第二載板30分離。
接下來，參見第5F圖，係將分離後之封裝結構54切割成各個單位。例如，係執行雷射切割工序(或其他切割方式)，將封裝結構54切割成單位54-1、單位54-2及單位54-3等等。第二實施例之各個封裝結構單位之結構特徵之詳細說明，請參見下文之敘述並配合第6A-1至6B-2圖之圖示。
第6A-1至6B-2圖為根據本發明第二實施例之不同實施態樣之封裝結構單位之剖面圖。參見第6A-1圖，於本實施態樣中，每一單位之封裝結構(例如：單位54-1)包括：第一導電層21、第二導電層26，第一盲孔柱261、第一層間柱24、導電柱27、第一晶粒23、第二晶粒32、第一貼附層22、第二貼附層31及導線52。並且，上述各層件與電路元件皆包覆於一介電材料40內，僅有第二晶粒32之部分區域(其主動面321之感測區域321a)暴露於外界。
封裝結構單位54-1之前述各結構層件，諸如第一導電層21、第二導電層26、第一盲孔柱261、第一層間柱24、第一與第二貼附層22與31、第一晶粒23、第二晶粒32及導線52，皆係包覆於介電材料40內。介電材料40之材質為絕緣材料，其可例如為酚醛基樹脂、環氧基樹脂或矽基樹脂；因此介電材料40提供了封裝結構單位54-1之上述各結構層件之間的電性分離(isolation)。此外，介電材料40亦對於上述各結構層件提供了保護作用以及散熱作用。另一方面，介電材料40於第二晶粒32之感測區域321a上方具有一開口401，其係將感測區域321a暴露於外界，以使第二晶粒32能夠藉由感測區域321a接收外界光線並據以感測外界之目標物。再者，於本實施態樣中之導電柱27，更分別連接至封裝結構單位54-1之外部之導電凸塊411(亦可為錫球或銲球)，並經由外部 導電凸塊411電性連接至一外部電路基板41。其中，外部電路基板41可例如為印刷電路板(PCB)。
由上，本發明之主要技術特徵在於：基於背對背堆疊之設置方式，第一晶粒23與第二晶粒32分別於第一導電層21之下方與上方，各自具有足夠之空間以分別設置其扇出/扇入之線路，以滿足各種線路之彈性設計需求。其中，第一晶粒23係專司於第一導電層21與第二導電層26之間的空間，設置由第一盲孔柱261搭配第二導電層26所構成之扇出/扇入重佈層線路。因此，另一方面，第二晶粒32能夠充裕的專司於第一導電層21上方，設置由導線52搭配第一導電層21所構成之扇出/扇入線路。
基於上述技術特徵，第一晶粒23與第二晶粒32兩者之扇出/扇入線路具有各自之佈局空間，而得以避免互相干擾。因此能夠克服先前技術中，控制器晶粒11與感測器晶粒12各自之扇出/扇入線路之佈局相互牽制之窘境；此外，第二晶粒32於其上方亦具有專司之充足空間，以利第二晶粒32之感測區域321a進行感測，而免於遭遇第一晶粒23之扇出/扇入重佈層線路之干擾。
第6A-2圖為根據本發明第二實施例之另一實施態樣之封裝結構單位54-1b之剖面圖。參見第6A-2圖，本實施態樣之封裝結構單位54-1b類似於第6A-1圖所示之封裝結構單位54-1；而差異之處在於：本實施態樣之封裝結構單位54-1b不包括導電柱27。取而代之的技術方案為：於封裝結構單位54-1b的介電材料40中，更於原導電柱27之形成位置分別形成開口402。並且，外部導電凸塊411具有延伸部分412，其可分別延伸入開口402，進而連接至第二導電層26之第一表面262，以取代原導電柱27。
特別說明的是，若欲製造本實施態樣之封裝結構單位54-1b，則於對應之製造方法中，將第2H圖所示之形成導電柱27之步驟省略。
第6B-1圖為根據本發明第二實施例之又一實施態樣之封裝結構單位54-1c之剖面圖。參見第6B-1圖，本實施態樣之封裝結構單位54-1c類似於第6A-1圖所示之封裝結構單位54-1；而差 異之處在於：本實施態樣之第二晶粒32為光學感測晶片以外之其他型式晶粒，其不具光學感測功能，因此其主動面321無須暴露於外界；因而本實施態樣之介電材料40於第二晶粒32上方無須形成開口。
特別說明的是，若欲製造本實施態樣之封裝結構單位54-1c，則於對應之製造方法中，將第5A圖所示之形成保護層51之步驟省略。
第6B-2圖為根據本發明第二實施例之再一實施態樣之封裝結構單位54-1d之剖面圖。參見第6B-2圖，本實施態樣之封裝結構單位54-1d類似於第6B-1圖所示之封裝結構單位54-1c；而差異之處在於：本實施態樣之封裝結構單位54-1d不包括導電柱27，而係以外部導電凸塊411之延伸部分412取代之。
綜上所述，本發明可提供第一晶粒23、第二晶粒32充分之線路佈設空間與線路佈設的設計彈性，且相對於打線封裝結構而言更能有效降低封裝結構的整體厚度，是以本發明符合發明專利之要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士，爰依本案發明精神所作之等效修飾或變化，皆應包括於以下之申請專利範圍內。
21‧‧‧第一導電層
212‧‧‧線路部
214‧‧‧第二表面
23‧‧‧第一晶粒
24‧‧‧第一層間柱
26‧‧‧第二導電層
261‧‧‧第一盲孔柱
32‧‧‧第二晶粒
321‧‧‧主動面
321a‧‧‧感測區域
321b‧‧‧金屬襯墊區域
33‧‧‧第二層間柱
36‧‧‧第三導電層
36a‧‧‧開口
361‧‧‧第二盲孔柱
362‧‧‧第一表面
37‧‧‧覆蓋層
37a‧‧‧開口
38-1‧‧‧封裝結構單位

Claims (17)

  1. 一種半導體裝置之封裝結構，該封裝結構之每一單位包括：一第一導電層，具有相對設置之一第一表面與一第二表面；一第二導電層，位於該第一導電層之第一表面下方，且具有相對設置之一第一表面與一第二表面；一第一晶粒，具有相對設置之一主動面與一背面，其主動面具有複數個金屬襯墊，並且該第一晶粒係以其背面接置於該第一導電層之第一表面；一第二晶粒，具有相對設置之一主動面與一背面，其主動面具有複數個金屬襯墊，並且該第二晶粒係以其背面接置於該第一導電層之第二表面；複數個第一盲孔柱，設置於該第二導電層與該第一晶粒之對應金屬襯墊之間，以傳遞該第一晶粒之訊號；以及一導電結構，電性連接該第一導電層與該第二晶粒之對應金屬襯墊，以傳遞該第二晶粒之訊號；其中該第一導電層與該第二導電層分別具有預定之線路佈局圖案，並且該等第一導電層、第二導電層、第一晶粒、第二晶粒、第一盲孔柱與導電結構係包覆於一介電材料內。
  2. 如請求項1之封裝結構，更包括一第一貼附層與一第二貼附層，該第一晶粒與該第二晶粒係分別經由該第一貼附層與該第二貼附層而分別接置於該第一導電層之第一表面與第二表面。
  3. 如請求項1之封裝結構，其中該第二晶粒之主動面更具有一感測區域，該介電材料對應於該感測區域之部分係選擇性的具有一開口，以暴露出該感測區域。
  4. 如請求項1之封裝結構，更包括複數個第一層間柱，其設置於該第一導電層與該第二導電層之間，以傳遞該第一導電層與該第二導電層之間的訊號。
  5. 如請求項1之封裝結構，更包括複數個導電柱，其設置於該第二導電層之第一表面，並且分別連接於複數個對應之外部導電凸塊。
  6. 如請求項5之封裝結構，其中該等外部導電凸塊分別具有延伸部分，該等延伸部分係選擇性的置換該等導電柱。
  7. 如請求項1之封裝結構，其中該導電結構包括複數個第二層間柱、一第三導電層及複數個第二盲孔柱而構成一重佈層線路，以傳遞該第二晶粒之訊號。
  8. 如請求項7之封裝結構，其中該第三導電層係位於該第一導電層與該第二晶粒之主動面之上方，該等第二層間柱係設置於該第三導電層與該第一導電層之間，並且該等第二盲孔柱係設置於該第三導電層與該第二晶粒之對應金屬襯墊之間。
  9. 如請求項1之封裝結構，其中該導電結構包括複數個導線，各導線之一端接合於該第一導電層之第二表面，並且其另一端接合於與該第二晶粒之對應金屬襯墊，以傳遞該第二晶粒之訊號。
  10. 一種半導體裝置之封裝結構之製造方法，包括：提供一第一載板；於該第一載板上形成一具有相對設置之一第一表面與一第二表面之第一導電層；將複數個具有相對設置之一主動面與一背面之第一晶粒，以其背面接置於該第一導電層之第一表面；形成一第一介電層，並且包覆該等第一晶粒與該第一導電層；於該第一介電層中形成複數個第一盲孔，以分別暴露出該等第一晶粒之主動面之對應金屬襯墊；於該第一介電層上形成一具有相對設置之一第一表面與一第二表面之第二導電層，該第二導電層並向下填充該等第一盲孔而形成複數個第一盲孔柱；形成一第二介電層，並且包覆該第二導電層，以形成一封裝結構半成品；上、下翻轉上述該封裝結構半成品，並於翻轉後之該第二介電層之下方接置一第二載板，再移除該第一載板；將複數個具有相對設置一主動面與一背面之第二晶粒以其背面接置於該第一導電層之第二表面； 形成一導電結構，以電性連接該第一導電層與該等第二晶粒之主動面之對應金屬襯墊；形成一第三介電層，並且包覆該等第一導電層、第二晶粒與該導電結構；移除該第二載板；以及切割該封裝結構成為複數個封裝單元。
  11. 如請求項10之製造方法，其中該第一載板與該第二載板之面積係為單一晶圓之複數倍，並且該等第一晶粒與第二晶粒係切割自複數個晶圓。
  12. 如請求項10之製造方法，其中該第二晶粒係一主動面具有感應區域之光學感測晶片，且選擇性的於該第三介電層形成一開口以暴露出該感測區域。
  13. 如請求項10之製造方法，其中於該等第一晶粒與該第一導電層上形成一第一介電層之步驟前，更包括：於該第一導電層之表面形成複數個第一層間柱之步驟，該等第一層間柱係連接於後續形成之該第二導電層。
  14. 如請求項10之製造方法，其中於該第一介電層上形成該第二導電層之步驟後，更包括：於該第二導電層之第一表面形成複數個導電柱之步驟，並可於該封裝結構製造完成後，將該等導電柱分別連接於複數個對應之外部導電凸塊。
  15. 如請求項10之製造方法，其中形成該導電結構之步驟係包括形成複數個第二層間柱、一第三導電層及複數個第二盲孔柱以構成一重佈層線路之步驟，以將該等第二晶粒之該等金屬襯墊電性連接於該第一導電層。
  16. 如請求項15之製造方法，其中形成該等第二層間柱、該第三導電層及該等第二盲孔柱之步驟包括：於該第一導電層之第二表面形成該等第二層間柱；形成一第三介電層，並且包覆該第一導電層、該等第二晶粒以及該等第二層間柱；於該第三介電層中形成複數個第二盲孔，以分別暴露出該等第 二晶粒之對應金屬襯墊；以及於該第三介電層上形成該第三導電層，該第三導電層並向下填充該等第二盲孔而形成該等第二盲孔柱，其中該第三導電層連接該等第二層間柱。
  17. 如請求項10之製造方法，其中形成該導電結構之步驟係包括執行打線工序，以將複數個導線之一端接合於該第一導電層之第二表面，並將其另一端接合於與該等第二晶粒之主動面之對應金屬襯墊。
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