CN111863638A - 一种半导体芯片上表面感应区外露的封装方法 - Google Patents

一种半导体芯片上表面感应区外露的封装方法 Download PDF

Info

Publication number
CN111863638A
CN111863638A CN202010678688.4A CN202010678688A CN111863638A CN 111863638 A CN111863638 A CN 111863638A CN 202010678688 A CN202010678688 A CN 202010678688A CN 111863638 A CN111863638 A CN 111863638A
Authority
CN
China
Prior art keywords
chip
polymer material
front surface
encapsulating layer
packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN202010678688.4A
Other languages
English (en)
Inventor
顾俊晔
付贵平
胡健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Xinyan Industrial Co Ltd
Original Assignee
Shanghai Xinyan Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Xinyan Industrial Co Ltd filed Critical Shanghai Xinyan Industrial Co Ltd
Publication of CN111863638A publication Critical patent/CN111863638A/zh
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3185Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明公开了一种半导体芯片上表面感应区外露的封装方法,尤其涉及一种芯片需要正面有小区外露于封装体的封装方式及结构。芯片表面预置光刻胶或其他高分子材料保护芯片表面的感应区功能区;通过引线键合工艺实现芯片与基材的电气连接;通过注塑工艺行程包封成;机械研磨包封层上表面,使其厚度达到要求,同时芯片表面预置的光刻胶或其他高分子材料外露于包封层;或者通过注塑模具在注塑成形时,使芯片上的高分子材料外露于包封层;通过化学药水或物理外力去除光刻胶或其他高分子材料,使芯片表面感应区外露与封装体。从而达到芯片正面感应区外露于封装体的封装方式及结构,同时优化了封装工艺,极大地降低了成本。

Description

一种半导体芯片上表面感应区外露的封装方法
技术领域
本发明涉及一种芯片正面感应区外露于封装体的封装方式,属于半导体技术领域。
背景技术
半导体芯片的应用在各行各业中的应用越来越广,应用越来越复杂,尤其是一些传感器芯片的应用。例如:指纹芯片或光学传感器芯片的应用,此种芯片的封装需要将芯片的感应区域外露于封装体表面,以便光信号的传输。
目前的封装过程中需要用到异形模具进行塑封,才能使芯片表面外露于封装体表面。但是异形模具在注塑成形时,需要很大的压力作用在芯片表面,损坏芯片的风险很高。同时异形模具应用灵活性很差,芯片的不同设计,需要不同的异形模具的开发,致使封装成本非常高昂。
发明内容
本发明的目的是:降低对异形模具的依赖,减少封装过程中损伤芯片的风险,同时极大降低芯片外露的封装成本。
为了达到上述目的,本发明的技术方案是提供了一种半导体芯片上表面感应区外露的封装方法,其特征在于,包括以下步骤:
步骤S1、将高分子材料预置于芯片正面后,对芯片正面进行曝光显影,使得仅预置在芯片正面功能区的高分子材料得到保留,使得芯片正面焊盘外露,从而实现对芯片正面功能区的保护,或者仅将高分子材料直接预置在芯片正面的功能区,使得芯片正面焊盘外露,从而实现对芯片正面功能区的保护;
步骤S2、通过步骤1得到预处理后的芯片,预处理后的芯片背面通过高分子粘结材料与基材或者基材上的金属焊盘结合;
步骤S3、采用引线键合工艺使金属引线连接芯片正面的焊盘和基材上预制的金属管脚模块;
步骤S4、通过注塑成形工艺,将芯片、引线、金属管脚模块和/或金属焊盘以及芯片正面功能区的高分子材料和芯片背面的高分子粘接材料包封,形成包封层;或者将芯片正面功能区的高分子材料和芯片背面的高分子粘接材料包封,形成包封层,包封层与基材保持结合,形成统一的封装体;或者用注塑模具在注塑成形时,模具腔体上表面直接与芯片正面功能区的高分子材料接触从而使注塑树脂不能注塑到高分子材料表面,形成包封层后,芯片上的高分子材料直接外露于包封层,此时,跳过步骤S5,直接进入步骤S6;
步骤S5、通过机械研磨方式减薄包封层,直至包封层厚度达到要求,同时使预置在芯片上的高分子材料外露于包封层;
步骤S6、通过化学药水去除正面功能区的高分子材料,使芯片正面功能区外露于包封层。
优选地,所述基材为印刷线路板、基板、引线框架、或带有电路的不锈钢板。
优选地,步骤S1中,对芯片正面进行曝光显影时,先在芯片正面旋转涂布一层湿式高分子材料或者贴干式高分子材料,然后再进行曝光显影,仅保留芯片正面功能区域上面的湿式高分子材料或干式高分子材料,去除位于芯片其他部分的多余部分的湿式高分子材料或干式高分子材料。
优选地,步骤S1中,仅将高分子材料直接预置在芯片正面的功能区时,通过丝网印刷工艺将液体状高分子材料印刷到芯片正面的功能区上面。
优选地,步骤S3中,通过所述金属引线连接所述芯片和所述金属管脚模块时,所述金属引线的线弧高度不超过所述芯片正面功能区的高分子材料的高度。
优选地,步骤S5中,通过机械研磨方式减薄包封层至预置在芯片正面功能区的高分子材料外露于包封层,并研磨到所述金属引线的线弧高度以上。
优选地,所述金属管脚模块和/或所述金属焊盘由金、镍、银、铜、钯、锡中的任意一种金属制成,或由金、镍、银、铜、钯、锡中的一种以上的金属叠层组成。
优选地,步骤S6中,所述芯片正面功能区的高度低于所述包封层上表面,形成天井式的凹槽结构;包封材料填充至芯片正面边缘,最大程度保护芯片,实现高作业性和高可靠性。
优选地,步骤S6中,所述化学药水采用中性Ph值的化学药水,达到去除预置在芯片正面功能区的高分子材料的同时,不损伤芯片正面的功能区和/或所述金属焊盘。
本发明在芯片表面预置一种光刻胶或其他高分子材料,将芯片正面有效区域保护起来,从而避免了在封装过程中损伤芯片。并且本发明提供的封装方法不需要使用异形模具的依赖,采用成熟的工艺就可以实现本发明的封装方法,从而极大地降低了芯片外露的封装成本。
附图说明
图1为芯片外观的侧视图及外观结构示意图;
图2为芯片上表面预置光刻胶或其他高分子材料侧视图及结构示意图。
图3为芯片预处理后的侧视图及结构示意图;
图4为芯片预处理后通过粘接材料放置在基材上的侧视图及结构示意图;
图5为芯片表面焊盘通过金属引线连接到基材上金属管脚模块的侧视图及结构示意图;
图6为采用注塑成形工艺,通过树脂将芯片、管脚或线路、焊盘、芯片表面预置的光刻胶或高分子材料、芯片背面的粘接材料及引线包裹形成包封层的侧视图及结构示意图;
图7为通过机械研磨工艺打磨减薄包封层上表面,使包封层厚度达到要求,且芯片上表面的光刻胶或其他高分子材料外露在包封层的侧视图及结构示意图;
图8为去除芯片上表面的光刻胶或其他高分子材料后的侧视图及结构示意图;
图9为通过注塑成形后通过树脂将芯片、芯片表面预置的光刻胶或高分子材料、芯片背面的粘接材料及引线包裹形成包封层,包封层与印刷线路板或陶瓷基板结合的侧视图及结构示意图;
图10为通过机械研磨工艺打磨减薄包封层上表面,使包封层厚度达到要求,且芯片上表面的光刻胶或其他高分子材料外露在包封层,并去除芯片上表面的光刻胶或其他高分子材料后的侧视图及结构示意图;
图11为本发明专利申请的实施方式的工序流程示意图。
具体实施方式
下面结合具体实施例,进一步阐述本发明。应理解,这些实施例仅用于说明本发明而不用于限制本发明的范围。此外应理解,在阅读了本发明讲授的内容之后,本领域技术人员可以对本发明作各种改动或修改,这些等价形式同样落于本申请所附权利要求书所限定的范围。
如图11所示,本发明提供的一种半导体芯片上表面感应区外露的封装方法包括以下步骤:
步骤S1:如图2所示,在如图1所示的正面有金属焊盘2的芯片1的正面有效区域预置光刻胶或其他高分子材料3,将芯片1正面有效区域保护起来。例如可以在芯片1表面旋转涂布一层湿式光刻胶或其他高分子材料或者贴干式光刻胶或其他高分子材料3。
如图3所示,然后进行曝光显影,仅保留芯片1正面的有效区域上面的光刻胶或其他高分子材料3,去除多余部分的光刻胶或其他高分子材料。
或者通过丝网印刷工艺,直接将液体状光刻胶或其他高分子材料3印刷到芯片1正面的有效区域上面。
步骤S1的作用是使芯片1正面的金属焊盘2外露,以便进行后续的引线键合工艺。同时保护了芯片1正面的有效区域。
步骤S2:如图4所示,通过粘接材料8将芯片1背面与基材上的金属焊盘5结合。粘接材料8可为高分子材料、银浆、或胶水。
步骤S3:如图5所述,采用引线键合的方式利用金属引线6连接芯片1正面的金属焊盘2与框架基材的金属管脚模块4的上表面,实现电气连接。
步骤S4:如图6所示,通过注塑成形,将芯片1、金属引线6、金属管脚模块4、金属焊盘2、金属焊盘5及芯片1正面有效区域的光刻胶或其他高分子材料3和芯片1背面的高分子粘接材料8包封,形成包封层7。
或者如图9所示,将芯片1、金属引线6、芯片1正面有效区域的光刻胶或其他高分子材料3和芯片1背面的高分子粘接材料8包封,形成包封层7,包封层7与基材保持结合,形成统一的封装体。
步骤S5:如图7所示,通过机械研磨的方式打磨减薄包封层7上表面至所需的厚度,同时预置在芯片1正面的光刻胶或其他高分子材料3外露于包封层7。或者用注塑模具在注塑成形时,模具腔体上表面直接与芯片1正面功能区的高分子材料3接触从而使注塑树脂不能注塑到高分子材料表面,使芯片上的高分子材料外露于包封层;
步骤S6:如图8所示,通过化学药水或者物理外力将预置在芯片1正面的光刻胶或其他高分子材料3去除。化学药水不限制酸碱度,中性为最佳。以不损伤破坏芯片表面为准。

Claims (9)

1.一种半导体芯片上表面感应区外露的封装方法,其特征在于,包括以下步骤:
步骤S1、将高分子材料预置于芯片正面后,对芯片正面进行曝光显影,使得仅预置在芯片正面功能区的高分子材料得到保留,使得芯片正面焊盘外露,从而实现对芯片正面功能区的保护,或者仅将高分子材料直接预置在芯片正面的功能区,使得芯片正面焊盘外露,从而实现对芯片正面功能区的保护;
步骤S2、通过步骤1得到预处理后的芯片,预处理后的芯片背面通过高分子粘结材料与基材或者基材上的金属焊盘结合;
步骤S3、采用引线键合工艺使金属引线连接芯片正面的焊盘和基材上预制的金属管脚模块;
步骤S4、通过注塑成形工艺,将芯片、引线、金属管脚模块和/或金属焊盘以及芯片正面功能区的高分子材料和芯片背面的高分子粘接材料包封,形成包封层;或者将芯片正面功能区的高分子材料和芯片背面的高分子粘接材料包封,形成包封层,包封层与基材保持结合,形成统一的封装体;或者用注塑模具在注塑成形时,模具腔体上表面直接与芯片正面功能区的高分子材料接触从而使注塑树脂不能注塑到高分子材料表面,形成包封层后,芯片上的高分子材料直接外露于包封层,此时,跳过步骤S5,直接进入步骤S6;
步骤S5、通过机械研磨方式减薄包封层,直至包封层厚度达到要求,同时使预置在芯片上的高分子材料外露于包封层;
步骤S6、通过化学药水去除正面功能区的高分子材料,使芯片正面功能区外露于包封层。
2.如权利要求1所述的一种半导体芯片上表面感应区外露的封装方法,其特征在于,所述基材为印刷线路板、基板、引线框架、或带有电路的不锈钢板。
3.如权利要求1所述的一种半导体芯片上表面感应区外露的封装方法,其特征在于,步骤S1中,对芯片正面进行曝光显影时,先在芯片正面旋转涂布一层湿式高分子材料或者贴干式高分子材料,然后再进行曝光显影,仅保留芯片正面功能区域上面的湿式高分子材料或干式高分子材料,去除位于芯片其他部分的多余部分的湿式高分子材料或干式高分子材料或液体状高分子材料。
4.如权利要求1所述的一种半导体芯片上表面感应区外露的封装方法,其特征在于,步骤S1中,仅将高分子材料直接预置在芯片正面的功能区时,通过丝网印刷工艺将液体状高分子材料印刷到芯片正面的功能区上面。
5.如权利要求1所述的一种半导体芯片上表面感应区外露的封装方法,其特征在于,步骤S3中,通过所述金属引线连接所述芯片和所述金属管脚模块时,所述金属引线的线弧高度不超过所述芯片正面功能区的高分子材料的高度。
6.如权利要求5所述的一种半导体芯片上表面感应区外露的封装方法,其特征在于,步骤S5中,通过机械研磨方式减薄包封层至预置在芯片正面功能区的高分子材料外露于包封层,并研磨到所述金属引线的线弧高度以上。
7.如权利要求1所述的一种半导体芯片上表面感应区外露的封装方法,其特征在于,所述金属管脚模块和/或所述金属焊盘由金、镍、银、铜、钯、锡中的任意一种金属制成,或由金、镍、银、铜、钯、锡中的一种以上的金属叠层组成。
8.如权利要求1所述的一种半导体芯片上表面感应区外露的封装方法,其特征在于,步骤S6中,所述芯片正面功能区的高度低于所述包封层上表面,形成天井式的凹槽结构;包封材料填充至芯片正面边缘,最大程度保护芯片,实现高作业性和高可靠性。
9.如权利要求1所述的一种半导体芯片上表面感应区外露的封装方法,其特征在于,步骤S6中,所述化学药水采用中性Ph值的化学药水,达到去除预置在芯片正面功能区的高分子材料的同时,不损伤芯片正面的功能区和/或所述金属焊盘。
CN202010678688.4A 2020-07-09 2020-07-15 一种半导体芯片上表面感应区外露的封装方法 Withdrawn CN111863638A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2020106559700 2020-07-09
CN202010655970 2020-07-09

Publications (1)

Publication Number Publication Date
CN111863638A true CN111863638A (zh) 2020-10-30

Family

ID=72983516

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010678688.4A Withdrawn CN111863638A (zh) 2020-07-09 2020-07-15 一种半导体芯片上表面感应区外露的封装方法

Country Status (1)

Country Link
CN (1) CN111863638A (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070222008A1 (en) * 2006-03-22 2007-09-27 Industrial Technology Research Institute Method for manufacturing plastic packaging of mems devices and structure thereof
CN108183091A (zh) * 2017-12-28 2018-06-19 江苏长电科技股份有限公司 一种封装结构及其工艺方法
CN108206170A (zh) * 2017-12-29 2018-06-26 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
US20200075565A1 (en) * 2018-08-29 2020-03-05 Phoenix & Corporation Package structure for semiconductor device and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070222008A1 (en) * 2006-03-22 2007-09-27 Industrial Technology Research Institute Method for manufacturing plastic packaging of mems devices and structure thereof
CN108183091A (zh) * 2017-12-28 2018-06-19 江苏长电科技股份有限公司 一种封装结构及其工艺方法
CN108206170A (zh) * 2017-12-29 2018-06-26 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
US20200075565A1 (en) * 2018-08-29 2020-03-05 Phoenix & Corporation Package structure for semiconductor device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
KR100460063B1 (ko) 센터 패드 칩 적층 볼 그리드 어레이 패키지 및 그 제조방법
CN106169466A (zh) 半导体封装组件及其制造方法
EP1984949A2 (en) A sip module with a single sided lid
US20070080435A1 (en) Semiconductor packaging process and carrier for semiconductor package
JP3449796B2 (ja) 樹脂封止型半導体装置の製造方法
KR100924554B1 (ko) 플립 칩 패키지 및 이의 제조 방법
KR100800475B1 (ko) 적층형 반도체 패키지 및 그 제조방법
US20070026573A1 (en) Method of making a stacked die package
US20080197466A1 (en) Semiconductor device and manufacturing method thereof
US20040150088A1 (en) Semiconductor die package
KR100295731B1 (ko) 전자패키지의제조방법
CN212392240U (zh) 扇出型封装结构
US20040084758A1 (en) Semiconductor package with lead frame as chip carrier and method for fabricating the same
KR20030083306A (ko) 메모리 카드
JP2000293651A (ja) 半導体装置
CN111863638A (zh) 一种半导体芯片上表面感应区外露的封装方法
EP1627430B1 (en) An integrated circuit package employing a flexible substrate
US11404361B2 (en) Method for fabricating package structure having encapsulate sensing chip
CN213184260U (zh) 一种芯片的封装结构
CN215798501U (zh) 微机电系统器件的封装结构
CN111863634B (zh) 超薄封装结构的制作方法
CN111863639A (zh) 一种芯片的封装方法
CN111863637A (zh) 一种半导体芯片的封装方法
CN212392241U (zh) 扇出型封装结构
CN210429792U (zh) 一种电子设备

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication
WW01 Invention patent application withdrawn after publication

Application publication date: 20201030