CN210429792U - 一种电子设备 - Google Patents

一种电子设备 Download PDF

Info

Publication number
CN210429792U
CN210429792U CN201921162418.7U CN201921162418U CN210429792U CN 210429792 U CN210429792 U CN 210429792U CN 201921162418 U CN201921162418 U CN 201921162418U CN 210429792 U CN210429792 U CN 210429792U
Authority
CN
China
Prior art keywords
contacts
bond pad
semiconductor die
electronic device
support structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201921162418.7U
Other languages
English (en)
Inventor
F·富利奥
M·塔比拉
E·小格莱科奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
STMicroelectronics Inc Philippines
Original Assignee
STMicroelectronics Inc Philippines
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Inc Philippines filed Critical STMicroelectronics Inc Philippines
Application granted granted Critical
Publication of CN210429792U publication Critical patent/CN210429792U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772Physical layout of the record carrier
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • H01L2224/49173Radial fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking

Abstract

本公开涉及一种电子设备。微型模块包括具有触点和键合焊盘的载体基板、半导体管芯以及支撑结构。半导体管芯位于键合焊盘上并且电耦合到触点。支撑结构位于键合焊盘上并且与半导体管芯相邻。支撑结构加强了键合焊盘,使得键合焊盘比柔性更硬。结果,施加到微型模块的外力不太可能导致微型模块弯曲并且损坏半导体管芯。

Description

一种电子设备
技术领域
本公开涉及微型模块,诸如订户身份模块(SIM)。
背景技术
订户身份模块(SIM)用于各种应用,诸如为安全产品和移动设备提供用户信息。SIM通常包括半导体管芯和电耦合到半导体管芯的多个触点。
SIM通常嵌入或容纳在卡本体中,卡本体通常称为集成电路卡或 SIM卡。当嵌入卡本体中时,SIM的半导体管芯的信号通过触点被带到卡本体的表面。例如,当集成电路卡插入主机设备(例如,计算机、安全设备、移动电话等)中的读卡器时,触点将物理地接触读卡器的卡触点并且因此将SIM的半导体管芯电耦合到主机设备。
由于SIM卡嵌入其中的卡本体很薄,因此SIM本身非常薄并且比刚性更柔性。因此,SIM通常易碎并且易于损坏。例如,由于SIM 的柔性,当在传输期间将外力施加到SIM时,SIM可能无意地弯曲,并且机械应力可能导致SIM的半导体管芯破裂。类似地,当SIM卡重复插入读卡器时,SIM的半导体管芯可能会由于读卡器的卡触点施加的压力而破裂。
实用新型内容
本公开的目的是提供一种电子设备,以至少部分地解决现有技术中存在的上述问题。
根据一个方面,提供了一种电子设备,包括:键合焊盘;多个触点;在所述键合焊盘和所述多个触点上的绝缘层,所述绝缘层包括暴露所述键合焊盘的表面的第一开口和暴露所述多个触点的表面的多个第二开口;在所述键合焊盘的所述表面上的半导体管芯;在所述键合焊盘的所述表面上的支撑结构;以及多个导线,将所述半导体管芯电耦合到所述多个触点,所述多个导线从所述半导体管芯延伸到所述多个触点的所述表面。
根据一个实施例,其中所述支撑结构比所述键合焊盘更硬。
根据一个实施例,其中所述绝缘层是载带。
根据一个实施例,其中所述支撑结构由玻璃制成。
根据一个实施例,其中所述多个触点中的至少一个触点电耦合到所述键合焊盘。
根据一个实施例,其中所述键合焊盘和所述多个触点彼此电隔离。
根据一个实施例,其中所述绝缘层是单个连续层。
根据一个实施例,其中所述键合焊盘的厚度小于50微米。
根据一个实施例,还包括:卡本体,所述载体基板、所述半导体管芯、所述支撑结构和所述导线被嵌入所述卡本体中。
根据一个实施例,其中所述半导体管芯覆盖所述第一表面的小于 50%。
根据一个方面,提供了一种电子设备,包括:载体基板,包括键合焊盘和多个触点;在所述载体基板上的绝缘层,所述绝缘层包括暴露所述键合焊盘的开口;在所述键合焊盘上并且在所述开口中的半导体管芯;在所述键合焊盘上并且在所述开口中的支撑基板;以及多个导线,将所述半导体管芯电耦合到所述多个触点。
根据一个实施例,其中所述多个触点包括第一组触点和第二组触点,并且所述键合焊盘被定位于所述第一组触点与所述第二组触点之间。
根据一个实施例,其中所述半导体管芯和所述支撑基板被直接附接到所述键合焊盘。
根据一个实施例,其中所述键合焊盘和所述多个触点基本上共面。
根据一个实施例,其中所述支撑基板是玻璃基板。
本公开涉及一种具有支撑结构的微型模块,该支撑结构增加了微型模块的整体强度并且防止微型模块内的半导体管芯破裂。
微型模块包括具有触点和键合焊盘的载体基板、半导体管芯以及支撑结构。半导体管芯位于键合焊盘上并且电耦合到触点。半导体管芯可以是任何类型的集成电路,并且可以包括任何数目的电子组件 (例如,存储器、处理器、电容器、晶体管、电阻器等)。支撑结构位于键合焊盘上并且与半导体管芯相邻。支撑结构为微型模块提供附加支撑,并且对施加到微型模块的任何压力释放应力。换言之,支撑结构加强了键合焊盘,使得键合焊盘比柔性更硬。结果,施加到微型模块的外力不太可能导致微型模块弯曲并且不太可能导致半导体管芯的损坏。
附图说明
在附图中,相同的附图标记表示相似的特征或元素。附图中的特征的尺寸和相对位置不一定按比例绘制。
图1是根据本公开的实施例的卡;
图2是根据本公开的实施例的微型模块的接触侧的放大视图;
图3是根据本公开的实施例的微型模块的键合侧的放大视图;
图4是根据本公开的实施例的沿着图3所示的轴的微型模块的横截面视图;以及
图5是根据本公开的实施例的制造微型模块的方法的流程图。
具体实施方式
在以下描述中,阐述了某些具体细节以便提供对所公开的主题的各个方面的透彻理解。然而,可以在没有这些具体细节的情况下实践所公开的主题。在一些情况下,没有详细描述电子设备、订户身份模块(SIM)和集成电路卡的公知结构和制造方法,以避免模糊对本公开的其他方面的描述。
除非上下文另有要求,否则在整个说明书和随后的权利要求中,词语“包括(comprise)”及其变体(诸如“包括(comprises)”和“包括(comprising)”)应当以开放的包含性的意义解释,即“包括但不限于”。
整个说明书中对“一个实施例”或“实施例”的引用表示结合该实施例描述的特定特征、结构或特性被包括在至少一个实施例中。因此,在整个说明书中各处出现的短语“在一个实施例中”或“在实施例中”不一定都指代同一方面。此外,特定特征、结构或特性可以在本公开的一个或多个方面中以任何合适的方式组合。
整个说明书中对集成电路的引用通常旨在包括构建在半导体或玻璃基板上的集成电路部件,无论这些部件是否一起耦合到电路中或能够互连。在整个说明书中,术语“层”以其最广泛的含义使用,包括薄膜、帽等,并且一个层可以由多个子层组成。
本公开涉及一种包括支撑结构的微型模块,诸如SIM。
图1是根据本公开的实施例的卡10。卡10是容纳微型模块的集成电路卡。卡10包括卡本体12和微型模块14。
卡本体12容纳微型模块14。在一个实施例中,卡本体12由诸如塑料等绝缘材料制成。在一个实施例中,如图1所示,卡本体12具有信用卡的尺寸和形状。然而,应当注意,卡本体12可以具有各种不同的尺寸和形状。例如,卡本体12可以具有完整SIM、微型SIM、纳米SIM等的尺寸和形状。
微型模块14嵌入在卡本体12中。微型模块14是提供卡10的功能的电子设备。在一个实施例中,微型模块14是SIM。在一个实施例中,微型模块14用于提供标识和/或认证信息以用于安全目的。如下面将进一步详细讨论的,微型模块14包括硅管芯和电耦合到硅管芯的多个触点。
如图1所示,微型模块14的接触侧16保持从卡本体12暴露。这样,当卡本体12插入主机设备(例如,计算机、安全设备、移动电话等)的读卡器中时,读卡器的卡触点可以物理地接触微型模块14 的触点,并且因此将微型模块14的半导体管芯电耦合到主机设备。结果,可以在微型模块14的半导体管芯与主机设备之间传输信号。
图2是根据本公开的实施例的微型模块14的接触侧16的放大视图。图3是根据本公开的实施例的微型模块14的与接触侧16相对的键合侧17的放大视图。图4是根据本公开的实施例的沿着图3所示的轴的微型模块14的横截面图。应当注意,在图2至图4中移除了卡本体12。这对一起回顾图2至图4是有益的。
微型模块14包括载体基板18、绝缘层20、半导体管芯22、支撑结构24和保护层26。
载体基板18支撑半导体管芯22和支撑结构24,并且提供半导体管芯22与外部电子设备(诸如计算机和移动设备)之间的电连接。载体基板18包括触点28和键合焊盘30。
触点28为微型模块14提供接触焊盘。每个触点28包括在接触侧16的第一表面32、以及与第一表面32相对并且在键合侧17的第二表面34。如图1最佳所示,当微型模块14嵌入卡本体12中时,触点28的第一表面32从卡本体12暴露。因此,当卡本体12插入主机设备的读卡器中时,读卡器的卡触点能够物理地接触第一表面32。如下面将进一步详细讨论的,触点28的第二表面34容纳导线以将触点 28和半导体管芯22电耦合在一起。应当注意,尽管图2中示出了六个触点28,但微型模块14可以包括任何数目的触点。
在一个实施例中,触点28彼此电隔离,使得触点28可以承载相应信号。在一个实施例中,触点28中的至少一个耦合到键合焊盘30。例如,如图2最佳所示,触点36电耦合到键合焊盘30。在一个实施例中,使用触点36作为地。
在一个实施例中,触点28电耦合到微型模块14内或微型模块14 外部的其他各种电子组件(例如,存储器、处理器、电容器、晶体管、电阻器等)。例如,如图2最佳所示,触点28可以经由绝缘层20上的电连接37电耦合到各种电子组件。
键合焊盘30为半导体管芯22和支撑结构24提供支撑。键合焊盘30包括在接触侧16的第一表面38和与第一表面38相对并且在键合侧17的第二表面40。如图1最佳所示,当微型模块14嵌入卡本体 12中时,键合焊盘30的第一表面38从卡本体12暴露。如下面将进一步详细讨论的,第二表面40容纳半导体管芯22和支撑结构24。
在一个实施例中,如图4所示,键合焊盘30与触点28基本共面。
如前所述,在一个实施例中,键合焊盘30与一个或多个触点28 电隔离。在一个实施例中,触点28中的至少一个(例如,触点36) 耦合到键合焊盘30。
在一个实施例中,包括触点28和键合焊盘30的载体基板18由导电材料制成。在一个实施例中,触点28和键合焊盘30由相同的材料制成。在一个实施例中,触点28和键合焊盘30由不同的材料制成。
在一个实施例中,包括触点28和键合焊盘30的载体基板18具有小的厚度,以便将微型模块14嵌入到卡本体12中。在一个实施例中,载体基板18的厚度t1小于50微米。在一个实施例中,载体基板 18的厚度t1在25到35微米之间。
绝缘层20位于载体基板18上。绝缘层20为包括触点28和键合焊盘30的载体基板18提供基板。此外,如图2最佳所示,绝缘层20 为耦合到触点28的任何电连接37提供基板。如前所述,在一个实施例中,触点28电耦合到微型模块14内或微型模块14外部的其他各种电子组件(例如,处理器、电容器、晶体管、电阻器等)。绝缘层 20可以由任何类型的绝缘材料制成。在一个实施例中,绝缘层20是载带。在一个实施例中,绝缘层20是单个连续层。
绝缘层20包括在微型模块14的键合侧17上的多个开口。具体地,如图3和4最佳所示,绝缘层20包括直接覆盖并且暴露触点28 的第二表面34的触点开口42、以及直接覆盖并且暴露键合焊盘30 的第二表面40的键合焊盘开口44。触点开口42和键合焊盘开口44 相对于微型模块14的接触侧16的位置在图2中示出为虚线轮廓。
触点28的第二表面34的由触点开口42暴露的部分用作引线键合区域46。如下面将进一步详细讨论的,每个引线键合区域46容纳将半导体管芯22电耦合到触点28的导线48的一端。
绝缘层20可以包括任何数目的触点开口42。例如,绝缘层20可以包括直接覆盖相应触点的2、3或4个触点开口。在一个实施例中,绝缘层20包括用于每个触点28的相应触点开口。例如,如图3最佳所示,绝缘层20包括用于六个触点28的六个开口。
触点开口42可以具有任何形状和尺寸。在一个实施例中,如图3 最佳所示,每个触点开口42具有圆形形状。在一个实施例中,触点开口42的尺寸适于至少容纳导线48的一端。
键合焊盘30的第二表面40的通过键合焊盘开口44暴露的部分用作管芯键合区域50。管芯键合区域50有时被称为腔体键合区域。如下面将进一步详细讨论的,管芯键合区域50容纳半导体管芯22和支撑结构24。
键合焊盘开口44可以具有任何形状和尺寸。在一个实施例中,如图3最佳所示,键合焊盘开口44具有矩形形状。在一个实施例中,键合焊盘开口的尺寸适于至少容纳半导体管芯22和支撑结构24。
半导体管芯22耦合到键合焊盘30。具体地,半导体管芯22在管芯键合区域50中耦合到键合焊盘30的第二表面40。在一个实施例中,半导体管芯22在管芯键合区域50中直接附接到键合焊盘30的第二表面40。例如,如图4所示,半导体管芯22通过粘合剂52附接到键合焊盘30的第二表面40。粘合剂52可以是任何类型的粘合剂,诸如管芯附接环氧树脂。
半导体管芯22电耦合到触点28。在一个实施例中,如图3和4 最佳所示,半导体管芯22经由导线48电耦合到触点28。即,每个导线具有耦合到半导体管芯22的第一端和耦合到相应触点28的引线键合区域46的第二端。如前所述,如图1最佳所示,当微型模块14嵌入在卡本体12中时,触点28的第一表面32从卡本体12暴露。因此,当卡本体12插入主机设备中的读卡器时,读卡器的卡触点可以物理地接触微型模块14的触点,从而将半导体管芯22电耦合到主机设备。结果,可以在半导体管芯22与主机设备之间传输信号。
半导体管芯22可以是任何类型的集成电路,并且可以包括任何数目的电子组件(例如,存储器、处理器、电容器、晶体管、电阻器等)。在一个实施例中,半导体管芯22提供识别和/或认证信息以用于安全目的。
支撑结构24耦合到键合焊盘30并且与半导体管芯22相邻。具体地,支撑结构24在管芯键合区域50中耦合到键合焊盘30的第二表面40。在一个实施例中,支撑结构24在管芯键合区域50中直接附接到键合焊盘30的第二表面40。例如,如图4所示,支撑结构24 通过粘合剂54附接到键合焊盘30的第二表面40。粘合剂54可以是任何类型的粘合剂,诸如管芯附接环氧树脂。
如前所述,在一个实施例中,载体基板18具有小的厚度(例如,小于50微米厚)。由于载体基板18的薄的厚度,载体基板18、特别是键合焊盘30趋于比刚性更柔性。因此,半导体管芯22易于在运输期间或正常使用期间受损。例如,在运输期间无意地施加到微型模块14的外力可能导致载体基板18弯曲并且导致半导体管芯22破裂。类似地,当卡10重复插入读卡器时,由于读卡器的卡触点施加到触点 28的压力,载体基板18可能弯曲并且半导体管芯22可能破裂。当半导体管芯22本身很薄和/或相对较小时,载体基板18的柔性进一步恶化。例如,当半导体管芯22的厚度小于150微米时,和/或当半导体管芯22覆盖键合焊盘30的第二表面40的表面区域的相对较小的部分(例如,小于50%)时,载体基板18特别容易弯曲。
为了防止对半导体管芯22的这种损坏,支撑结构24由刚性材料制成并且邻近半导体管芯22定位。在一个实施例中,支撑结构24比载体基板18、具体地比键合焊盘30和/或接触件28更硬。也就是说,支撑结构24能够在破裂之前承受比载体基板18更大的压力或力。在一个实施例中,当键合焊盘30的中心最容易弯曲时,支撑结构24位于键合焊盘30的中心处或附近。
支撑结构24为微型模块14提供附加支撑,并且对施加到微型模块14的任何压力提供应力消除。换言之,支撑结构24加强了键合焊盘30以增加键合焊盘30的刚度。结果,施加到微型模块14的外力不太可能导致微型模块14弯曲并且损坏半导体管芯22。在一个实施例中,支撑结构24为微型模块14提供附加支撑,使得微型模块14 能够承受至少6牛顿的压力而不会被损坏(例如,在半导体管芯22 或保护层26中形成裂缝)。
因此,支撑结构24增加了微型模块14的坚固性和可靠性。
在一个实施例中,支撑结构24由具有高热机械强度的材料制成。即,支撑结构24由即使在暴露于极端温度(例如,大于160摄氏度的推荐固化曲线的温度)时也能够保持其刚性和强度的材料制成。例如,在一个实施例中,支撑结构24由熔点温度为1400摄氏度的材料制成。在一个实施例中,支撑结构24是玻璃基板。在一个实施例中,支撑结构24是镜面硅晶片。
在一个实施例中,支撑结构24的最大高度等于半导体管芯22的高度。换言之,在一个实施例中,支撑结构24具有高度或厚度使得支撑结构24的上表面不延伸超过和高于半导体管芯22的上表面。例如,如图4最佳所示,支撑结构24具有的厚度(在竖直方向上)小于半导体管芯22的厚度,使得支撑结构24的顶表面位于半导体22 的顶表面下方。结果,支撑结构24将不会不必要地增加微型模块14 的总厚度。
在一个实施例中,支撑结构24覆盖键合焊盘30的第二表面40 的大部分表面区域以增加微型模块14的强度。例如,在一个实施例中,支撑结构24覆盖在键合焊盘30的第二表面40的30-50%。
支撑结构24可以是任何形状。在一个实施例中,如图3最佳所示,支撑结构24具有矩形形状。在一个实施例中,支撑结构24具有环形形状,并且半导体管芯22位于支撑结构24的中心。
应当注意,尽管图3和4中示出了单个支撑结构,但微型模块14 可以包括多个支撑结构以进一步增加微型模块14的强度。例如,在一个实施例中,微型模块14包括两个支撑结构,其中半导体管芯22 位于两个支撑结构之间。
保护层26形成在载体基板18、绝缘层20、半导体管芯22、支撑结构24和导线48上。应当注意,保护层26未在图3中示出。保护层26形成在键合侧17上,并且保护载体基板18、绝缘层20、半导体管芯22、支撑结构24和导线48免受损坏。在一个实施例中,保护层26由树脂材料制成。
图5是根据本公开的实施例的制造微型模块14的方法56的流程图。
在框58中,将半导体管芯定位在载体基板的第一表面上。例如,参考图2至4,半导体管芯22在载体基板18的管芯键合区域50中位于键合焊盘30的第二表面40上。
在框60中,将支撑结构定位在载体基板的第一表面上并且与半导体管芯相邻。例如,参考图2至图4,支撑结构24在承载基板18 的管芯键合区域50中耦合到键合焊盘30的第二表面40。在一个实施例中,当载体基板18的厚度小于50微米厚并且半导体管芯22覆盖键合焊盘30的第二表面40小于50%的表面积时,支撑结构24定位在承载基板18上。
在框62中,半导体管芯电耦合到载体基板的第二表面。例如,参考图2至图4,半导体管芯22经由导线48电耦合到触点28,导线 48在半导体管芯22与引线键合区域46之间延伸。
在框64中,在载体基板、半导体管芯和支撑结构上形成保护层。例如,参考图2至图4,保护层26形成在载体基板18、绝缘层20、半导体管芯22、支撑结构24和导线48上。
应当注意,尽管框58、60、62和64在图5中以依次顺序定位,但框58、60、62和64也可以以另一顺序执行。例如,框60可以在框58之前执行,框58和60可以同时执行,并且框58可以在框62 之后执行。
尽管上面关于微型模块(诸如SIM)讨论了支撑结构24,但是支撑结构可以包括在各种设备中,其中期望加强设备。
各种实施例提供了具有支撑结构的微型模块,该支撑结构增加了微型模块的整体强度。结果,微型模块不易受到封装破裂的影响,并且封装可靠性得到改善。
可以组合上述各种实施例以提供另外的实施例。根据以上详细描述,可以对实施例进行这些和其他改变。通常,在以下权利要求中,所使用的术语不应当被解释为将权利要求限制于说明书和权利要求中公开的特定实施例,而是应当被解释为包括所有可能的实施例以及这样的权利要求有权享有的等同物的全部范围。因此,权利要求不受本公开的限制。

Claims (15)

1.一种电子设备,其特征在于,包括:
键合焊盘;
多个触点;
在所述键合焊盘和所述多个触点上的绝缘层,所述绝缘层包括暴露所述键合焊盘的表面的第一开口和暴露所述多个触点的表面的多个第二开口;
在所述键合焊盘的所述表面上的半导体管芯;
在所述键合焊盘的所述表面上的支撑结构;以及
多个导线,将所述半导体管芯电耦合到所述多个触点,所述多个导线从所述半导体管芯延伸到所述多个触点的所述表面。
2.根据权利要求1所述的电子设备,其特征在于,其中所述支撑结构比所述键合焊盘更硬。
3.根据权利要求1所述的电子设备,其特征在于,其中所述绝缘层是载带。
4.根据权利要求1所述的电子设备,其特征在于,其中所述支撑结构由玻璃制成。
5.根据权利要求1所述的电子设备,其特征在于,其中所述多个触点中的至少一个触点电耦合到所述键合焊盘。
6.根据权利要求1所述的电子设备,其特征在于,其中所述键合焊盘和所述多个触点彼此电隔离。
7.根据权利要求1所述的电子设备,其特征在于,其中所述绝缘层是单个连续层。
8.根据权利要求1所述的电子设备,其特征在于,其中所述键合焊盘的厚度小于50微米。
9.根据权利要求1所述的电子设备,其特征在于,还包括:
卡本体,
载体基板,包括所述键合焊盘和所述多个触点,
所述载体基板、所述半导体管芯、所述支撑结构和所述导线被嵌入所述卡本体中。
10.根据权利要求1所述的电子设备,其特征在于,其中所述半导体管芯覆盖所述键合焊盘的所述表面的小于50%。
11.一种电子设备,其特征在于,包括:
载体基板,包括键合焊盘和多个触点;
在所述载体基板上的绝缘层,所述绝缘层包括暴露所述键合焊盘的开口;
在所述键合焊盘上并且在所述开口中的半导体管芯;
在所述键合焊盘上并且在所述开口中的支撑基板;以及
多个导线,将所述半导体管芯电耦合到所述多个触点。
12.根据权利要求11所述的电子设备,其特征在于,其中所述多个触点包括第一组触点和第二组触点,并且所述键合焊盘被定位于所述第一组触点与所述第二组触点之间。
13.根据权利要求11所述的电子设备,其特征在于,其中所述半导体管芯和所述支撑基板被直接附接到所述键合焊盘。
14.根据权利要求11所述的电子设备,其特征在于,其中所述键合焊盘和所述多个触点基本上共面。
15.根据权利要求11所述的电子设备,其特征在于,其中所述支撑基板是玻璃基板。
CN201921162418.7U 2018-07-25 2019-07-23 一种电子设备 Active CN210429792U (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862703193P 2018-07-25 2018-07-25
US62/703,193 2018-07-25
US16/458,559 2019-07-01
US16/458,559 US11088087B2 (en) 2018-07-25 2019-07-01 Micro module with a support structure

Publications (1)

Publication Number Publication Date
CN210429792U true CN210429792U (zh) 2020-04-28

Family

ID=69178663

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201921162418.7U Active CN210429792U (zh) 2018-07-25 2019-07-23 一种电子设备
CN201910667568.1A Pending CN110783297A (zh) 2018-07-25 2019-07-23 具有支撑结构的微型模块

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201910667568.1A Pending CN110783297A (zh) 2018-07-25 2019-07-23 具有支撑结构的微型模块

Country Status (2)

Country Link
US (1) US11088087B2 (zh)
CN (2) CN210429792U (zh)

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3541491B2 (ja) * 1994-06-22 2004-07-14 セイコーエプソン株式会社 電子部品
KR100255108B1 (en) * 1997-06-18 2000-05-01 Samsung Electronics Co Ltd Chip card
US6492717B1 (en) * 1999-08-03 2002-12-10 Motorola, Inc. Smart card module and method of assembling the same
US6876553B2 (en) * 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
JP2006507569A (ja) * 2002-09-17 2006-03-02 アクサルト ソシエテ アノニム ハイブリッドカード
US8586413B2 (en) * 2005-05-04 2013-11-19 Spansion Llc Multi-chip module having a support structure and method of manufacture
US7615487B2 (en) * 2007-03-15 2009-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Power delivery package having through wafer vias
US9634391B2 (en) * 2011-08-08 2017-04-25 Féinics Amatech Teoranta RFID transponder chip modules
EP2631849A1 (fr) * 2012-02-27 2013-08-28 Gemalto SA Procédé de fabrication d'un dispositif comprenant un module doté d'un circuit électrique et/ou électronique
US20140224882A1 (en) * 2013-02-14 2014-08-14 Douglas R. Hackler, Sr. Flexible Smart Card Transponder
US8669140B1 (en) * 2013-04-04 2014-03-11 Freescale Semiconductor, Inc. Method of forming stacked die package using redistributed chip packaging
US9167691B2 (en) * 2013-04-16 2015-10-20 Identive Group, Inc. Dual interface module and dual interface card having a dual interface module manufactured using laser welding
US9093337B2 (en) * 2013-09-27 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for controlling warpage in packaging
FR3021145B1 (fr) * 2014-05-14 2018-08-31 Linxens Holding Procede de fabrication d'un circuit pour module de carte a puce et circuit pour module de carte a puce
US9449912B1 (en) * 2015-06-11 2016-09-20 Stmicroelectronics Pte Ltd Integrated circuit (IC) card having an IC module and reduced bond wire stress and method of forming
EP3159831B1 (en) * 2015-10-21 2018-10-03 Nxp B.V. Dual-interface ic card
US20180151461A1 (en) * 2016-11-29 2018-05-31 Globalfoundries Inc. Stiffener for fan-out wafer level packaging and method of manufacturing
WO2019045638A1 (en) * 2017-08-28 2019-03-07 Smartflex Technology Pte Ltd INTEGRATED CIRCUIT MODULES AND INTELLIGENT CARDS INCORPORATING THEM
US10438895B1 (en) * 2018-06-08 2019-10-08 American Semiconductor, Inc. Flexible micro-module

Also Published As

Publication number Publication date
US20200035619A1 (en) 2020-01-30
CN110783297A (zh) 2020-02-11
US11088087B2 (en) 2021-08-10

Similar Documents

Publication Publication Date Title
KR100332282B1 (ko) 반도체장치및제조방법
KR102136785B1 (ko) 인덕터를 포함하는 적층형 반도체 다이 및 연관된 방법
US8232631B2 (en) Semiconductor packing having offset stack structure
AU745483B2 (en) Process for manufacturing semiconductor wafer, process for manufacturing semic onductor chip, and IC card
EP2492846B1 (en) RFID tag, wireless charging antenna part, method of manufacturing the same, and mold
TWI325618B (en) Film type package for fingerprint sensor
TW200301871A (en) Semiconductor module and production method therefor and module for IC cards and the like
US7220915B1 (en) Memory card and its manufacturing method
JP2007508630A (ja) デュアルインタフェースを有するカードの生産方法と同方法から得られたマイクロ回路カード
JPH1041424A (ja) 半導体ダイを収納するスマートカード
KR100426330B1 (ko) 지지 테이프를 이용한 초박형 반도체 패키지 소자
US10438895B1 (en) Flexible micro-module
TW202013690A (zh) 半導體裝置及半導體裝置之製造方法
JP2000293651A (ja) 半導体装置
CN210429792U (zh) 一种电子设备
WO2018082275A1 (zh) 一种柔性封装结构及其制备方法、可穿戴设备
US9368424B2 (en) Method of fabricating a semiconductor device used in a stacked-type semiconductor device
US7208822B1 (en) Integrated circuit device, electronic module for chip cards using said device and method for making same
CN108962868B (zh) 封装结构及其制法
TWI306217B (en) Insertion-type semiconductor device and fabrication method thereof
CN219350202U (zh) 封装模块及智能卡
WO2019090748A1 (zh) 生物传感芯片及电子设备
KR101716882B1 (ko) 접속 영역의 스트레스가 분산되는 연성 패키지, 및 그 제조 방법
JP3753984B2 (ja) 非接触通信機器用モジュール及びその製造方法
KR101964045B1 (ko) 반도체 메모리 모듈 및 그 제조 방법

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant