TW202001983A - 半導體結構及其形成方法 - Google Patents
半導體結構及其形成方法 Download PDFInfo
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- TW202001983A TW202001983A TW107128246A TW107128246A TW202001983A TW 202001983 A TW202001983 A TW 202001983A TW 107128246 A TW107128246 A TW 107128246A TW 107128246 A TW107128246 A TW 107128246A TW 202001983 A TW202001983 A TW 202001983A
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- bonding
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- semiconductor structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000010410 layer Substances 0.000 claims abstract description 246
- 239000012790 adhesive layer Substances 0.000 claims abstract description 103
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 239000000463 material Substances 0.000 claims abstract description 59
- 239000000853 adhesive Substances 0.000 claims abstract description 36
- 230000001070 adhesive effect Effects 0.000 claims abstract description 36
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 17
- 239000003989 dielectric material Substances 0.000 claims abstract description 16
- 230000000149 penetrating effect Effects 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 150000001721 carbon Chemical group 0.000 claims 10
- 239000000203 mixture Substances 0.000 description 12
- 239000010408 film Substances 0.000 description 11
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000005304 joining Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910018557 Si O Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 description 2
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/36—Carbonitrides
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/42—Silicides
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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Abstract
本發明涉及一種半導體結構及其形成方法,所述半導體結構包括:第一基底、在所述第一基底表面上的第一黏著/接合疊層,所述第一黏著/接合疊層包括至少一層第一黏著層和至少一層第一接合層,所述第一黏著層和第一接合層分別採用不同的材料,所述第一接合層的材料為包括Si、N和C的介電材料,所述第一黏著層的材料為包括Si和N的介電材料。所述半導體結構的第一黏著/接合疊層在接合時能夠具有較高的接合力。
Description
本發明涉及半導體技術領域,更具體言之,其係關於一種半導體結構及其形成方法。
在3D晶片技術平臺中,通常會將兩片以上形成有半導體元件的晶圓通過晶圓接合(wafer bonding)技術進行接合,以提高晶片的積集度。現有的晶圓接合技術,在晶圓接合面上採用的接合薄膜多為氧化矽或氮化矽薄膜。
現有技術中採用氧化矽和氮化矽薄膜作為接合薄膜,然而其接合強度不夠,導致製程中容易出現缺陷,產品良率因而受到影響。
再者,接合薄膜內還形成有金屬連接結構,在混合接合(hybrid bonding)的過程中,所述金屬連接結構容易在接合介面出現擴散現象,導致產品性能受到影響。
因此,如何提高晶圓接合的品質,是目前亟待解決的問題。
本發明所要解決的技術問題是,提供一種半導體結構及其形成方法。
本發明提供一種半導體結構,所述半導體結構包括:第一基底、在所述第一基底表面上的第一黏著/接合疊層,所述第一黏著/接合疊層包括至少一第一黏著層和至少一第一接合層,所述第一黏著層和第一接合層分別採用不同的材料,所述第一接合層的材料為包括Si、N和C的介質材料,所述第一黏著層的材料為包括Si和N的介質材料。
可選的,所述第一基底表面與一第一黏著層接觸,所述第一黏著/接合疊層表面為一第一接合層表面。
可選的,所述第一接合層中,C的原子濃度大於0且小於50%。
可選的,所述第一接合層中,C的原子濃度均勻分佈,或者C的原子濃度隨第一接合層厚度增加而逐漸改變。
可選的,所述第一黏著層還含有C、所述第一黏著層中C的原子濃度均勻分佈、或者C的原子濃度隨第一黏著層厚度增加而逐漸改變。
可選的,所述第一黏著/接合疊層中的C濃度在所述第一黏著/接合疊層的厚度方向上漸變。
可選的,所述第一黏著/接合疊層中各層的緻密度在所述第一黏著/接合疊層的厚度方向上漸變。
可選的,所述第一接合層的厚度大於100 埃(Å),所述第一黏著層的厚度大於10 Å。
可選的,還包括:第二基底,所述第二基底表面形成有第二黏著/接合疊層,所述第二黏著/接合疊層與所述第一黏著/接合疊層表面相對接合固定。
可選的,所述第二黏著/接合疊層與所述第一黏著/接合疊層具有相同的材料與結構。
可選的,還包括:貫穿所述第一黏著/接合疊層的第一接合墊、貫穿所述第二黏著/接合疊層的第二接合墊、所述第一接合墊與第二接合墊相對接合連接。
本發明的技術方案還提供半導體結構的形成方法,包括:提供第一基底、在所述第一基底表面形成第一黏著/接合疊層,所述第一黏著/接合疊層包括堆疊的至少一第一接合層和至少一第一黏著層,所述第一接合層和第一黏著層分別採用不同的材料,所述第一接合層的材料為包括Si、N和C的介質材料,所述第一黏著層的材料為包括Si和N的介質材料。
可選的,所述第一接合層中,C的原子濃度大於0且小於50%。
可選的,所述第一接合層中C的原子濃度均勻分佈、或者C的原子濃度隨第一接合層厚度增加而逐漸改變。
可選的,所述第一黏著層還含C、所述第一黏著層中C的原子濃度均勻分佈,或者C的原子濃度隨第一黏著層厚度增加而逐漸改變。
可選的,所述第一黏著/接合疊層中的C濃度在所述第一黏著/接合疊層的厚度方向上漸變,或者所述第一黏著/接合疊層中的層的緻密度在所述第一黏著/接合疊層的厚度方向上漸變。
可選的,所述第一接合層的厚度大於100 Å,所述第一黏著層的厚度大於10 Å。
可選的,還包括:提供第二基底、在所述第二基底表面形成第二黏著/接合疊層、將所述第二黏著/接合疊層表面與所述第一黏著/接合疊層表面相對接合固定。
可選的,所述第二黏著/接合疊層與所述第一黏著/接合疊層具有相同的材料與結構。
可選的,還包括:形成貫穿所述第一黏著/接合疊層的第一接合墊、形成貫穿所述第二黏著/接合疊層的第二接合墊、在將所述第二黏著/接合疊層表面與所述第一黏著/接合疊層表面相對接合固定的同時,將所述第一接合墊與第二接合墊相對接合連接。
本發明的半導體結構包括第一基底和位於第一基底表面的第一黏著/接合疊層,所述第一黏著/接合疊層為複合接合層,包括至少一第一黏著層和至少一第一接合層,所述第一黏著/接合疊層與第一基底表面具有較高的黏著力,在接合後也能在接合表面具有較強的鍵合力,並且能夠阻擋金屬材料在接合介面的擴散,從而提高形成的半導體結構的性能。
下面結合附圖對本發明提供的半導體結構及其形成方法的具體實施方式做詳細說明。
請參考第1圖至第4圖,為本發明一具體實施方式的半導體結構的形成過程的結構示意圖。
請參考第1圖,提供第一基底100。
所述第一基底100包括第一半導體基底101、形成於所述第一半導體基底101表面的第一元件層102。
所述第一半導體基底101可以為單晶矽基底、鍺(Ge)基底、矽鍺(SiGe)基底、矽覆絕緣基底(SOI)或鍺覆絕緣基底(GOI)等。根據元件的實際需求,可以選擇合適的第一半導體基底101,於此不作限定。該具體實施方式中,所述第一半導體基底101為單晶矽晶圓。
所述第一元件層102包括形成於所述半導體基底101上的半導體元件、連接所述半導體元件的金屬互連結構、覆蓋所述半導體元件以及金屬互連結構的介電層等。所述第一元件層102可以為多層或單層結構。在一個具體實施方式中,所述第一元件層102包括介電層以及形成於介電層內的3D NAND結構。
請參考第2圖,在所述第一基底100表面形成第一黏著/接合疊層200,所述第一黏著/接合疊層200包括堆疊的至少一第一接合層201和至少一第一黏著層202,所述第一基底對向的所述第一黏著/接合疊層表面為接合面。
該具體實施方式中,所述第一黏著/接合疊層200包括位於第一基底100表面的第一黏著層202以及位於所述第一黏著層202表面的第一接合層201。
所述第一接合層201與第一黏著層202材料不同。具體言之,所述第一接合層201與所述第一黏著層202可以具有相同的構成元素,但是元素的濃度不同。或者所述第一接合層201與所述第一黏著層202含有的元素不同。可以分別採用化學氣相沉積工藝,依次形成所述第一黏著層202和第一接合層201。該具體實施方式中,採用電漿輔助化學氣相沉積(PECVD)製程形成所述第一黏著層202和第一接合層201。
所述第一接合層201的材料為包括矽(Si)、氮(N)和碳(C)的介電材料,所述第一黏著層202的材料為包括Si和N的介電材料,基於化學氣相沉積製程中採用的反應氣體以及具體產品的需求,所述第一接合層201和第一黏著層202內均還可以摻雜有氧(O)、氫(H)、磷(P)、氟(F)等元素中的至少一種。例如,所述第一接合層201的材料可以為摻碳氮化矽、摻碳氮氧化矽、摻氮碳氧化矽等。所述第一黏著層202的材料可以為氮化矽、氮氧化矽等。
在一個具體實施方式中,採用PECVD製程形成所述第一黏著層202,採用的反應氣體包括SiH4
和NH3
,SiH4
與NH3
的流量比大於0.5,射頻功率大於300W。採用電漿輔助化學氣相沉積製程形成所述第一接合層201,採用的反應氣體包括:三甲基矽烷或四甲基矽烷中的其中一種以及NH3
,三甲基矽烷或四甲基矽烷與NH3
的流量比大於0.5,射頻功率大於300W。
在其他具體實施方式中,還可以通過對介電材料進行處理來形成所述第一黏著層202和第一接合層201。例如,在第一基底100表面形成氧化矽薄膜後,對所述氧化矽薄膜進行氮摻雜,形成第一黏著層202。然後再於所述第一黏著層202表面形成氮化矽薄膜,並對所述氮化矽薄膜進行碳摻雜,形成第一接合層201。可以根據待形成的第一黏著層202和第一接合層201材料選擇合適的介電薄膜材料以及薄膜處理方式。
通過控制形成所述第一接合層201和第一黏著層202的製程參數,可以調整所述第一接合層201和第一黏著層202內各組分的濃度,從而對第一基底100與第一黏著層202、第一黏著層202與第一接合層內201之間黏著力以及第一黏著/接合疊層200的介電係數進行調整。
所述第一接合層201位於第一黏著/接合疊層200的頂部,所述第一接合層201中的C能夠有效提高所述第一接合層201在接合過程中與其他接合層之間的接合力。C濃度越高,與其他接合層之間進行接合時產生的接合力越大。在一個具體實施方式中,所述第一接合層201中C的原子濃度大於0,小於50%。
所述第一黏著層202中具有較高的Si原子濃度,能夠提高所述第一黏著層202的緻密度以及與所述第一接合層201以及第一元件層102之間的黏著力。在一個具體實施方式中,所述第一黏著層202中的Si的原子濃度大於20%。所述第一黏著層還含C,並且C的原子濃度小於第一接合層201中C的原子濃度。與在所述第一元件層102表面直接形成第一接合層201相比,由於所述第一黏著層202與所述第一元件層102之間的黏著力更高,能夠有效提高所述第一黏著/接合疊層200與所述第一元件層102之間的黏著力。
由於不同材料層之間的黏著力與介面兩側的材料組成相關,材料組成越接近,黏著力越強。為了進一步增強所述第一黏著層202與所述第一元件層102之間的黏著力,可以在形成所述第一黏著層202的過程中逐漸調整製程參數,使得所述第一黏著層202內的組成濃度逐漸發生變化,使得所述第一元件層102與所述第一黏著層202介面兩側的材料組成接近。在一個具體實施方式中,在形成所述第一黏著層202的過程中,隨著第一黏著層202厚度的增加,通過調整沉積製程的參數,使得第一黏著層202內的Si的原子濃度隨第一黏著層厚度增加而逐漸改變。在其他具體實施方式中,根據所述第一元件層102表面材料的不同,也可以對所述第一黏著層202內的其他成分濃度進行調整,例如使得第一黏著層202中C的原子濃度均勻分佈,或者C的原子濃度隨第一黏著層厚度增加而逐漸改變。在其他具體實施方式中,也可以在形成所述第一黏著層202的過程中保持沉積製程的參數不變,使得第一黏著層202內的各元素的原子濃度在不同厚度位置處保持穩定不變。
為了進一步增強所述第一黏著層202與所述第一接合層201之間的黏著力,可以在形成所述第一接合層201的過程中逐漸調整製程參數,使得所述第一接合層201內的組成濃度逐漸發生變化,使得所述第一接合層201與所述第一黏著層202介面兩側的材料組成接近。在一個具體實施方式中,在形成所述第一接合層201的過程中,隨著第一接合層201厚度的增加,通過調整沉積製程的參數,使得C的原子濃度隨著第一接合層201厚度增加而逐漸增大。在其他具體實施方式中,也可以使得C的原子濃度隨著第一接合層201厚度增加而逐漸減小或者先逐漸增大再逐漸減小。在其他具體實施方式中,在形成所述第一接合層201的過程中保持沉積製程的參數不變,使得第一接合層201中各元素在不同厚度位置處保持穩定不變。
所述第一接合層201的厚度大於所述第一黏著層202的厚度,以確保在將所述第一接合層201與其他接合層進行接合時,所述第一接合層201具有足夠的接合厚度。在一個具體實施方式中,所述第一黏著層202的厚度大於10 Å,所述第一接合層201的厚度大於100 Å。
在其他具體實施方式中,所述第一黏著/接合疊層200還可以包括三層以上堆疊的子接合層。在一個具體實施方式中,所述第一黏著/接合疊層200包括一層第一黏著層202、兩層以上的第一接合層201,不同第一接合合層201的材料可以相同也可以不同。在其他具體實施方式中,所述第一黏著/接合疊層200還可以包括兩層以上的第一黏著層202和一層第一接合層201。所述第一黏著/接合疊層200還可以包括多層相互間隔層疊的第一黏著層202和第一接合層201。在所述第一黏著/接合疊層200包括三層以上的子接合層的情況下,所述第一基底100表面與一第一黏著層202接觸,所述第一黏著/接合疊層200表面為一第一接合層201表面,從而使得所述第一黏著/接合疊層200與所述第一元件層102表面具有較高的黏著力,所述第一黏著/接合疊層200與其他接合層進行接合時能夠產生較強的接合力。
在一個具體實施方式中,所述第一黏著/接合疊層200中的C濃度在所述第一黏著/接合疊層的厚度方向上漸變。在另一具體實施方式中,所述第一黏著/接合疊層200中各層的緻密度在所述第一黏著/接合疊層的厚度方向上漸變。
請參考圖3,在另一具體實施方式中,還包括:提供第二基底300、在所述第二基底300表面形成第二黏著/接合疊層400。
所述第二基底300包括第二半導體基底301以及位於所述第二半導體基底201表面的第二元件層302。
採用化學氣相沉積製程在所述第二元件層302表面形成第二黏著/接合疊層400。在該具體實施方式中,所述第二黏著/接合疊層400包括至少一層第一接合層401以及至少一層第一黏著層402,所述第二黏著/接合疊層400的具體材料與結構請參考上述具體實施方式中的第一黏著/接合疊層200的描述,於此不再贅述。在一個具體實施方式中,所述第二黏著/接合疊層400的結構與上述第一黏著/接合疊層200的材料與結構均相同。
請參考圖4,將所述第二黏著/接合疊層400與所述第一黏著/接合疊層200的表面相對接合固定。在接合過程中,所述第二黏著/接合疊層400表面的第一接合層401與所述第一黏著/接合疊層200表面的第一接合層201表面進行接合。
所述第一接合層401與第一接合層201內均含有C,部分C以-CH3
的形式存在,-CH3
更易被氧化為-OH,並在接合過程中形成Si-O鍵,使得在接合介面上能夠形成更多的矽氧鍵,從而形成較強的接合力。在一個具體實施方式中,所述第一接合層401與第一接合層201之間的接合力大於2焦耳/平方公尺(J/m2
)。而現有技術中在採用不含C的接合層進行接合的場合中,通常其接合力小於1.5 J/m2
。
在一個具體實施方式中,所述第一基底100為形成有3D NAND記憶體結構的基底,而所述第二基底200為形成有週邊電路的基底。
在其他具體實施方式中,還可以在基底的兩側表面均形成上述黏著/接合疊層,以實現三個以上基底的接合。
請參考第5圖,在另一具體實施方式中,還包括:形成貫穿所述第一黏著/接合疊層200的第一接合墊501、形成貫穿所述第二黏著/接合疊層400的第二接合墊502、在將所述第二黏著/接合疊層400表面與所述第一黏著/接合疊層200的表面相對接合固定的同時,將所述第一接合墊501與第二接合墊502相對接合連接。
所述第一接合墊501和第二接合墊502可以分別連接至所述第一元件層102和第二元件層302內的半導體器件以及金屬互連層。
所述第一接合墊501的形成方法包括:對所述第一黏著/接合疊層200進行圖形化製程,形成貫穿所述第一黏著/接合疊層200的開口、在所述開口內填充金屬材料並進行平坦化,以形成填充滿所述開口的第一接合墊501。採用相同的方法在所述第二黏著/接合疊層400內形成所述第二接合墊502。將所述第一接合墊501與第二接合墊502接合連接,可以實現所述第一元件層102和第二元件層302內的半導體元件之間的電連接。
所述第一接合墊501和第二接合墊502的材料可以是Cu、W等金屬材料。所述第一黏著/接合疊層200和第二黏著/接合疊層400的接合介面為第一接合層201、401的接合表面,所述第一接合層201和第一接合層401內含有C,能夠有效阻擋所述第一接合墊501和第二接合墊502的材料在接合介面發生擴散,從而提高所述半導體結構的性能。
上述方法還用於多片基底接合。請參考第6圖,在本發明一具體實施方式中,還包括提供第三基底600,在所述第三基底600的相對兩側表面分別形成第三黏著/接合疊層700和第四黏著/接合疊層800、將所述第三黏著/接合疊層700與第一黏著/接合疊層200的表面相對接合固定,將所述第四黏著/接合疊層800與第二黏著/接合疊層400的表面接合固定,形成三層接合結構。
該具體實施方式中,所述第三黏著/接合疊層700包括第一黏著層702和第一接合層701,所述第四黏著/接合疊層800包括第一黏著層802和第一接合層801。將所述第一接合層801與第一接合層401的表面接合固定,將所述第一接合層701與第一接合層201的表面接合固定。
在其他具體實施方式中,所述第三黏著/接合疊層700和第四黏著/接合疊層800還可以為其他結構。所述第三黏著/接合疊層700和第四黏著/接合疊層800的形成方法,請參考上述具體實施方式中,第一接合疊層200的形成方法,於此不再贅述。
該具體實施方式中,還包括在第三黏著/接合疊層700內形成第三接合墊703,在第四黏著/接合疊層800內形成第四接合墊803,將所述第三接合墊703與第一接合墊501接合連接,將所述第四接合墊803與第二接合墊502接合連接。
在其他具體實施方式中,還可以採用上述方法形成四層以上的接合結構。
上述具體實施方式,在基底表面形成複合結構的接合層,其與基底表面會具有較高的黏著力,在接合後也能在接合表面具有較強的接合力,並且能夠阻擋金屬材料在接合介面的擴散,從而提高形成的半導體結構的性能。
需說明的是,在本發明的技術方案中,半導體結構中各個基底內的半導體元件類型並不應侷限於所給實施例,除了3D NAND之外,其可以為互補式金屬氧化物半導體(CMOS)電路、影像感測器(CIS)電路、薄膜電晶體(TFT)電路等等。
本發明的具體實施方式還提供一種半導體結構。
請參考第2圖,為本發明一具體實施方式的半導體結構的結構示意圖。
所述半導體結構,包括:第一基底100;位於所述第一基底100表面的第一黏著/接合疊層200,所述第一黏著/接合疊層200包括堆疊的至少一層第一接合層201和至少一層第一黏著層202,所述第一接合層201和第一黏著層202的材料不同,所述第一接合層201材料為包括Si、N和C的介電材料,所述第一黏著層202的材料為包括Si和N的介電材料。
所述第一基底100包括第一半導體基底101、形成於所述第一半導體基底101表面的第一元件層102。
所述第一半導體基底101可以為單晶矽基底、Ge基底、SiGe基底、SOI或GOI等。根據元件的實際需求,可以選擇合適的第一半導體基底101,於此不作限定。該具體實施方式中,所述第一半導體基底101為單晶矽晶圓。
所述第一元件層102包括形成與所述半導體基底101上的半導體元件、連接所述半導體元件的金屬互連結構、覆蓋所述半導體元件以及金屬互連結構的介電層等。所述第一元件層102可以為多層或單層結構。在一個具體實施方式中,所述第一元件層102包括介電層以及形成於介電層內的3D NAND結構。
所述第一黏著/接合疊層200包括位於第一基底100表面的第一接合層201以及位於所述第一接合層201表面的第一黏著層202。所述第一接合層201與第一黏著層202材料不同。具體言之,所述第一接合層201與所述第一黏著層202可以具有相同的構成元素,但是元素的濃度不同。或者所述第一接合層201與所述第一黏著層202含有的元素不同。
所述第一接合層201的材料為包括Si、N和C的介電材料,所述第一黏著層202的材料為包括Si和N的介電材料。基於形成所述第一接合層201和第一黏著層202的製程以及具體的產品需求,所述第一接合層201和第一黏著層202內還可以摻雜有O、H、P、F等元素中的至少一種。例如,所述第一接合層201的材料可以為摻碳氮化矽、摻碳氮氧化矽、摻氮碳氧化矽等。所述第一黏著層202的材料可以為氮化矽、氮氧化矽等。
通過控制形成所述第一接合層201和第一黏著層202的製程參數,可以調整所述第一接合層201和第一黏著層202內各組成的濃度,從而對材料層之間的黏著力以及所述第一黏著/接合疊層200的介電係數進行調整。
所述第一接合層201位於第一黏著/接合疊層200的頂部,所述第一接合層201中的C能夠有效提高所述第一接合層201在接合過程中與其他接合層之間的接合力。C濃度越高,與其他接合層之間進行接合時產生的接合力越大。在一個具體實施方式中,所述第一接合層201中C的原子濃度大於0且小於50%。
所述第一黏著層202中具有較高的Si原子濃度,能夠提高所述第一黏著層202的緻密度以及與所述第一接合層201以及第一元件層102之間的黏著力。在一個具體實施方式中,所述第一黏著層202中的Si原子濃度大於20%,並且C的原子濃度小於第一接合層201中的C的原子濃度,與在所述第一元件層102表面直接形成第一接合層202相比,由於所述第一黏著層202與所述第一元件層102之間的黏著力更高,能夠有效提高所述第一黏著/接合疊層200與所述第一元件層102之間的黏著力。
由於不同材料層之間的黏著力與介面兩側的材料組成相關,材料組成越接近,黏著力越強。為了進一步增強所述第一黏著層202與所述第一元件層102之間的黏著力,所述第一黏著層202內的組成濃度隨厚度逐漸發生變化,使得所述第一元件層102與所述第一黏著層202介面兩側的材料組成接近。在一個具體實施方式中,所述第一黏著層202內的Si原子濃度隨第一黏著層厚度增加而逐漸改變。在其他具體實施方式中,根據所述第一元件層102表面材料的不同,所述第一黏著層202內的其他成分濃度也可以隨厚度進行變化。在其他具體實施方式中,也可以使得第一黏著層202內的各元素的原子濃度在不同厚度位置處保持穩定不變,具有均勻分佈的原子濃度。
為了進一步增強所述第一黏著層202與所述第一接合層201之間的黏著力,所述第一接合層201內的組成濃度也可以隨厚度逐漸變化,使得所述第一接合層201與所述第一黏著層202介面兩側的材料組成接近。在一個具體實施方式中,隨著第一接合層201厚度的增加,第一接合層201內的C原子濃度隨著第一接合層201厚度增加而逐漸增大。在其他具體實施方式中,第一接合層201內C的原子濃度隨著第一接合層201厚度的增加而逐漸減小,或者是先逐漸增大再逐漸減小。在其他具體實施方式中,所述第一接合層201中各元素在不同厚度位置處保持穩定不變,具有均勻分佈的原子濃度。
所述第一接合層201的厚度大於所述第一黏著層202的厚度,以確保在將所述第一接合層201與其他接合層進行接合時,所述第一接合層201具有足夠的接合厚度。在一個具體實施方式中,所述第一黏著層202的厚度大於10 Å,所述第一接合層201的厚度大於100 Å。
在其他具體實施方式中,所述第一黏著/接合疊層200還可以包括三層以上堆疊的子接合層。在一個具體實施方式中,所述第一黏著/接合疊層200包括一層第一黏著層202、兩層以上的第一接合層201,不同第一接合層201的材料可以相同也可以不同.在其他具體實施方式中,所述第一黏著/接合疊層200還可以包括兩層以上的第一黏著層202和一層第一接合層201。所述第一黏著/接合疊層200還可以包括多層相互間隔層疊的第一黏著層202和第一接合層201。在所述第一黏著/接合疊層200包括三層以上子接合層的情況下,所述第一基底100表面與一第一黏著層202接觸,所述第一黏著/接合疊層200表面為一第一接合層201表面,從而使得所述第一黏著/接合疊層200與所述第一元件層102表面具有較高的黏著力,所述第一黏著/接合疊層200與其他接合層進行接合時能夠產生較強的接合力。
在一個具體實施方式中,所述第一黏著/接合疊層200中C濃度在所述第一黏著/接合疊層的厚度方向上漸變。在另一具體實施方式中,所述第一黏著/接合疊層200中各層的緻密度在所述第一黏著/接合疊層的厚度方向上漸變。
請參考第4圖,為本發明另一具體實施方式的半導體結構的示意圖。
該具體實施方式中,所述半導體結構還包括:第二基底300,所述第二基底300表面形成有第二黏著/接合疊層400,所述第二黏著/接合疊層400與所述第一黏著/接合疊層200的表面相對接合固定。
所述第二基底300包括第二半導體基底301以及位於所述第二半導體基底201表面的第二元件層302。在該具體實施方式中,所述第二黏著/接合疊層400包括至少一層第一接合層401以及至少一層第一黏著層402,所述第二黏著/接合疊層400的具體材料與結構請參考上述具體實施方式中的第一黏著/接合疊層200的描述,於此不再贅述。在一個具體實施方式中,所述第二黏著/接合疊層400的結構與上述第一黏著/接合疊層200的材料與結構均相同。
所述第二黏著/接合疊層400頂層的第一接合層401會與所述第一黏著/接合疊層200頂層的第一接合層201表面進行接合。所述第一接合層401與第一接合層201內均含有C,部分C以-CH3
的形式存在,-CH3
更易被氧化為-OH,並在接合過程中形成Si-O鍵,使得在接合介面上能夠形成更多的矽氧鍵,從而形成較強的接合力。
在其他具體實施方式中,所述半導體結構可以包括三個以上的基底,相鄰基底之間均通過本發明具體實施方式中的複合接合層進行接合。
請參考第5圖,為發明另一具體實施方式的半導體結構的結構示意圖。
該具體實施方式中,所述半導體結構還包括:貫穿所述第一黏著/接合疊層200的第一接合墊501、貫穿所述第二黏著/接合疊層400的第二接合墊502;所述第二黏著/接合疊層400表面與所述第一黏著/接合疊層200的表面相對接合固定且所述第一接合墊501與第二接合墊502相對接合連接。
所述第一接合墊501和第二接合墊502可以分別連接至所述第一元件層102和第二元件層302內的半導體元件以及金屬互連層。
所述第一接合墊501和第二接合墊502的材料可以是Cu、W等金屬材料。所述第一黏著/接合疊層200和第二黏著/接合疊層400的接合介面為第一接合層201、401的接合表面,所述第一接合層201和第一接合層401內含有C,能夠有效阻擋所述第一接合接合墊501和第二接合墊502的材料在接合介面發生擴散,從而提高所述半導體結構的性能。
在一個具體實施方式中,所述第一基底100為形成有3D NAND記憶體結構的基底,而所述第二基底200為形成有週邊電路的基底。
請參考第6圖,為本發明另一具體實施方式的半導體結構示意圖。
該具體實施方式中,所述半導體結構還包括第三基底600,所述第三基底600的相對兩側表面分別形成有第三黏著/接合疊層700和第四黏著/接合疊層800、所述第三黏著/接合疊層700與第一黏著/接合疊層200的表面相對接合固定,所述第四黏著/接合疊層800與第二黏著/接合疊層400的表面接合固定,構成三層接合結構。
該具體實施方式中,所述第三黏著/接合疊層700包括第一黏著層702和第一接合層701,所述第四黏著/接合疊層800包括第一黏著層802和第一接合層801。所述第一接合層801與第一接合層401表面接合固定,所述第一接合層701與第一接合層201的表面接合固定。
在其他具體實施方式中,所述第三黏著/接合疊層700和第四黏著/接合疊層800還可以為其他結構。所述第三黏著/接合疊層700和第四黏著/接合疊層800的材料和結構,請參考上述具體實施方式中對第一黏著/接合疊層200的具體描述,於此不再贅述。
該具體實施方式中,所述第三黏著/接合疊層700內還形成有第三接合墊703,第四黏著/接合疊層800內還形成有第四接合墊803,所述第三接合墊703與第一接合墊501接合連接,所述第四接合墊803與第二接合墊502接合連接。
在其他具體實施方式中,還可以採用上述方法形成四層以上的接合結構。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100‧‧‧第一基底101‧‧‧第一半導體基底102‧‧‧第一元件層200‧‧‧第一黏著/接合疊層201‧‧‧第一接合層202‧‧‧第一黏著層300‧‧‧第二基底301‧‧‧第二半導體基底302‧‧‧第二元件層400‧‧‧第二黏著/接合疊層401‧‧‧第一接合層402‧‧‧第一黏著層501‧‧‧第一接合墊502‧‧‧第二接合墊600‧‧‧第三基底700‧‧‧第三黏著/接合疊層701‧‧‧第一接合層702‧‧‧第一黏著層703‧‧‧第三接合墊800‧‧‧第四黏著/接合疊層801‧‧‧第一接合層802‧‧‧第一黏著層803‧‧‧第四接合墊
第1圖至第4圖為本發明一具體實施方式的半導體結構的形成過程的結構示意圖; 第5圖為本發明一具體實施方式的半導體結構的結構示意圖;以及 第6圖為本發明一具體實施方式的半導體結構的結構示意圖。
100‧‧‧第一基底
101‧‧‧第一半導體基底
102‧‧‧第一元件層
200‧‧‧第一黏著/接合疊層
201‧‧‧第一接合層
202‧‧‧第一黏著層
Claims (20)
- 一種半導體結構,包括: 第一基底;其中 位在該第一基底的表面上的第一黏著/接合疊層,該第一黏著/接合疊層包括至少一第一黏著層和至少一第一接合層,該第一黏著層和該第一接合層分別採用不同的材料,該第一接合層的材料包括矽、氮及碳的介電材料,該第一黏著層的材料包括矽和氮的介電材料。
- 如申請專利範圍第1項所述之半導體結構,其中該第一基底的表面與該第一黏著層接觸,該第一黏著/接合疊層的表面為一第一接合層的表面。
- 如申請專利範圍第1項所述之半導體結構,其中該第一接合層中的碳原子濃度大於0且小於50%。
- 如申請專利範圍第1項所述之半導體結構,其中該第一接合層中的碳原子濃度均勻分佈,或者碳原子濃度隨著該第一接合層的厚度增加而逐漸改變。
- 如申請專利範圍第1項所述之半導體結構,其中該第一黏著層還含有碳,該第一黏著層中的碳原子濃度均勻分佈,或者碳原子濃度隨著該第一黏著層的厚度增加而逐漸改變。
- 如申請專利範圍第5項所述之半導體結構,其中該第一黏著/接合疊層中的碳濃度在該第一黏著/接合疊層的厚度方向上漸變。
- 如申請專利範圍第1項所述之半導體結構,其中該第一黏著/接合疊層中的碳濃度在該第一黏著/接合疊層的厚度方向上漸變。
- 如申請專利範圍第1項所述之半導體結構,其中該第一接合層的厚度大於100 Å,所述第一黏著層的厚度大於10 Å。
- 如申請專利範圍第1項所述之半導體結構,還包括:第二基底,該第二基底的表面形成有第二黏著/接合疊層,該第二黏著/接合疊層與該第一黏著/接合疊層的表面相對接合固定。
- 如申請專利範圍第9項所述之半導體結構,其中該第二黏著/接合疊層與該第一黏著/接合疊層具有相同的材料與結構。
- 如申請專利範圍第9項所述之半導體結構,還包括: 貫穿所述第一黏著/接合疊層的第一接合墊;以及 貫穿所述第二黏著/接合疊層的第二接合墊,其中該第一鍵合墊與第二接合墊相對接合連接。
- 一種半導體結構的形成方法,包括: 提供第一基底;以及 在該第一基底的表面形成第一黏著/接合疊層,該第一黏著/接合疊層包括堆疊的至少一第一接合層和至少一第一黏著層,該第一接合層和第一黏著層分別採用不同的材料,該第一接合層的材料為包括矽、氮及碳的介電材料,該第一黏著層的材料為包括矽和氮的介電材料。
- 如申請專利範圍第12項所述之半導體結構的形成方法,其中該第一接合層中的碳原子濃度大於0且小於50%。
- 如申請專利範圍第12項所述之半導體結構的形成方法,其中該第一接合層中的碳原子濃度均勻分佈,或者碳原子濃度隨著該第一接合層的厚度增加而逐漸改變。
- 如申請專利範圍第12項所述之半導體結構的形成方法,其中該第一黏著層還含有碳,該第一黏著層中的碳原子濃度均勻分佈,或者碳原子濃度隨著該第一黏著層的厚度增加而逐漸改變。
- 如申請專利範圍第15項所述之半導體結構的形成方法,該第一黏著/接合疊層中的碳濃度在該第一黏著/接合疊層的厚度方向上漸變,或者該第一黏著/接合疊層中各層的緻密度在該第一黏著/接合疊層的厚度方向上漸變。
- 如申請專利範圍第12項所述之半導體結構的形成方法,其中該第一接合層的厚度大於100 Å,該第一黏著層的厚度大於10 Å。
- 如申請專利範圍第12項所述之半導體結構的形成方法,還包括: 提供第二基底; 在該第二基底的表面形成第二黏著/接合疊層;以及 將該第二黏著/接合疊層的表面與該第一黏著/接合疊層的表面相對接合固定。
- 如申請專利範圍第18項所述之半導體結構的形成方法,其中該第二黏著/接合疊層與該第一黏著/接合疊層具有相同的材料與結構。
- 如申請專利範圍第18項所述之半導體結構的形成方法,還包括: 形成貫穿該第一黏著/接合疊層的第一接合墊; 形成貫穿該第二黏著/接合疊層的第二接合墊;以及 在將該第二黏著/接合疊層的表面與該第一黏著/接合疊層的表面相對接合固定的同時,將該第一接合墊與該第二接合墊相對接合連接。
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US20240071984A1 (en) * | 2022-08-23 | 2024-02-29 | Tokyo Electron Limited | Next generation bonding layer for 3d heterogeneous integration |
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Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
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US6953984B2 (en) * | 2000-06-23 | 2005-10-11 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
US7384693B2 (en) * | 2004-04-28 | 2008-06-10 | Intel Corporation | Diamond-like carbon films with low dielectric constant and high mechanical strength |
US7456093B2 (en) * | 2004-07-03 | 2008-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving a semiconductor device delamination resistance |
US7465676B2 (en) * | 2006-04-24 | 2008-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming dielectric film to improve adhesion of low-k film |
JP2010056156A (ja) * | 2008-08-26 | 2010-03-11 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP5644096B2 (ja) * | 2009-11-30 | 2014-12-24 | ソニー株式会社 | 接合基板の製造方法及び固体撮像装置の製造方法 |
US8940620B2 (en) * | 2011-12-15 | 2015-01-27 | Power Integrations, Inc. | Composite wafer for fabrication of semiconductor devices |
US8779600B2 (en) * | 2012-01-05 | 2014-07-15 | International Business Machines Corporation | Interlevel dielectric stack for interconnect structures |
US9048283B2 (en) * | 2012-06-05 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding systems and methods for semiconductor wafers |
CN105070668B (zh) * | 2015-08-06 | 2019-03-12 | 武汉新芯集成电路制造有限公司 | 一种晶圆级芯片封装方法 |
US20170317466A1 (en) * | 2016-04-29 | 2017-11-02 | Hewlett Packard Enterprise Development Lp | Devices including dielectric layers(s) and interface layers(s) |
CN108122823B (zh) * | 2016-11-30 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | 晶圆键合方法及晶圆键合结构 |
WO2020000380A1 (zh) * | 2018-06-29 | 2020-01-02 | 长江存储科技有限责任公司 | 半导体结构及其形成方法 |
CN112567512B (zh) * | 2018-06-29 | 2023-09-01 | 长江存储科技有限责任公司 | 半导体结构及其形成方法 |
-
2018
- 2018-06-29 CN CN201880096595.1A patent/CN112567495B/zh active Active
- 2018-06-29 SG SG11202103709VA patent/SG11202103709VA/en unknown
- 2018-06-29 CN CN202310283040.0A patent/CN116364659A/zh active Pending
- 2018-06-29 WO PCT/CN2018/093692 patent/WO2020000378A1/zh active Application Filing
- 2018-08-14 TW TW107128246A patent/TWI710001B/zh active
-
2019
- 2019-04-08 US US16/378,517 patent/US20200006284A1/en not_active Abandoned
-
2021
- 2021-07-05 US US17/367,431 patent/US20210335745A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
TWI710001B (zh) | 2020-11-11 |
CN116364659A (zh) | 2023-06-30 |
CN112567495A (zh) | 2021-03-26 |
US20210335745A1 (en) | 2021-10-28 |
CN112567495B (zh) | 2023-04-11 |
US20200006284A1 (en) | 2020-01-02 |
WO2020000378A1 (zh) | 2020-01-02 |
SG11202103709VA (en) | 2021-05-28 |
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