TWI668860B - 半導體結構及其形成方法 - Google Patents
半導體結構及其形成方法 Download PDFInfo
- Publication number
- TWI668860B TWI668860B TW107128278A TW107128278A TWI668860B TW I668860 B TWI668860 B TW I668860B TW 107128278 A TW107128278 A TW 107128278A TW 107128278 A TW107128278 A TW 107128278A TW I668860 B TWI668860 B TW I668860B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- bonding
- bonding layer
- adhesion
- semiconductor structure
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000010410 layer Substances 0.000 claims abstract description 344
- 239000012790 adhesive layer Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims description 59
- 229910052710 silicon Inorganic materials 0.000 claims description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000012495 reaction gas Substances 0.000 description 9
- 229910052731 fluorine Inorganic materials 0.000 description 8
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 description 2
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 2
- 229910018557 Si O Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/05576—Plural external layers being mutually engaged together, e.g. through inserts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
- H01L2224/29082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3018—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/30181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/335—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
- H01L2224/80013—Plasma cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8034—Bonding interfaces of the bonding area
- H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Recrystallisation Techniques (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
本發明涉及一種半導體結構及其形成方法,所述半導體結構包括:第一基底;位於所述第一基底表面的第一黏附層;位於所述第一黏附層表面的第一鍵合層,所述第一黏附層的緻密度大於所述第一鍵合層的緻密度。所述半導體結構的第一黏附層與所述第一基底以及第一鍵合層之間具有較高的黏附性,有利於提高半導體結構的性能。
Description
本發明涉及半導體技術領域,尤其涉及一種半導體結構及其形成方法。
在3D的晶片技術平臺中,通常會將兩片及以上形成有半導體元件的晶圓透過晶圓鍵合技術進行鍵合,以提高晶片的集成度。現有的晶圓鍵合技術,在晶圓鍵合面上形成鍵合薄膜,兩層晶圓之間透過鍵合薄膜表面鍵合實現晶圓鍵合。
現有技術中,通常採用氧化矽和氮化矽薄膜作為鍵合薄膜,鍵合強度不夠,導致製程過程中容易出現缺陷,產品良率受到影響。
並且,鍵合薄膜內還形成有金屬連接結構,在混合鍵合的過程中,所述金屬連接結構容易在鍵合介面出現擴散現象,導致產品性能受到影響。
因此,如何提高晶圓鍵合的品質,是目前亟待解決的問題。
本發明所要解決的技術問題是,提供一種半導體結構及其形成方法,以提高鍵合品質。
為解決上述問題,本發明提供一種半導體結構,包括:一種半導體結構,其特徵在於,包括:第一基底;位於所述第一基底表面的第一黏附層;位於所述第一黏附層表面的第一鍵合層,所述第一黏附層的緻密度大於所述第一鍵合層的緻密度。
可選擇的,所述第一鍵合層的材料為包含C元素的介質材料。
可選擇的,所述第一鍵合層還包括Si和N。
可選擇的,所述第一黏附層的材料包括氮化矽、氮氧化矽以及氧化矽中的至少一種。
可選擇的,所述第一黏附層的厚度為30Å~100Å。
可選擇的,所述第一鍵合層中,C的原子濃度均勻分佈,或者C的原子濃度隨第一鍵合層厚度增加而增大。
可選擇的,還包括:第二基底,所述第二基底表面形成有第二黏附層和位於所述第二黏附層表面的第二鍵合層,所述第二黏附層的緻密度大於所述第二鍵合層的緻密度;所述第二鍵合層與所述第一鍵合層表面相對鍵合固定。
可選擇的,所述第二鍵合層與所述第一鍵合層的材料相同,所述第二黏附層與所述第一黏附層的材料相同。
可選擇的,所述第二黏附層的厚度為30Å~100Å。
可選擇的,還包括貫穿所述第一鍵合層和第一黏附層的第一鍵合墊;貫穿所述第二鍵合層和第二黏附層的第二鍵合墊;所述第一鍵合墊與第二鍵合墊相對鍵合連接。
為解決上述問題,本發明的技術方案還提供一種半導體結構的形成方法,包括:提供第一基底;在所述第一基底表面形成第一黏附層;對所述第一黏附層進行電漿轟擊,以提高緻密度;在所述第一黏附層表面形成第一鍵合層,所述第一黏附層的緻密度大於所述第一鍵合層的緻密度。
進行所述電漿轟擊之前,所述第一黏附層含有H鍵;在所述電漿轟擊步驟中,採用含N電漿進行轟擊,以減少所述第一黏附層中的H鍵。
可選擇的,所述第一鍵合層的材料為包含C元素的介質材料。
可選擇的,所述第一鍵合層還包括Si和N。
可選擇的,所述第一黏附層的材料包括氮化矽、氮氧化矽以及氧化矽中的至少一種。
可選擇的,所述第一黏附層的厚度為30Å~100Å。
本發明的半導體結構的第一基底與第一鍵合層之間具有第一黏附層,所述第一黏附層的緻密度大於第一鍵合層緻密度,從而提高第一黏附層與第一鍵合層之間的黏附力。且所述第一鍵合層在鍵合後也能在鍵合表面具有較強的鍵合力,能夠阻擋金屬材料在鍵合介面的擴散,從而提高形成的半導體結構的性能。
100‧‧‧第一基底
101‧‧‧第一半導體襯底
102‧‧‧第一元件層
201‧‧‧第一鍵合層
202‧‧‧第一黏附層
300‧‧‧第二基底
301‧‧‧第二半導體襯底
302‧‧‧第二元件層
401‧‧‧第二鍵合層
402‧‧‧第二黏附層
501‧‧‧第一鍵合墊
502‧‧‧第二鍵合墊
600‧‧‧第三基底
701‧‧‧第三鍵合層
702‧‧‧第三黏附層
703‧‧‧第三鍵合墊
801‧‧‧第四鍵合層
802‧‧‧第四黏附層
803‧‧‧第四鍵合墊
圖1至圖4為本發明一具體實施方式的半導體結構的形成過程的結構示意圖;圖5為本發明一具體實施方式的半導體結構的結構示意圖;圖6為本發明一具體實施方式的半導體結構的結構示意圖。
下面結合附圖對本發明提供的半導體結構及其形成方法的具體實施方式做詳細說明。
請參考圖1至圖4,為本發明一具體實施方式的半導體結構的形成過程的結構示意圖。
請參考圖1,提供第一基底100。
所述第一基底100包括第一半導體襯底101、形成於所述第一半導體
襯底101表面的第一元件層102。
所述第一半導體襯底101可以為單晶矽襯底、Ge襯底、SiGe襯底、SOI或GOI等;根據元件的實際需求,可以選擇合適的第一半導體襯底101,在此不作限定。該具體實施方式中,所述第一半導體襯底101為單晶矽晶圓。
所述第一元件層102包括形成於所述半導體襯底101上的半導體元件、連接所述半導體元件的金屬互連結構、覆蓋所述半導體元件以及金屬互連結構的介質層等,所述介質層通常為氧化矽、氮化矽或氮氧化矽。所述第一元件層102可以為多層或單層結構。在一個具體實施方式中,所述第一元件層102包括介質層以及形成於介質層內的3D NAND結構。
請參考圖2,在所述第一基底100表面形成第一黏附層202和位於所述第一黏附層202表面的第一鍵合層201。
可以分別採用化學氣相沉積製程,依次形成所述第一黏附層202和第一鍵合層201。該具體實施方式中,採用電漿輔助化學氣相沉積製程形成所述第一黏附層202和第一鍵合層201。
所述第一黏附層202的材料為緻密度大於所述第一鍵合層201緻密度的介質材料。所述第一黏附層202的材料可以為氮化矽、氮氧化矽以及氧化矽中的至少一種,基於化學氣相沉積製程中採用的反應氣體,以及具體產品的需求,所述第一黏附層202內還可以摻雜有O、H、P、F等元素中的至少一種。
在一個具體實施方式中,所述第一黏附層202的材料為氮化矽,採用電漿輔助化學氣相沉積製程形成所述第一黏附層202,採用的反應氣體包括SiH4和NH3,SiH4和NH3的流量比範圍為(0.8~1.2):1,射頻功率範圍為150W~300W。
可以透過調整所述沉積製程中的製程參數,形成具有較高緻密度的第一黏附層202。
在其他具體實施方式中,所述第一黏附層202的形成方法包括:採用沉積製程在所述第一基底100表面形成黏附材料層,然後對所述黏附材料層進行電漿轟擊,以減少黏附材料層中H的含量,從而提高形成的第一黏附層202的緻密度。所述電漿轟擊可以採用含N氣體,例如N2、NH3等。在一個具體實施方式中,所述電漿轟擊可以採用N2作為電漿源,射頻功率範圍為300W~800W,轟擊時間大於15s。透過所述電漿轟擊可以去除所述第一黏附層202內的H,從而使得所述第一黏附層202的單位面積內擁有更多可與相鄰材料層連接的化學鍵,例如Si-、N-等,從而提高所述第一黏附層202與第一鍵合層201介面之間的黏附力。
所述第一鍵合層201的材料為包含C元素的介質材料,在一個具體實施方式中,所述第一鍵合層201主要包含Si、N和C。在其他具體實施方式中,基於化學氣相沉積製程中採用的反應氣體,以及具體產品的需求,所述第一鍵合層201內還可以摻雜有Si、N、O、H、P、F等元素中的至少一種。所述第一鍵合層201的材料可以為摻碳氮化矽、摻碳氮氧化矽、摻氮碳氧化矽等。由於所述第一鍵合層201中含C元素,會導致第一鍵合層201的緻密度較低,如果直接在所述第一基底表面形成所述第一鍵合層201,會導致與第一基底100表面之間的黏附力較弱。而本申請的具體實施方式中,在所述第一鍵合層201與第一基底100之間形成有緻密度更高的第一黏附層202,可以提高各層之間的黏附力。
在一個具體實施方式中,採用電漿輔助化學氣相沉積製程形成所述第一鍵合層201,採用的反應氣體包括:三甲基矽烷或四甲基矽烷中的一種以及NH3,三甲基矽烷或四甲基矽烷與NH3的流量比範圍為(1.6~2.4):1,射頻功率範圍為500W~1100W。透過控制所述第一鍵合層201和第一黏附層202的形成製程參數,可以調整所述第一鍵合層201和第一黏附層202內各組分的濃度,對材料層之間黏附力以及第一鍵合層201的介電係數進行調整。
所述第一鍵合層201中的C能夠有效提高所述第一鍵合層201在鍵合過程中,與其他鍵合層之間的鍵合力。C濃度越高,與其他鍵合層之間進行鍵合時產生的鍵合力越大。在一個具體實施方式中,所述第一鍵合層201中,C的原子濃度大於0且小於50%;在另一具體實施方式中,所述第一鍵合層201中C的原子濃度大於35%。
由於不同材料層之間的黏附力與介面兩側的材料組分相關,材料組分越接近,黏附力越強。為了進一步增強所述第一黏附層202與所述第一元件層102之間的黏附力,可以在形成所述第一黏附層202的過程中,逐漸調整製程參數,使得所述第一黏附層202內的組分濃度逐漸發生變化,使得所述第一元件層102與所述第一黏附層202介面兩側的材料組分接近。在一個具體實施方式中,在形成所述第一黏附層202的過程中,隨著第一黏附層202厚度的增加,透過調整沉積製程的參數,使得第一黏附層202內的Si的原子濃度隨第一黏附層202厚度增加而逐漸改變。在其他具體實施方式中,根據所述第一元件層102表面材料的不同,也可以對所述第一黏附層202內的其他成分濃度進行調整。在其他具體實施方式中,也可以在形成所述第一黏附層202的過程中,保持沉積製程參數不
變,使得第一黏附層202內的各元素的原子濃度在不同厚度位置處保持穩定不變。
為了進一步增強所述第一黏附層202與所述第一鍵合層201之間的黏附力,可以在形成所述第一鍵合層201的過程中,逐漸調整製程參數,使得所述第一鍵合層201內的組分濃度逐漸發生變化,使得所述第一鍵合層201與所述第一黏附層202介面兩側的材料組分接近。在一個具體實施方式中,在形成所述第一鍵合層201的過程中,隨著第一鍵合層201厚度的增加,透過調整沉積製程的參數,使得C的原子濃度隨第一鍵合層201厚度增加而逐漸增大。在其他具體實施方式中,也可以使得C的原子濃度隨第一鍵合層201厚度增加而逐漸減小或者先逐漸增大再逐漸減小。在其他具體實施方式中,在形成所述第一鍵合層201的過程中,保持沉積製程參數不變,使得第一鍵合層201中各元素在不同厚度位置處保持一致。
為了保持所述第一黏附層202具有較高的緻密性,在形成所述第一黏附層202的過程中,離子轟擊過程中,能夠盡可能多的減少所述第一黏附層202內的H,使所述第一黏附層202各厚度處的緻密性均得到提高,所述第一黏附層202的厚度不能過大。在一個具體實施方式中,所述第一黏附層202的厚度為30Å~100Å。
所述第一鍵合層201的厚度大於所述第一黏附層202的厚度,以確保在將所述第一鍵合層201與其他鍵合層進行鍵合時,所述第一鍵合層201具有足夠的鍵合厚度。所述第一鍵合層201的厚度大於100Å。
在其他具體實施方式中,所述第一鍵合層201還可以包括兩層以上堆疊的子鍵合層。不同子鍵合層的材料可以相同也可以不同。
上述具體實施方式的半導體結構的第一基底與第一鍵合層之間具有第一黏附層,所述第一黏附層的緻密度大於第一鍵合層緻密度,從而提高第一黏附層與第一鍵合層之間的黏附力。且所述第一鍵合層在鍵合後也能在鍵合表面具有較強的鍵合力,能夠阻擋金屬材料在鍵合介面的擴散,從而提高形成的半導體結構的性能。
請參考圖3,在另一具體實施方式中,還包括:提供第二基底300;在所述第二基底300表面形成第二黏附層402和位於所述第二黏附層402表面的第二鍵合層401。
所述第二基底300包括第二半導體襯底301以及位於所述第二半導體襯底301表面的第二元件層302。
所述第二黏附層402的材料為緻密度大於所述第二鍵合層401緻密度的介質材料。所述第一黏附層202的材料可以為氮化矽、氮氧化矽以及氧化矽中的至少一種,基於化學氣相沉積製程中採用的反應氣體,以及具體產品的需求,所述第一黏附層202內還可以摻雜有O、H、P、F等元素中的至少一種。
所述第二鍵合層401的材料為包含C元素的介質材料,在一個具體實施方式中,所述第二鍵合層401主要包含Si、N和C。在其他具體實施方式中,基於化學氣相沉積製程中採用的反應氣體,以及具體產品的需求,所述第二鍵合
層401內還可以摻雜有Si、N、O、H、P、F等元素中的至少一種。
採用化學氣相沉積製程在所述第二元件層302表面依次形成所述第二黏附層402和第二黏附層401。所述第二黏附層402和所述第二鍵合層401的具體材料與結構請參考上述具體實施方式中的第一黏附層202和第一鍵合層201的描述,在此不再贅述。在一個具體實施方式中,所述第二黏附層402與第一黏附層202的材料、結構相同;所述第二鍵合層401和第一鍵合層201的結構、材料均相同。所述第二黏附層402的厚度為30Å~100Å,所述第二鍵合層401的厚度大於100Å。
請參考圖4,將所述第二鍵合層401所述第一鍵合層201表面相對鍵合固定。
所述第二鍵合層401與第一鍵合層201內均含有C,部分C以-CH3的形式存在,-CH3更易被氧化為-OH,並在鍵合過程中形成Si-O鍵,使得在鍵合介面上能夠形成更多的矽氧鍵,從而形成較強的鍵合力。在一個具體實施方式中,所述第二鍵合層401與第一鍵合層201之間的鍵合力大於2J/M2。而現有技術中採用不含C的鍵合層進行鍵合,通常鍵合力小於1.5J/M2。
在一個具體實施方式中,所述第一基底100為形成有3D NAND儲存結構的基底,而所述第二基底200為形成有周邊電路的基底。
在其他具體實施方式中,還可以在基底的兩側表面均形成上述黏附層和鍵合層,以實現多層鍵合。
請參考圖5,在另一具體實施方式中,還包括:形成貫穿所述第一鍵合層201和第一黏附層202的第一鍵合墊501;形成貫穿所述第二鍵合層401和第二黏附層402的第二鍵合墊502;在將所述第二鍵合層401表面與所述第一鍵合層201表面相對鍵合固定的同時,將所述第一鍵合墊501與第二鍵合墊502相對鍵合連接。
所述第一鍵合墊501和第二鍵合墊502可以分別連接至所述第一元件層102和第二元件層302內的半導體元件以及金屬互連層。
所述第一鍵合墊501的形成方法包括:對所述第一鍵合層201和第一黏附層202進行圖形化,形成貫穿所述第一鍵合層201和第一黏附層202的開口;在所述開口內填充金屬材料,並進行平坦化,形成填充滿所述開口的第一鍵合墊501。採用相同的方法在所述第二鍵合層401和第二黏附層402內形成所述第二鍵合墊502。將所述第一鍵合墊501與第二鍵合墊502鍵合連接,可以實現所述第一元件層102和第二元件層302內的半導體元件之間的電連接。
所述第一鍵合墊501和第二鍵合墊502的材料可以是Cu、W等金屬材料。所述第一鍵合層201和第二鍵合層401內含有C,能夠有效阻擋所述第一鍵合墊501和第二鍵合墊502的材料在鍵合介面發生擴散,從而提高所述半導體結構的性能。
上述具體實施方式,在基底表面形成黏附層、在黏附層表面形成鍵合層,所述黏附層的緻密度大於鍵合層緻密度,從而提高黏附層與鍵合層之間
的黏附力。且所述鍵合層在鍵合後也能在鍵合表面具有較強的鍵合力,能夠阻擋金屬材料在鍵合介面的擴散,從而提高形成的半導體結構的性能。
上述具體實施方式的半導體結構形成方法還用於多片基底鍵合。
請參考圖6,在本發明一具體實施方式中,還包括提供第三基底600,在所述第三基底600的一側表面依次形成第三黏附層702、第三鍵合層701,在另一側相對表面上依次形成第四黏附層802、第四鍵合層801;將所述第三鍵合層701與第一鍵合層201表面相對鍵合固定,將所述第四鍵合層801與第二鍵合層401表面鍵合固定,形成三層鍵合結構。
所述第三黏附層702和第四黏附層802的形成方法,請參考上述具體實施方式中,第一黏附層202的形成方法,在此不再贅述。所述第三鍵合層701和第四鍵合層801的形成方法,請參考上述具體實施方式中,第一鍵合層201的形成方法,在此不再贅述。
該具體實施方式中,還包括形成貫穿所述第三鍵合層701、第三黏附層702的第三鍵合墊703,形成貫穿所述第四鍵合層801、第四黏附層802的第四鍵合墊803,將所述第三鍵合墊703與第一鍵合墊501鍵合連接,將所述第四鍵合墊803與第二鍵合墊502鍵合連接。
在其他具體實施方式中,還可以採用上述方法形成四層以上的鍵合結構。
需說明的是,在本發明的技術方案中,半導體結構中各個基底內的半導體元件類型並不應局限於所給實施例,除了3D NAND之外,其可以為CMOS電路、CIS電路、TFT電路等等。
本發明的具體實施方式還提供一種半導體結構。
請參考圖2,為本發明一具體實施方式的半導體結構的結構示意圖。
所述半導體結構,包括:第一基底100;位於所述第一基底100表面的第一黏附層202;位於所述第一黏附層202表面的第一鍵合層201。
所述第一基底100包括第一半導體襯底101、形成於所述第一半導體襯底101表面的第一元件層102。
所述第一半導體襯底101可以為單晶矽襯底、Ge襯底、SiGe襯底、SOI或GOI等;根據元件的實際需求,可以選擇合適的第一半導體襯底101,在此不作限定。該具體實施方式中,所述第一半導體襯底101為單晶矽晶圓。
所述第一元件層102包括形成於所述半導體襯底101上的半導體元件、連接所述半導體元件的金屬互連結構、覆蓋所述半導體元件以及金屬互連結構的介質層等。所述第一元件層102可以為多層或單層結構。在一個具體實施方式中,所述第一元件層102包括介質層以及形成於介質層內的3D NAND結構。
所述第一黏附層202的材料為緻密度大於所述第一鍵合層201緻密度
的介質材料。所述第一黏附層202的材料可以為氮化矽、氮氧化矽以及氧化矽中的至少一種,基於化學氣相沉積製程中採用的反應氣體,以及具體產品的需求,所述第一黏附層202內還可以摻雜有O、H、P、F等元素中的至少一種。在一個具體實施方式中,所述第一黏附層202為具有高緻密度的SiN。
所述第一鍵合層201的材料為包含C元素的介質材料,在一個具體實施方式中,所述第一鍵合層201主要包含Si、N和C。在其他具體實施方式中,基於化學氣相沉積製程中採用的反應氣體,以及具體產品的需求,所述第一鍵合層201內還可以摻雜有Si、N、O、H、P、F等元素中的至少一種。所述第一鍵合層201的材料可以為摻碳氮化矽、摻碳氮氧化矽、摻氮碳氧化矽等。由於所述第一鍵合層201中含C元素,會導致第一鍵合層201的緻密度較低,如果直接在所述第一基底表面形成所述第一鍵合層201,會導致與第一基底100表面之間的黏附力較弱。而本申請的具體實施方式中,所述第一鍵合層201與第一基底100之間形成有緻密度更高的第一黏附層202,可以提高各層之間的黏附力。
透過控制所述第一鍵合層201和第一黏附層202的形成製程參數,可以調整所述第一鍵合層201和第一黏附層202內各組分的濃度,從而對材料層之間黏附力以及所述第一鍵合層201的介電係數進行調整。
所述第一鍵合層201中的C能夠有效提高所述第一鍵合層201在鍵合過程中,與其他鍵合層之間的鍵合力。C濃度越高,與其他鍵合層之間進行鍵合時產生的鍵合力越大。在一個具體實施方式中,所述第一鍵合層201中,C的原子濃度大於0,小於50%。在另一具體實施方式中,所述C的原子濃度大於35%。
由於不同材料層之間的黏附力與介面兩側的材料組分相關,材料組分越接近,黏附力越強。為了進一步增強所述第一黏附層202與所述第一元件層102之間的黏附力,所述第一黏附層202內的組分濃度隨厚度逐漸發生變化,使得所述第一元件層102與所述第一黏附層202介面兩側的材料組分接近。在一個具體實施方式中,所述第一黏附層202內的Si的原子濃度隨第一黏附層202厚度增加而逐漸改變。在其他具體實施方式中,根據所述第一元件層102表面材料的不同,所述第一黏附層202內的其他成分濃度也可以隨厚度進行變化。在其他具體實施方式中,也可以使得第一黏附層202內的各元素的原子濃度在不同厚度位置處保持穩定不變,具有均勻分佈的原子濃度。
為了進一步增強所述第一黏附層202與所述第一鍵合層201之間的黏附力,所述第一鍵合層201內的組分濃度也可以隨厚度逐漸變化,使得所述第一鍵合層201與所述第一黏附層202介面兩側的材料組分接近。在一個具體實施方式中,隨著第一鍵合層201厚度的增加,第一鍵合層201內的C原子濃度隨第一鍵合層201厚度增加而逐漸增大。在其他具體實施方式中,第一鍵合層201內的C的原子濃度隨第一鍵合層201厚度增加而逐漸減小或者先逐漸增大再逐漸減小。在其他具體實施方式中,所述第一鍵合層201中各元素在不同厚度位置處保持穩定不變,具有均勻分佈的原子濃度。
為了使得所述第一黏附層202整體具有較高的緻密度,所述第一黏附層202的厚度不能過大。在一個具體實施方式中,所述第一黏附層202的厚度為30Å~100Å。
所述第一鍵合層201的厚度大於所述第一黏附層202的厚度,以確保
在將所述第一鍵合層201與其他鍵合層進行鍵合時,所述第一鍵合層201具有足夠的鍵合厚度。在一個具體實施方式中,所述第一鍵合層201的厚度大於100Å。
在其他具體實施方式中,所述第一鍵合層201還可以包括兩層以上堆疊的子鍵合層,不同子鍵合層之間的材料可以相同也可以不同。
請參考圖4,為本發明另一具體實施方式的半導體結構的示意圖。
該具體實施方式中,所述半導體結構還包括:第二基底300,所述第二基底300表面形成有第二黏附層402和位於所述第二黏附層402表面的第二鍵合層401;所述第二鍵合層401與所述第一鍵合層201表面相對鍵合固定。
所述第二基底300包括第二半導體襯底301以及位於所述第二半導體襯底201表面的第二元件層302。
所述第二黏附層402的材料為緻密度大於所述第二鍵合層401緻密度的介質材料。所述第二黏附層402的材料可以為氮化矽、氮氧化矽以及氧化矽中的至少一種,基於化學氣相沉積製程中採用的反應氣體,以及具體產品的需求,所述第二黏附層402內還可以摻雜有O、H、P、F等元素中的至少一種。
所述第二鍵合層401的材料為包含C元素的介質材料,在一個具體實施方式中,所述第二鍵合層401主要包含Si、N和C。在其他具體實施方式中,基於化學氣相沉積製程中採用的反應氣體,以及具體產品的需求,所述第二鍵合層401內還可以摻雜有Si、N、O、H、P、F等元素中的至少一種。
所述第二黏附層402和所述第二鍵合層401的具體材料與結構請參考上述具體實施方式中的第一黏附層202和第一鍵合層201的描述,在此不再贅述。在一個具體實施方式中,所述第二黏附層402與第一黏附層202的材料、結構相同;所述第二鍵合層401和第一鍵合層201的結構、材料均相同。在一個具體實施方式中,所述第二黏附層402的厚度為30Å~100Å,第二鍵合層401的厚度大於100Å。
所述第二鍵合層401與第一鍵合層201內均含有C,使得在鍵合介面上形成較多的矽氧鍵,具有較強的鍵合力。在一個具體實施方式中,所述第二鍵合層401與第一鍵合層201之間的鍵合力大於1.7J/M2。
在其他具體實施方式中,所述半導體結構可以包括三個以上的基底,相鄰基底之間均透過本發明具體實施方式中的黏附層和鍵合層進行鍵合。
請參考圖5,為發明另一具體實施方式的半導體結構的結構示意圖。
該具體實施方式中,所述半導體結構還包括:貫穿所述第一鍵合層201和第一黏附層202的第一鍵合墊501;貫穿所述第二鍵合層401和第二黏附層402的第二鍵合墊502;所述第二鍵合層401表面與所述第一鍵合層201表面相對鍵合固定且所述第一鍵合墊501與第二鍵合墊502相對鍵合連接。
所述第一鍵合墊501和第二鍵合墊502可以分別連接至所述第一元件層102和第二元件層302內的半導體元件以及金屬互連層。
所述第一鍵合墊501和第二鍵合墊502的材料可以是Cu、W等金屬材料。所述第一鍵合層201和第二鍵合層401內含有C,能夠有效阻擋所述第一鍵合墊501和第二鍵合墊502的材料在鍵合介面發生擴散,從而提高所述半導體結構的性能。
請參考圖6,在本發明一具體實施方式中,所述半導體結構還包括第三基底600,位於所述第三基底600的一側表面的第三黏附層702、位於第三黏附層702表面的第三鍵合層701,位於第三基底600的另一側相對表面的第四黏附層802、位於第四黏附層802表面的第四鍵合層801;所述第三鍵合層701與第一鍵合層201表面相對鍵合固定,所述第四鍵合層801與第二鍵合層401表面鍵合固定,構成三層鍵合結構。
所述第三黏附層702和第四黏附層802的材料和結構,請參考上述具體實施方式中,第一黏附層202的材料和結構,在此不再贅述。所述第三鍵合層701和第四鍵合層801的材料和結構,請參考上述具體實施方式中,第一鍵合層201的處理和結構,在此不再贅述。
該具體實施方式中,所述半導體結構還包括貫穿所述第三鍵合層701、第三黏附層702的第三鍵合墊703,貫穿所述第四鍵合層801、第四黏附層802的第四鍵合墊803,所述第三鍵合墊703與第一鍵合墊501鍵合連接,所述第四鍵合墊803與第二鍵合墊502鍵合連接。
在其他具體實施方式中,所述半導體結構還可以為四層以上的鍵合
結構。
以上所述僅是本發明的優選實施方式,應當指出,對於本技術領域
的普通技術人員,在不脫離本發明原理的前提下,還可以做出若干改進和潤飾,這些改進和潤飾也應視為本發明的保護範圍。
Claims (14)
- 一種半導體結構,包括:第一基底;位於所述第一基底表面的第一黏附層;以及位於所述第一黏附層表面的第一鍵合層,所述第一黏附層的緻密度大於所述第一鍵合層的緻密度,且所述第一鍵合層的材料為包含C元素的介質材料。
- 如請求項1所述的半導體結構,其中所述第一鍵合層還包括Si和N。
- 如請求項1所述的半導體結構,其中所述第一黏附層的材料包括氮化矽、氮氧化矽以及氧化矽中的至少一種。
- 如請求項1所述的半導體結構,其中所述第一黏附層的厚度為30Å~100Å。
- 如請求項1所述的半導體結構,其中所述第一鍵合層中,C的原子濃度均勻分佈,或者C的原子濃度隨第一鍵合層厚度增加而增大。
- 如請求項1所述的半導體結構,還包括:第二基底,所述第二基底表面形成有第二黏附層和位於所述第二黏附層表面的第二鍵合層,所述第二黏附層的緻密度大於所述第二鍵合層的緻密度;所述第二鍵合層與所述第一鍵合層表面相對鍵合固定。
- 如請求項6所述的半導體結構,其中所述第二鍵合層與所述第一鍵合層的材料相同,所述第二黏附層與所述第一黏附層的材料相同。
- 如請求項6所述的半導體結構,其中所述第二黏附層的厚度為30Å~100Å。
- 如請求項6所述的半導體結構,其中還包括:貫穿所述第一鍵合層和第一黏附層的第一鍵合墊;以及貫穿所述第二鍵合層和第二黏附層的第二鍵合墊;其中所述第一鍵合墊與第二鍵合墊相對鍵合連接。
- 一種半導體結構的形成方法,包括:提供第一基底;在所述第一基底表面形成第一黏附層;對所述第一黏附層進行電漿轟擊,以提高緻密度;以及在所述第一黏附層表面形成第一鍵合層,所述第一黏附層的緻密度大於所述第一鍵合層的緻密度,且所述第一鍵合層的材料為包含C元素的介質材料。
- 如請求項10所述的半導體結構的形成方法,其中在進行所述電漿轟擊之前,所述第一黏附層含有H鍵,在所述電漿轟擊步驟中,採用含N電漿進行轟擊,以減少所述第一黏附層中的H鍵。
- 如請求項10所述的半導體結構的形成方法,其中所述第一鍵合層還包括Si和N。
- 如請求項10所述的半導體結構的形成方法,其中所述第一黏附層的材料包括氮化矽、氮氧化矽以及氧化矽中的至少一種。
- 如請求項10所述的半導體結構的形成方法,其中所述第一黏附層的厚度為30Å~100Å。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2018/093693 WO2020000379A1 (zh) | 2018-06-29 | 2018-06-29 | 半导体结构及其形成方法 |
WOPCT/CN2018/093693 | 2018-06-29 | ||
??PCT/CN2018/093693 | 2018-06-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI668860B true TWI668860B (zh) | 2019-08-11 |
TW202002285A TW202002285A (zh) | 2020-01-01 |
Family
ID=68316571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107128278A TWI668860B (zh) | 2018-06-29 | 2018-08-14 | 半導體結構及其形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10811380B2 (zh) |
CN (2) | CN112567512B (zh) |
TW (1) | TWI668860B (zh) |
WO (1) | WO2020000379A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112567495B (zh) * | 2018-06-29 | 2023-04-11 | 长江存储科技有限责任公司 | 半导体结构及其形成方法 |
CN116995059A (zh) * | 2018-06-29 | 2023-11-03 | 长江存储科技有限责任公司 | 半导体结构及其形成方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201546874A (zh) * | 2014-02-18 | 2015-12-16 | Ngk Insulators Ltd | 半導體用複合基板的載台基板以及半導體用複合基板 |
TW201705192A (zh) * | 2015-03-17 | 2017-02-01 | 東芝股份有限公司 | 半導體裝置之製造方法及半導體裝置之製造裝置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5526768A (en) * | 1994-02-03 | 1996-06-18 | Harris Corporation | Method for providing a silicon and diamond substrate having a carbon to silicon transition layer and apparatus thereof |
US6953984B2 (en) * | 2000-06-23 | 2005-10-11 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
JP4548828B2 (ja) * | 2004-10-29 | 2010-09-22 | Dowaホールディングス株式会社 | 金属被覆基板の製造方法 |
US7892648B2 (en) * | 2005-01-21 | 2011-02-22 | International Business Machines Corporation | SiCOH dielectric material with improved toughness and improved Si-C bonding |
JP5304536B2 (ja) * | 2009-08-24 | 2013-10-02 | ソニー株式会社 | 半導体装置 |
CN101956180B (zh) * | 2010-07-14 | 2012-05-23 | 中国科学院电工研究所 | 一种减反射薄膜SiNx:H表面原位NH3等离子体处理方法 |
US8896125B2 (en) * | 2011-07-05 | 2014-11-25 | Sony Corporation | Semiconductor device, fabrication method for a semiconductor device and electronic apparatus |
CN103839800A (zh) * | 2012-11-20 | 2014-06-04 | 中国科学院微电子研究所 | 氮化硅制造方法 |
US9443796B2 (en) * | 2013-03-15 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Air trench in packages incorporating hybrid bonding |
KR102211143B1 (ko) * | 2014-11-13 | 2021-02-02 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
KR102505856B1 (ko) * | 2016-06-09 | 2023-03-03 | 삼성전자 주식회사 | 웨이퍼 대 웨이퍼 접합 구조체 |
CN108122823B (zh) * | 2016-11-30 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | 晶圆键合方法及晶圆键合结构 |
-
2018
- 2018-06-29 CN CN201880096617.4A patent/CN112567512B/zh active Active
- 2018-06-29 WO PCT/CN2018/093693 patent/WO2020000379A1/zh active Application Filing
- 2018-06-29 CN CN202311008314.1A patent/CN117080201A/zh active Pending
- 2018-08-14 TW TW107128278A patent/TWI668860B/zh active
-
2019
- 2019-04-07 US US16/377,241 patent/US10811380B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201546874A (zh) * | 2014-02-18 | 2015-12-16 | Ngk Insulators Ltd | 半導體用複合基板的載台基板以及半導體用複合基板 |
TW201705192A (zh) * | 2015-03-17 | 2017-02-01 | 東芝股份有限公司 | 半導體裝置之製造方法及半導體裝置之製造裝置 |
Also Published As
Publication number | Publication date |
---|---|
CN112567512B (zh) | 2023-09-01 |
US20200006277A1 (en) | 2020-01-02 |
TW202002285A (zh) | 2020-01-01 |
US10811380B2 (en) | 2020-10-20 |
CN117080201A (zh) | 2023-11-17 |
WO2020000379A1 (zh) | 2020-01-02 |
CN112567512A (zh) | 2021-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI710001B (zh) | 半導體結構及其形成方法 | |
US7371662B2 (en) | Method for forming a 3D interconnect and resulting structures | |
TWI682445B (zh) | 半導體結構及其形成方法 | |
TWI668860B (zh) | 半導體結構及其形成方法 | |
US20230005873A1 (en) | Semiconductor structure and method of forming the same | |
US20220216178A1 (en) | Semiconductor structure and method of forming the same | |
JP5679662B2 (ja) | 誘電体キャップ層 | |
KR101152203B1 (ko) | 반도체 장치 및 그의 제조 방법 | |
KR102263508B1 (ko) | 선택적 증착법을 이용한 적층가능한 기판의 결합방법 | |
JP2000286262A (ja) | 半導体装置及びその製造方法 |