TW201947731A - 晶片封裝結構及其製造方法 - Google Patents

晶片封裝結構及其製造方法 Download PDF

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TW201947731A
TW201947731A TW107115470A TW107115470A TW201947731A TW 201947731 A TW201947731 A TW 201947731A TW 107115470 A TW107115470 A TW 107115470A TW 107115470 A TW107115470 A TW 107115470A TW 201947731 A TW201947731 A TW 201947731A
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Taiwan
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layer
chip package
redistribution
transistor
package structure
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TW107115470A
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English (en)
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TWI672791B (zh
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游政煌
王泰瑞
馮捷威
鄭惟元
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財團法人工業技術研究院
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Priority to TW107115470A priority Critical patent/TWI672791B/zh
Priority to US16/027,374 priority patent/US10950588B2/en
Priority to CN201810908711.7A priority patent/CN110459531A/zh
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Publication of TWI672791B publication Critical patent/TWI672791B/zh
Publication of TW201947731A publication Critical patent/TW201947731A/zh

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Abstract

一種晶片封裝結構,包括重分佈線路結構層、至少一晶片及封裝膠體。重分佈線路結構層包括至少一重分佈線路、電性連接重分佈線路的至少一電晶體以及電性連接重分佈線路與電晶體的多個導電通孔。晶片設置於重分佈線路結構層上,且與重分佈線路結構層電性連接。封裝膠體設置於重分佈線路結構層上,且至少包覆晶片。另提供一種晶片封裝結構的製造方法。

Description

晶片封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法,且特別是有關於一種晶片封裝結構及其製造方法。
因靜電放電(Electrostatic Discharge,ESD)產生的原因及其對積體電路放電的方式不同,目前靜電放電可區分為人體放電模式(Human-Body Model,HBM)、機器放電模式(Machine Model,MM)以及元件充電模式(Charged-Device Model,CDM)。為了防止積體電路因靜電放電現象而損壞,目前在積體電路中會加入靜電放電防護電路的設計。然而,這種作法增加了積體電路的製程複雜度,同時也增加了生產成本。另一種做法是將靜電放電防護電路製作於與晶片連接的中介板(interposer)上,但此作法不僅增加了中介板的製造成本,亦會增加整體封裝結構的厚度。
也就是說,在有限的晶片封裝結構中,為了提供晶片或是系統之靜電放電防護功能,若僅使用傳統的靜電放電防護設計方式將會面臨無法降低製造成本同時縮減晶片封裝結構尺寸的需求。因此,在不增加晶片封裝結構尺寸的情況下,如何將靜電放電防護功能整合至晶片或系統封裝結構中是目前研究人員亟欲解決的問題。
本發明實施例提供一種晶片封裝結構,其具有靜電防護的功能且具有較小的封裝體積及厚度。
本發明實施例還提供一種晶片封裝結構的製造方法,用以製作上述的晶片封裝結構。
本發明實施例的一種晶片封裝結構,其包括重分佈線路結構層、至少一晶片以及封裝膠體。重分佈線路結構層包括至少一重分佈線路、電性連接重分佈線路的至少一電晶體以及電性連接重分佈線路與電晶體的多個導電通孔。晶片設置於重分佈線路結構層上,且與重分佈線路結構層電性連接。封裝膠體設置於重分佈線路結構層上,且至少包覆晶片。
本發明實施例的一種晶片封裝結構的製造方法,至少包括下列步驟。形成重分佈線路結構層,其中重分佈線路結構層具有彼此相對的第一側與第二側。形成重分佈線路結構層包括形成至少一電晶體及多個導電通孔於第一側;以及形成至少一重分佈線路以電性連接電晶體,其中導電通孔電性連接重分佈線路與電晶體。翻轉重分佈線路結構層以設置至少一晶片於重分佈線路結構層的第二側上,其中晶片與重分佈線路結構層電性連接。形成封裝膠體於重分佈線路結構層上,以至少包覆晶片。
基於上述,在本發明實施例的晶片封裝結構的設計中,重分佈線路結構層至少包括重分佈線路、電晶體以及導電通孔,其中電晶體與晶片電性連接,可以提供靜電放電防護功能及/或對於晶片輸入訊號的調整與選擇功能,進而具有簡化製程、較小封裝體積及厚度與較少製作成本的優勢。
為讓本發明更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A至圖1H是本發明第一實施例的晶片封裝結構的製作方法的剖面示意圖。圖1A至圖1D示出將重分佈線路結構層110形成於第一載板10上的流程。重分佈線路結構層110可以包括至少一電晶體112、多個導電通孔114以及至少一重分佈線路116。
首先,請參照圖1A,提供一第一載板10,其中第一載板10例如是玻璃基板、矽基板、金屬基板、塑膠基板、其組合或其他適合的載板。
緊接著,請再參考圖1A,形成至少一電晶體112、第一導電通孔V1以及第一介電層D1於第一載板10上。在一些實施例中,可預先於第一載板10上形成離型層(未示出),使重分佈線路結構層110透過離型層而暫時地固定在第一載板10上,以便於後續製程中將第一載板10與重分佈線路結構層110分離。更進一步來說,本實施例的第一介電層D1包括依序堆疊的第一介電子層D1-1、第二介電子層D1-2以及第三介電子層D1-3。電晶體112包括半導體材料層1122、金屬材料層1124及導電材料層1126。
在一些實施例中,可以利用旋轉塗佈(spin-on coating)、沉積製程(deposition process)或其他適合的製作技術在第一載板10上形成第一介電子層D1-1。在一些實施例中,第一介電子層D1-1可以視為緩衝層。接著,可以在第一介電子層D1-1上形成半導體材料。舉例來說,半導體材料可以利用非晶矽(a-Si)、低溫多晶矽(Low Temperature Poly-Silicon,LTPS)、金屬氧化物製成,但並不以此為限。隨後,可以在半導體材料上利用沉積或其他適合的方式形成第二介電子層D1-2,以覆蓋半導體材料。然後,在第二介電子層D1-2上形成金屬材料,並將金屬材料圖案化,以形成電晶體112的金屬材料層1124。在一些實施例中,金屬材料層1124可以視為電晶體112的閘極(gate)或控制端。隨後,可以在金屬材料層1124上形成第三介電子層D1-3,以覆蓋金屬材料層1124。
接著,可以形成電晶體112的導電材料層1126。舉例來說,可以利用雷射鑽孔或其他適當的技術形成沿厚度方向貫穿該第三介電子層D1-3與第二介電子層D1-2的多個開孔,這些開孔可以環繞金屬材料層1124的圖案,並暴露出部分的半導體材料。在一些實施例中,還可以在金屬材料層1124上形成開孔,以暴露出部分的金屬材料層1124。接著,可以透過這些開孔來對半導體材料進行摻雜製程,以形成半導體材料層1122。在一些實施例中,半導體材料層1122可以視為電晶體112的通道層,其可包括未摻雜區與摻雜區。隨後,可以將導電材料形成於這些開孔中以及第三介電子層D1-3上,以電性接觸或直接接觸半導體材料層1122,且導電材料層1126環繞於金屬材料層1124。在一些實施例中,導電材料層1126還可以形成在暴露出部分的金屬材料層1124的開孔中,以電性連接金屬材料層1124。在一些實施例中,導電材料層1126可以視為包括汲極(drain)與源極(source),其分別連接並對應至半導體材料層1122兩端的摻雜區。在形成導電材料層1126之後,可以選擇性地於導電材料層1126上形成其他介電子層,以覆蓋導電材料層1126。此處,本發明的實施例並不限制介電子層的數量。
在一些實施例中,可以在形成電晶體112的過程中(例如在形成第一介電子層D1-1之後、在形成電晶體112的金屬材料層1124的期間或是其他適合的電晶體112製程階段中),在電晶體112的周圍形成第一重分佈線路C1。在一些實施例中,可於第一重分佈線路C1上形成電性連接至第一重分佈線路C1的第一導電通孔V1。第一重分佈線路C1與第一導電通孔V1可以是由相同或相似的金屬材料形成,例如銅、鋁、銀及其合金等,但並不限於此。舉例來說,電晶體112的導電材料層1126的尺寸可以小於第一導電通孔V1的尺寸。
接著,請參考圖1B,可以透過例如旋塗製程、鍍覆製程、沉積製程、微影蝕刻製程或其他適合的製作技術,在第一介電層D1上形成阻障層118。由於在隨後形成於電晶體112上的線路中可能包括擴散係數高的金屬離子(例如銅離子)。若這些金屬原子擴散至電晶體112中,則容易造成電晶體112的特性退化,因此藉由設置阻障層118,以提升電晶體112的電性可靠度及接合強度。阻障層118的材料可以包括氮化矽(SiNx)、氧化矽(SiOx)或氮化鈦(TiNx),然本發明的實施例並不以此為限,其他適合的阻擋金屬離子(例如銅離子)的阻障材料也可應用於本發明的實施例中。在一些實施例中,阻障層118可以具有多個開口118a,以暴露出部分的第一導電通孔V1與導電材料層1126,以利後續電性連接。
請參考圖1C,在形成阻障層118之後,可以在阻障層118上交替地形成第二重分佈線路C2、第二介電層D2、第二導電通孔V2、第三重分佈線路C3、第三介電層D3及第三導電通孔V3。舉例來說,可以將導電材料形成於阻障層118上以及開口118a(請參考圖1B)中,並圖案化導電材料,以形成第二重分佈線路C2。在一些實施例中,可以將介電材料形成於阻障層118上,以覆蓋第二重分佈線路C2,並經過雷射鑽孔或其他適合的製作技術以移除部分的介電材料而形成多個開口,而這些開口暴露出部分的第二重分佈線路C2,而形成第二介電層D2。藉此,阻障層118夾在第一介電層D1與第二介電層D2之間,並且位於重分佈線路C2以及電晶體112的半導體材料層1122(請參考圖1A)之間,以防止電晶體112受到重分佈線路C2的離子(例如銅離子)擴散之影響。
隨後,可以將導電材料形成於這些開口中,以形成第二導電通孔V2。接著,可以在第二導電通孔V2上形成第三重分佈線路C3。在一些實施例中,第二導電通孔V2與形成於其上的第三重分佈線路C3可以於同一製程中製作。例如可以將導電材料形成於第二介電層D2的開口中以及第二介電層D2上,並圖案化導電材料,以在第二介電層D2上形成第三重分佈線路C3。在形成第三重分佈線路C3之後,可以利用類似的方式形成第三介電層D3以及第三導電通孔V3,於此便不再贅述。應當理解的是,可以視實際設計需求,來決定重分佈線路與介電層的層數或導電通孔的數量,其可以是單層或多層,圖1C僅為示例,本發明的實施例並不限於此。在其他實施例中,阻障層118也可以視設計需求而形成在第二介電層D2及第三介電層D3之間,本發明的實施例並不限制阻障層118的設置數量。
更進一步來說,本實施例的重分佈線路結構層110中的多個介電層中的任一層(例如第一介電層D1、第二介電層D2或第三介電層D3)具有厚度Ta。電晶體112所在的第二介電子層D1-2(請參考圖1A)及第三介電子層D1-3(請參考圖1A)的厚度總和Tb,銅阻障層118具有厚度Tc。在一些實施例中,介電層中的任一層的厚度Ta大於電晶體112所在的第二介電子層D1-2(請參考圖1A)及第三介電子層D1-3的厚度總和Tb。舉例來說,介電層中的任一層的厚度Ta可以大約介於0.1微米(μm)至20μm之間,厚度總和Tb介於約500奈米(nm)至約1000 nm之間。在一些實施例中,電晶體112所在的第二介電子層D1-2(請參考圖1A)及第三介電子層D1-3的厚度總和Tb大於銅阻障層118的厚度Tc。舉例來說,阻障層118的厚度Tc可以介於約5 nm至約500nm之間。重分佈線路116中的任一者(例如第一重分佈線路C1、第二重分佈線路C2或第三重分佈線路C3)的厚度Td可以大約介於2 μm至8μm之間。在本實施例重分佈線路結構層110中的製程中,先製作需要在相對較高溫的製程環境(例如約300度至400度之間)進行的電晶體112製程,隨後再於電晶體112上製作在相對較低溫的製程環境(例如約200度)進行的重分佈線路116製程,因此不會傷害到底部的電晶體112。
接著,請參照圖1D及圖1E,形成保護膜層20於重分佈線路結構層110上。舉例來說,重分佈線路結構層110具有彼此相對的第一側S1與第二側S2。第一側S1可以接觸第一載板10,且電晶體112及第一導電通孔V1形成在且位於第一側S1。保護膜層20可以設置第二側S2上,以使重分佈線路結構層110位於第一載板10與保護膜層20之間。舉例來說,保護膜層20可以具有足夠的剛性,以在隨後的製程中提供支撐。在一些實施例中,保護膜層20可以包括離型膜,以便之後自重分佈線路結構層110的第二側S2剝離。在形成保護膜層20之後,可以進行剝離製程及轉板製程。在一些實施例中,可以先進行剝離製程,以將第一載板10自重分佈線路結構層110的第一側S1剝離,而暴露出第一介電層D1的表面,隨後,再進行轉板製程,將重分佈線路結構層110上下翻轉180度,以使重分佈線路結構層110的第一側S1朝上,便於後續於第一介電層D1上進行製程。在其他實施例中,也可以先進行轉板製程再進行剝離製程,然本發明的實施例並不以此為限。
請參照圖1F,在執行剝離製程之後,可以將至少一個晶片120設置在重分佈線路結構層110的第一側S1上,以靠近電晶體112。舉例來說,晶片120的主動表面120a上可以設置有多個接墊122,可以藉由覆晶的方式將晶片120的接墊122與位於電晶體112周圍的第一導電通孔V1及/或第一重分佈線路C1電性連接,以縮短晶片120與電晶體112之間電性傳導的距離。在一些實施例中,完成剝離製程之後,此時第一介電層D1(例如圖1A所示的第一介電子層D1-1)覆蓋第一導電通孔V1及第一重分佈線路C1,可以透過雷射穿孔或其他適合的製作技術在重分佈線路結構層110的第一側S1上,即第一介電層D1上,形成多個開口,以暴露出第一導電通孔V1及/或第一重分佈線路C1,隨後,可以將導電性較高的金屬(例如錫)填入這些開孔中,再與晶片120電性連接,藉此可降低晶片120與重分佈線路結構層110的阻抗。在其他實施例中,晶片120也可以利用錫球或其他適合的方式電性連接至重分佈線路結構層110,本發明實施例的製作技術並不限於此。
在設置晶片120之後,可以形成封裝膠體130於重分佈線路結構層110的第一側S1上。舉例來說,封裝膠體130可以透過模塑製程(molding process)將模塑材料(例如環氧樹脂)或其他適合的介電材料形成於重分佈線路結構層110的第一側S1上,以至少包覆晶片120,使晶片120與外界環境隔絕,然本發明實施例的封裝膠體130的材料與製作技術並不以此為限。
請參照圖1G及圖1H,在形成封裝膠體130之後,可以選擇性地將保護膜層20自重分佈線路結構層110的第二側S2剝離,以暴露出第三介電層D3的表面。隨後,設置載板140於重分佈線路結構層110的第二側S2,其中載板140透過重分佈線路結構層110的導電通孔114電性連接至晶片120。在一些實施例中,載板140可以是印刷電路板、半導體積體電路載板或是半導體製程晶圓之基板,然本發明的實施例並不以此為限。舉例來說,載板140上可以具有多個接墊142,可以將載板140的接墊142與重分佈線路層110的第三導電通孔V3結合,以使晶片120透過重分佈線路結構層110與載板140電性連接。至此,已完成晶片封裝結構100A的製程。舉例來說,晶片封裝結構100A可以在面板級封裝(panel-level package,PLP)製程中進行,也就是說可以在面板階段完成封裝步驟後,再予以切割成獨立的晶片封裝結構100A。在其他實施例中,也可以在晶圓級封裝(wafer level packaging,WLP)製程中進行,本發明並不以此為限。
圖2是本發明第二實施例的晶片封裝結構的剖面示意圖。本實施例的晶片封裝結構100B類似於圖1H的晶片封裝結構100A,因此相同或相似的標號表示相同或相似的構件,故針對圖1A至圖1H中所說明過的構件於此便不再贅述。請參照圖2,晶片封裝結構100B包括設置於重分佈線路結構層110-B上的晶片120-A及120-B,且晶片120-A及120-B可以透過重分佈線路結構層110-B而彼此電性連接。在一些實施例,晶片120-A及120-B可以是具有相同功能的晶片。在其他實施例中,晶片120-A及120-B也可以具有不同的功能。舉例來說,晶片120-A及120-B包括邏輯晶片、記憶體晶片、輸入/輸出晶片等,然本發明的實施例並不以此為限。應當理解的是,雖然圖2中繪示兩個晶片,但在其他實施例中,晶片封裝結構中的晶片數量也可以視設計需求而配置多於兩個晶片,本發明的實施例並不限制晶片的數量。
在本實施例中,位於第一介電層D1中的電晶體可以是具有靜電放電防護功能的薄膜電晶體(在圖2中標示為ESD)。舉例來說,可以設置至少兩個靜電放電防護電晶體ESD藉由重分佈線路結構層110-B以分別與晶片120-A及120-B電性連接。在一些實施例中,設置在靜電放電防護電晶體ESD周圍的第一導電通孔V1與設置在靜電放電防護電晶體ESD上的導電材料層 1126(見圖1A)可以透過重分佈線路116及位於其他層中的導電通孔114使靜電放電防護電晶體ESD與晶片120-A及120-B電性連接電性連接。至少一部份的這些導電通孔114(包括第一導電通孔V1或靜電放電防護電晶體ESD的導電材料層 1126以及其他層中的導電通孔)與至少一部份的重分佈線路116可以構成電壓源線路Vdd及接地線路Vss。在一些實施例中,這些彼此電性連接的晶片120-A、120-B可以共用電壓源線路Vdd及接地線路Vss。
在一些實施例中,晶片120-A、120-B的至少一端可以設置輸出輸入(I/O)的接腳PIN。一般來說,靜電放電可能會透過接腳PIN進入晶片中。本發明的實施例藉由在形成重分佈線路結構層110-B的過程中形成靜電放電防護電晶體ESD,可以防範靜電放電對晶片120-A、120-B的功能電路造成損傷。此外,相較於傳統設置靜電放電防護元件的做法,本發明的實施例的設置方式可大幅減少靜電放電防護電晶體於晶片封裝結構中所占的面積,亦無須設置包含靜電放電防護元件的中介板,藉此可節省製造成本。舉例來說,在本實施例中,靜電放電防護電晶體ESD可以設置在靠近晶片120-A及120-B的一側,以就近釋放靜電放電電流。在一些實施例中,靜電放電防護電晶體ESD包括與連接的第一端E1及第二端E2。在一些實施例中,靜電放電防護電晶體ESD還包括與晶片120-A及120-B的接腳PIN電性連接的第三端E1。應當理解的是,雖然在圖2中,第一端E1、第二端E2及第三端E3是依序由左至右配置於同一側,但在其他實施例中,也可以視設計需求而有不同的順序配置或是配置於靜電放電防護電晶體ESD的不同側上。舉例來說,靜電放電防護電晶體ESD的第一端E1可以電性連接至電壓源線路Vdd,靜電放電防護電晶體ESD的第二端E2可以電性連接至接地線路Vss,藉此可將突波電流導入電壓源線路Vdd及接地線路Vss,以避免損害晶片120-A及120-B。
圖3是本發明第三實施例的晶片封裝結構的剖面示意圖。本實施例的晶片封裝結構100C類似於圖1H的晶片封裝結構100A及圖2的晶片封裝結構100B,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖3,在晶片封裝結構100C的重分佈線路結構層110-C中,靜電放電防護電晶體ESD例如是配置在第二介電層D2,且第二介電層D2的相對兩側上可以分別配置阻障層118-A、118-B,以阻隔靜電放電防護電晶體ESD與位於其他介電層(例如第一介電層D1及/或第三介電層D3)上的重分佈線路116。
舉例來說,可以先在第一載板上先形成阻障層118-A,接著在阻障層118-A上進行電晶體製程,以形成靜電放電防護電晶體ESD及第二介電層D2及位於第二介電層D2中的重分佈線路與導電通孔。接著,形成阻障層118-B,然後在阻障層118-B上形成第三介電層D3及位於第三介電層D3中的重分佈線路與導電通孔於第二介電層D2上。隨後,再進行保護膜層的貼合、取下第一載板後以及進行轉板製程之後,於第二介電層D2相對於第三介電層D3的另一側形成第一介電層D1及位於第一介電層D1中的重分佈線路與導電通孔。之後,再將晶片120設置在第一介電層D1上。接著,再將保護膜層移除,以將載板150接合至第三介電層D3。
在本實施例中,圖3的靜電放電防護電晶體ESD的第三端E3、第一端E1及第二端E2繪示為依序由左至右配置,以分別電性連接至晶片120的接腳PIN、電壓源線路Vdd及接地線路Vss。在其他實施例中,晶片封裝結構100C也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-C將這些晶片彼此電性連接。
圖4是本發明第四實施例的晶片封裝結構的剖面示意圖。請參照圖4,本實施例的晶片封裝結構100D的重分佈線路結構層110-D中可以配置於載板150上,且靜電放電防護電晶體ESD設置於第三介電層D3中。舉例來說,可以在第一載板上進行電晶體製程,以形成靜電放電防護電晶體ESD、第三介電層D3及位於第三介電層D3中的重分佈線路與導電通孔。接著,在第三介電層D3上形成阻障層118。其次,在阻障層118上形成第二介電層D2及位於其中的重分佈線路與導電通孔,然後在第二介電層D2上形成第一介電層D1及位於其中的重分佈線路與導電通孔。隨後,再取下第一載板,以分別在第一介電層D1及第三介電層D3設置晶片120與載板150。也就是說,相較於圖1A至圖1H所述的方法,形成本實施例的晶片封裝結構100D,在形成重分佈線路結構層110-D之後,無須進行轉板製程。因此,在本實施例中,靜電放電防護電晶體ESD是位於重分佈線路結構層110-D連接載板150的第一側S1,並遠離晶片120所在的第二側S2。舉例來說,載板150包括玻璃基板、陶瓷基板或其他適合的載板,載板150中可以不具有線路。在一些實施例中,晶片封裝結構100D也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-D將這些晶片彼此電性連接。在其他實施例中,載板150也可以是類似於圖1H的載板,藉由載板上的接墊直接與重分佈線路結構層110-D電性連接,於此便不再贅述。
圖5是本發明第五實施例的晶片封裝結構的剖面示意圖。本實施例的晶片封裝結構100E類似於圖4的晶片封裝結構100D,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖5,本實施例的晶片封裝結構100E與圖4的晶片封裝結構100D之間的差異例如在於,本實施例的靜電放電防護電晶體ESD配置於第二介電層D2,故重分佈線路結構層110-E包括至少兩個阻障層118-A、118-B分別配置在靜電放電防護電晶體ESD所在的第二介電層D2的相對兩側上。本實施例的晶片封裝結構100E的形成方式可以類似於圖3的晶片封裝結構100C的形成方式,於此便不再贅述。在其他實施例中,晶片封裝結構100E也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-E將這些晶片彼此電性連接。
圖6是本發明第六實施例的晶片封裝結構的剖面示意圖。本實施例的晶片封裝結構100F類似於圖1H的晶片封裝結構100A,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖6,在晶片封裝結構100F的重分佈線路結構層110-F中,位於第一介電層D1中的電晶體可以是具有開關控制功能的薄膜電晶體(在圖6中標示為SWT)。開關控制電晶體SWT可以透過重分佈線路116及/或導電通孔114以與晶片120-C電性連接,藉此可以對晶片120-C進行輸入訊號的調整與選擇。舉例來晶片120-C可以包括連接於重分佈線路結構層110-F中的電壓源線路Vdd的電壓源端F1、連接於重分佈線路結構層110-F中的接地線路Vss的接地端F2以及連接於開關控制電晶體SWT的第三端E3的接腳端F3。在一些實施例中,開關控制電晶體SWT可以透過位於第一介電層D1中的重分佈線路116與晶片120-C的接腳端F3電性連接。在其他實施例中,晶片封裝結構100F也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-F將這些晶片彼此電性連接,這些彼此電性連接的晶片例如可以共用電壓源線路Vdd及接地線路Vss。
圖7是本發明第七實施例的晶片封裝結構的剖面示意圖。本實施例的晶片封裝結構100G類似於圖6的晶片封裝結構100F,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖7,晶片120-D可以包括多個接腳端F3,且這些接腳端F3中的任一者可以與開關控制電晶體SWT電性連接。在本實施例的晶片封裝結構100G的重分佈線路結構層110-G中,開關控制電晶體SWT例如是形成在第二介電層D2中,且第二介電層D2的相對兩側上可以分別配置阻障層118-A、118-B,以阻隔開關控制電晶體SWT與位於其他介電層(例如第一介電層D1及/或第三介電層D3)中的重分佈線路116。在其他實施例中,晶片封裝結構100G也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-G將這些晶片彼此電性連接,這些彼此電性連接的晶片例如可以共用電壓源線路Vdd及接地線路Vss。
圖8是本發明第八實施例的晶片封裝結構的剖面示意圖。本實施例的晶片封裝結構100H類似於圖7的晶片封裝結構100G,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖8,本實施例的晶片封裝結構100H的重分佈線路結構層110-H中可以類似於圖4的晶片封裝結構100D,將重分佈線路結構層110-H形成於載板150上。也就是說,重分佈線路結構層110-H可以依照圖1A至圖1C所述的方法形成至載板150上,之後無須進行貼附保護膜層、轉板製程及剝離製程,而直接將晶片120-D設置於重分佈線路結構層110-H上。因此,在本實施例中,開關控制電晶體SWT於第二介電層D2中的位置是靠近載板150的一側,而在圖7所示的實施例中,開關控制電晶體SWT於第二介電層D2中的位置是靠近晶片120-D的一側。在其他實施例中,晶片封裝結構100H也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-H將這些晶片彼此電性連接,這些彼此電性連接的晶片例如可以共用電壓源線路Vdd及接地線路Vss。
圖9是本發明第九實施例的晶片封裝結構的剖面示意圖。本實施例的晶片封裝結構100I類似於圖8的晶片封裝結構100H,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖9,晶片封裝結構100I中的開關控制電晶體SWT是位於重分佈線路結構層110-I連接載板150的第一側S1,並遠離晶片120-D所在的第二側S2。本實施例的晶片封裝結構100I與圖8的晶片封裝結構100H之間的差異還包括,本實施例的晶片封裝結構100I配置單一阻障層118。
圖10是本發明第十實施例的晶片封裝結構的剖面示意圖。請參照圖10,本實施例的晶片封裝結構100J包括多個不同功能的電晶體,例如靜電放電防護電晶體ESD及開關控制電晶體SWT。本實施例的晶片封裝結構100J的配置方式類似圖6的晶片封裝結構100F結合圖1H的晶片封裝結構100A,靜電放電防護電晶體ESD及開關控制電晶體SWT可以同時配置在靠近晶片120-E一側的介電層中,細節於此便不再贅述。晶片封裝結構100J可以在不增加結構尺寸與製程複雜度的條件下,透過靜電放電防護電晶體ESD來避免瞬間大量的靜電放電電流的湧入而造成損壞,同時能夠運用開關控制電晶體SWT對晶片120-E進行輸入訊號的調整與選擇。在其他實施例中,晶片封裝結構100J也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-J將這些晶片彼此電性連接,這些彼此電性連接的晶片例如可以共用電壓源線路Vdd及接地線路Vss。
圖11是本發明第十一實施例的晶片封裝結構的剖面示意圖。本實施例的晶片封裝結構100K類似於圖10的晶片封裝結構100J,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖11,晶片封裝結構100K的配置方式類似圖3的晶片封裝結構100C結合圖7的晶片封裝結構100G,靜電放電防護電晶體ESD及開關控制電晶體SWT可以同時配置在第二介電層D2中,且阻障層118-A、118-B可以分別配置在第二介電層D2的相對兩側上,細節於此便不再贅述。在其他實施例中,晶片封裝結構100K也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-K將這些晶片彼此電性連接,這些彼此電性連接的晶片例如可以共用電壓源線路Vdd及接地線路Vss。
圖12是本發明第十二實施例的晶片封裝結構的剖面示意圖。請參照圖12,本實施例的晶片封裝結構100L類似於圖11的晶片封裝結構100K,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖12,晶片封裝結構100L的配置方式類似圖5的晶片封裝結構100E結合圖8的晶片封裝結構100H,靜電放電防護電晶體ESD及開關控制電晶體SWT可以同時配置在第二介電層D2中靠近載板150的一側,細節於此便不再贅述。在其他實施例中,晶片封裝結構100L也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-L將這些晶片彼此電性連接,這些彼此電性連接的晶片例如可以共用電壓源線路Vdd及接地線路Vss。
圖13是本發明第十三實施例的晶片封裝結構的剖面示意圖。請參照圖13,本實施例的晶片封裝結構100M類似於圖12的晶片封裝結構100L,因此相同或相似的標號表示相同或相似的構件,於此便不再贅述。請參照圖13,晶片封裝結構100M的配置方式類似圖4的晶片封裝結構100D結合圖9的晶片封裝結構100I,靜電放電防護電晶體ESD及開關控制電晶體SWT可以同時配置在連接於載板150的第一側S1,細節於此便不再贅述。在其他實施例中,晶片封裝結構100M也可以配置成類似圖2包括多個晶片的晶片封裝結構,並透過重分佈線路結構層110-M將這些晶片彼此電性連接,這些彼此電性連接的晶片例如可以共用電壓源線路Vdd及接地線路Vss。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧第一載板
20‧‧‧保護膜層
100A、100B、100C、100D、100E、100F、100G、100H、100I、100J、100K、100L、100M‧‧‧晶片封裝結構
110、110-B、110-C、110-D、110-E、110-F、110-G、110-H、110-I、110-J、110-K、110-L、110-M‧‧‧重分佈線路結構層
112‧‧‧電晶體
1122‧‧‧半導體材料層
1124‧‧‧金屬材料層
1126‧‧‧導電材料層
114‧‧‧導電通孔
116‧‧‧重分佈線路
118、118-A、118-B‧‧‧阻障層
118a‧‧‧開口
120、120-A、120-B、120-C、120-D、120-E‧‧‧晶片
120a‧‧‧主動表面
122‧‧‧接墊
130‧‧‧封裝膠體
140、150‧‧‧載板
142‧‧‧接墊
C1‧‧‧第一重分佈線路
C2‧‧‧第二重分佈線路
C3‧‧‧第三重分佈線路
D1‧‧‧第一介電層
D1-1‧‧‧第一介電子層
D1-2‧‧‧第二介電子層
D1-3‧‧‧第三介電子層
D2‧‧‧第二介電層
D3‧‧‧第三介電層
ESD‧‧‧靜電放電防護電晶體
E1‧‧‧第一端
E2‧‧‧第二端
E3‧‧‧第三端
F1‧‧‧電壓源端
F2‧‧‧接地端
F3‧‧‧接腳端
PIN‧‧‧接腳
S1‧‧‧第一側
S2‧‧‧第二側
SWT‧‧‧開關控制電晶體
Ta、Tc、Td‧‧‧厚度
Tb‧‧‧厚度總和
V1‧‧‧第一導電通孔
V2‧‧‧第二導電通孔
V3‧‧‧第三導電通孔
Vdd‧‧‧電壓源線路
Vss‧‧‧接地線路
圖1A至圖1H是本發明第一實施例的晶片封裝結構的製作方法的剖面示意圖。 圖2是本發明第二實施例的晶片封裝結構的剖面示意圖。 圖3是本發明第三實施例的晶片封裝結構的剖面示意圖。 圖4是本發明第四實施例的晶片封裝結構的剖面示意圖。 圖5是本發明第五實施例的晶片封裝結構的剖面示意圖。 圖6是本發明第六實施例的晶片封裝結構的剖面示意圖。 圖7是本發明第七實施例的晶片封裝結構的剖面示意圖。 圖8是本發明第八實施例的晶片封裝結構的剖面示意圖。 圖9是本發明第九實施例的晶片封裝結構的剖面示意圖。 圖10是本發明第十實施例的晶片封裝結構的剖面示意圖。 圖11是本發明第十一實施例的晶片封裝結構的剖面示意圖。 圖12是本發明第十二實施例的晶片封裝結構的剖面示意圖。 圖13是本發明第十三實施例的晶片封裝結構的剖面示意圖。

Claims (20)

  1. 一種晶片封裝結構,包括: 重分佈線路結構層,包括: 至少一重分佈線路; 至少一電晶體,電性連接所述至少一重分佈線路;以及 多個導電通孔,電性連接所述至少一重分佈線路與所述至少一電晶體; 至少一晶片,設置於所述重分佈線路結構層上,且與所述重分佈線路結構層電性連接;以及 封裝膠體,設置於所述重分佈線路結構層上,且至少包覆所述至少一晶片。
  2. 如申請專利範圍第1項所述的晶片封裝結構,其中所述重分佈線路結構層更包括多個介電層,所述多個介電層其中的一個包括依序堆疊的第一介電子層、第二介電子層以及第三介電子層,而所述至少一電晶體位於所述多個介電層中,且所述至少一電晶體包括: 半導體材料層,位於所述第二介電子層中; 金屬材料層,位於所述第三介電子層中;以及 導電材料層,貫穿所述第三介電子層與所述第二介電子層而連接至所述半導體材料層,且所述導電材料層環繞所述金屬材料層。
  3. 如申請專利範圍第2項所述的晶片封裝結構,其中所述半導體材料層包括多晶矽半導體層、金屬氧化物半導體層或非晶矽半導體層。
  4. 如申請專利範圍第2項所述的晶片封裝結構,其中所述重分佈線路結構層更包括: 至少一阻障層,設置於所述至少一重分佈線路與所述至少一電晶體的所述半導體材料層之間。
  5. 如申請專利範圍第4項所述的晶片封裝結構,其中所述多個介電層中任一層的厚度大於所述第二介電子層的厚度加上所述第三介電子層的厚度的總和,且所述第二介電子層的厚度加上所述第三介電子層的厚度的總和大於所述至少一阻障層的厚度。
  6. 如申請專利範圍第5項所述的晶片封裝結構,其中所述至少一阻障層的所述厚度介於5奈米至500奈米之間。
  7. 如申請專利範圍第5項所述的晶片封裝結構,其中所述多個介電層中任一層的所述厚度介於0.1微米至20微米之間。
  8. 如申請專利範圍第4項所述的晶片封裝結構,其中所述至少一阻障層的材質包括氮化矽、氧化矽或氮化鈦。
  9. 如申請專利範圍第1項所述的晶片封裝結構,其中所述至少一電晶體具有第一端與第二端,所述至少一重分佈線路包括電壓源線路及接地線路,所述至少一電晶體的所述第一端電性連接至所述電壓源線路,且所述至少一電晶體的所述第二端電性連接至所述接地線路。
  10. 如申請專利範圍第1項所述的晶片封裝結構,更包括: 載板,所述至少一晶片與所述載板分別位於所述重分佈線路結構層的相對兩側,其中所述載板透過所述重分佈線路結構層的所述多個導電通孔電性連接至所述至少一晶片。
  11. 如申請專利範圍第1項所述的晶片封裝結構,其中所述至少一重分佈線路的厚度介於2微米至8微米之間。
  12. 如申請專利範圍第1項所述的晶片封裝結構,其中所述至少一電晶體包括靜電放電防護電晶體或開關控制電晶體。
  13. 一種晶片封裝結構的製造方法,包括: 形成重分佈線路結構層,其中所述重分佈線路結構層具有彼此相對的第一側與第二側,形成所述重分佈線路結構層包括: 形成至少一電晶體及多個導電通孔於所述第一側;以及 形成至少一重分佈線路以電性連接所述至少一電晶體,其中所述導電通孔電性連接所述至少一重分佈線路與所述至少一電晶體; 設置至少一晶片於所述重分佈線路結構層的所述第二側上,其中所述至少一晶片與所述重分佈線路結構層電性連接;以及 形成封裝膠體於所述重分佈線路結構層上,以至少包覆所述至少一晶片。
  14. 如申請專利範圍第13項所述的晶片封裝結構的製造方法,更包括: 將所述重分佈線路結構層形成於第一載板上,其中所述重分佈線路結構層的所述第一側接觸所述第一載板;以及 翻轉所述重分佈線路結構層,並於設置所述至少一晶片之前,移除所述第一載板,以暴露所述重分佈線路結構層的所述第一側。
  15. 如申請專利範圍第14項所述的晶片封裝結構的製造方法,更包括: 在形成所述重分佈線路結構層之後,設置保護膜層於所述重分佈線路結構層的所述第二側上,以使所述重分佈線路結構層位於所述第一載板與所述保護膜層之間;以及 在形成所述封裝膠體於所述重分佈線路結構層上之後,移除所述保護膜層,以暴露出所述重分佈線路結構層的所述第二側。
  16. 如申請專利範圍第15項所述的晶片封裝結構的製造方法,更包括: 在移除所述保護膜層之後,設置載板於所述重分佈線路結構層的所述第二側,其中所述載板透過所述重分佈線路結構層的所述多個導電通孔電性連接至所述至少一晶片。
  17. 如申請專利範圍第13項所述的晶片封裝結構的製造方法,其中所述重分佈線路結構層更包括多個介電層,所述多個介電層其中的一個包括依序堆疊的第一介電子層、第二介電子層以及第三介電子層,形成所述至少一電晶體包括: 形成半導體材料層於所述第一介電子層上; 形成所述金屬材料層於所述第二介電子層上;以及 形成所述導電材料層以貫穿所述第三介電子層與所述第二介電子層而連接至所述半導體材料層,其中所述導電材料層環繞所述金屬材料層。
  18. 如申請專利範圍第17項所述的晶片封裝結構的製造方法,其中形成所述重分佈線路結構層更包括: 形成至少一阻障層於所述多個介電層中,其中所述至少一阻障層位於至少一重分佈線路與所述至少一電晶體的所述半導體材料層之間。
  19. 如申請專利範圍第18項所述的晶片封裝結構的製造方法,其中所述多個介電層中任一層的厚度大於所述第二介電子層的厚度加上所述第三介電子層的厚度的總和,且所述第二介電子層的厚度加上所述第三介電子層的厚度的總和大於所述至少一阻障層的厚度。
  20. 如申請專利範圍第13項所述的晶片封裝結構的製造方法,其中所述至少一電晶體包括靜電放電防護電晶體或開關控制電晶體。
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