TW201947731A - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A chip package structure including a redistribution structure layer, at least one chip and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuitry, at least one transistor electrically connected to the redistribution circuitry, and a plurality of conductive vias electrically connected to the redistribution circuitry and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

Description

Chip package structure and manufacturing method thereof

The invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof.

Due to the causes of Electrostatic Discharge (ESD) and the way in which they are discharged to the integrated circuit, the current electrostatic discharge can be divided into Human-Body Model (HBM) and Machine Model (MM) And component charging mode (Charged-Device Model, CDM). In order to prevent the integrated circuit from being damaged by the electrostatic discharge phenomenon, the design of the electrostatic discharge protection circuit is currently added to the integrated circuit. However, this method increases the complexity of the integrated circuit manufacturing process and also increases the production cost. Another method is to make the ESD protection circuit on the interposer connected to the chip, but this method not only increases the manufacturing cost of the interposer, but also increases the thickness of the overall packaging structure.

In other words, in a limited chip package structure, in order to provide the electrostatic discharge protection function of the chip or the system, if only the traditional electrostatic discharge protection design method is used, there will be a need to reduce the manufacturing cost and reduce the size of the chip package structure. Therefore, without increasing the size of the chip package structure, how to integrate the electrostatic discharge protection function into the chip or system package structure is a problem that researchers currently want to solve.

An embodiment of the present invention provides a chip packaging structure, which has a function of electrostatic protection and has a small package volume and thickness.

An embodiment of the present invention also provides a method for manufacturing a chip packaging structure, which is used to fabricate the above chip packaging structure.

A chip packaging structure according to an embodiment of the present invention includes a redistribution circuit structure layer, at least one chip, and a packaging gel. The redistribution circuit structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution circuit structure layer and is electrically connected to the redistribution circuit structure layer. The encapsulating gel is disposed on the redistribution circuit structure layer and at least covers the wafer.

A method for manufacturing a chip package structure according to an embodiment of the present invention includes at least the following steps. A redistribution line structure layer is formed, wherein the redistribution line structure layer has a first side and a second side opposite to each other. Forming the redistribution circuit structure layer includes forming at least one transistor and a plurality of conductive vias on the first side; and forming at least one redistribution circuit to electrically connect the transistor, wherein the conductive vias electrically connect the redistribution circuit and the transistor. The redistribution circuit structure layer is turned over to set at least one wafer on the second side of the redistribution circuit structure layer, wherein the wafer is electrically connected to the redistribution circuit structure layer. Forming an encapsulant on the redistribution circuit structure layer to at least cover the wafer.

Based on the above, in the design of the chip packaging structure according to the embodiment of the present invention, the redistribution circuit structure layer includes at least a redistribution circuit, a transistor, and a conductive via, wherein the transistor is electrically connected to the chip, which can provide electrostatic discharge protection and / Or the function of adjusting and selecting the input signal of the chip, which has the advantages of simplifying the manufacturing process, smaller packaging volume and thickness, and less manufacturing cost.

In order to make the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

1A to 1H are schematic cross-sectional views of a method for manufacturing a chip package structure according to a first embodiment of the present invention. 1A to 1D illustrate a process of forming a redistribution circuit structure layer 110 on a first carrier board 10. The redistribution circuit structure layer 110 may include at least one transistor 112, a plurality of conductive vias 114, and at least one redistribution circuit 116.

First, referring to FIG. 1A, a first carrier board 10 is provided. The first carrier board 10 is, for example, a glass substrate, a silicon substrate, a metal substrate, a plastic substrate, a combination thereof, or other suitable substrates.

Next, referring to FIG. 1A again, at least one transistor 112, a first conductive via V1, and a first dielectric layer D1 are formed on the first carrier board 10. In some embodiments, a release layer (not shown) may be formed on the first carrier board 10 in advance, so that the redistribution circuit structure layer 110 is temporarily fixed on the first carrier board 10 through the release layer, so as to facilitate In a subsequent process, the first carrier board 10 is separated from the redistribution circuit structure layer 110. Furthermore, the first dielectric layer D1 in this embodiment includes a first dielectric electron layer D1-1, a second dielectric electron layer D1-2, and a third dielectric electron layer D1-3 which are sequentially stacked. The transistor 112 includes a semiconductor material layer 1122, a metal material layer 1124, and a conductive material layer 1126.

In some embodiments, the first dielectric layer D1-1 may be formed on the first carrier plate 10 by using a spin-on coating, a deposition process, or other suitable manufacturing techniques. In some embodiments, the first dielectric layer D1-1 may be regarded as a buffer layer. Next, a semiconductor material may be formed on the first dielectric layer D1-1. For example, the semiconductor material can be made of amorphous silicon (a-Si), low temperature poly-silicon (LTPS), or metal oxide, but it is not limited thereto. Subsequently, a second dielectric layer D1-2 may be formed on the semiconductor material by deposition or other suitable methods to cover the semiconductor material. Then, a metal material is formed on the second dielectric layer D1-2, and the metal material is patterned to form a metal material layer 1124 of the transistor 112. In some embodiments, the metal material layer 1124 may be regarded as a gate or a control terminal of the transistor 112. Subsequently, a third dielectric layer D1-3 may be formed on the metal material layer 1124 to cover the metal material layer 1124.

Next, a conductive material layer 1126 of the transistor 112 may be formed. For example, laser drilling or other appropriate techniques may be used to form a plurality of openings penetrating the third dielectric layer D1-3 and the second dielectric layer D1-2 along the thickness direction. These openings may surround the metal The pattern of the material layer 1124 exposes a portion of the semiconductor material. In some embodiments, openings can also be formed in the metal material layer 1124 to expose a portion of the metal material layer 1124. Then, the semiconductor material can be doped through these openings to form a semiconductor material layer 1122. In some embodiments, the semiconductor material layer 1122 may be regarded as a channel layer of the transistor 112, which may include an undoped region and a doped region. Subsequently, a conductive material may be formed in the openings and on the third dielectric layer D1-3 to electrically or directly contact the semiconductor material layer 1122, and the conductive material layer 1126 surrounds the metal material layer 1124. In some embodiments, the conductive material layer 1126 may also be formed in the opening of the exposed metal material layer 1124 to electrically connect the metal material layer 1124. In some embodiments, the conductive material layer 1126 can be regarded as including a drain and a source, which are respectively connected to and correspond to the doped regions at both ends of the semiconductor material layer 1122. After the conductive material layer 1126 is formed, other dielectric layers can be selectively formed on the conductive material layer 1126 to cover the conductive material layer 1126. Here, the embodiments of the present invention do not limit the number of dielectric layers.

In some embodiments, during the process of forming the transistor 112 (for example, after forming the first dielectric layer D1-1, during the formation of the metal material layer 1124 of the transistor 112, or other suitable transistor 112 processes) Stage), a first redistribution line C1 is formed around the transistor 112. In some embodiments, a first conductive via V1 electrically connected to the first redistribution line C1 may be formed on the first redistribution line C1. The first redistribution line C1 and the first conductive via V1 may be formed of the same or similar metal materials, such as copper, aluminum, silver, and alloys thereof, but are not limited thereto. For example, the size of the conductive material layer 1126 of the transistor 112 may be smaller than the size of the first conductive via V1.

Next, referring to FIG. 1B, the barrier layer 118 may be formed on the first dielectric layer D1 through, for example, a spin coating process, a plating process, a deposition process, a lithographic etching process, or other suitable manufacturing techniques. This is because metal ions (for example, copper ions) having a high diffusion coefficient may be included in the wiring formed later on the transistor 112. If these metal atoms diffuse into the transistor 112, the characteristics of the transistor 112 are easily deteriorated. Therefore, the barrier layer 118 is provided to improve the electrical reliability and the joint strength of the transistor 112. The material of the barrier layer 118 may include silicon nitride (SiNx), silicon oxide (SiOx), or titanium nitride (TiNx), but the embodiment of the present invention is not limited thereto. Other suitable barrier metal ions (such as copper (Ion) barrier materials can also be used in embodiments of the present invention. In some embodiments, the barrier layer 118 may have a plurality of openings 118 a to expose a portion of the first conductive via V1 and the conductive material layer 1126 to facilitate subsequent electrical connection.

Referring to FIG. 1C, after the barrier layer 118 is formed, a second redistribution line C2, a second dielectric layer D2, a second conductive via V2, and a third redistribution line C3 may be alternately formed on the barrier layer 118. , A third dielectric layer D3 and a third conductive via V3. For example, a conductive material may be formed on the barrier layer 118 and the opening 118a (refer to FIG. 1B), and the conductive material may be patterned to form a second redistribution line C2. In some embodiments, a dielectric material may be formed on the barrier layer 118 to cover the second redistribution line C2 and formed by removing a portion of the dielectric material through laser drilling or other suitable fabrication techniques. A plurality of openings, and these openings expose a portion of the second redistribution line C2 to form a second dielectric layer D2. As a result, the barrier layer 118 is sandwiched between the first dielectric layer D1 and the second dielectric layer D2, and is located between the redistribution line C2 and the semiconductor material layer 1122 (see FIG. 1A) of the transistor 112. The transistor 112 is prevented from being affected by the diffusion of ions (such as copper ions) of the redistribution line C2.

Subsequently, a conductive material may be formed in these openings to form a second conductive via V2. Then, a third redistribution line C3 may be formed on the second conductive via V2. In some embodiments, the second conductive via V2 and the third redistribution circuit C3 formed thereon can be fabricated in the same process. For example, a conductive material may be formed in the opening of the second dielectric layer D2 and on the second dielectric layer D2, and the conductive material may be patterned to form a third redistribution line C3 on the second dielectric layer D2. After the third redistribution line C3 is formed, the third dielectric layer D3 and the third conductive via V3 may be formed in a similar manner, and details are not described herein again. It should be understood that the number of layers of redistribution lines and dielectric layers or the number of conductive vias may be determined according to actual design requirements, which may be single or multiple layers. FIG. 1C is merely an example. Not limited to this. In other embodiments, the barrier layer 118 may also be formed between the second dielectric layer D2 and the third dielectric layer D3 according to design requirements. The embodiment of the present invention does not limit the number of the barrier layers 118 provided.

Furthermore, any one of the plurality of dielectric layers (for example, the first dielectric layer D1, the second dielectric layer D2, or the third dielectric layer D3) in the redistribution line structure layer 110 of this embodiment has Thickness Ta. The total thickness Tb of the second dielectric layer D1-2 (refer to FIG. 1A) and the third dielectric layer D1-3 (refer to FIG. 1A) where the transistor 112 is located, and the copper barrier layer 118 has a thickness Tc. In some embodiments, the thickness Ta of any one of the dielectric layers is greater than the total thickness Tb of the second dielectric layer D1-2 (see FIG. 1A) and the third dielectric layer D1-3 where the transistor 112 is located. For example, the thickness Ta of any one of the dielectric layers may be between about 0.1 micrometer (μm) and 20 μm, and the total thickness Tb is between about 500 nanometers (nm) and about 1000 nm. In some embodiments, the total thickness Tb of the second dielectric layer D1-2 (refer to FIG. 1A) and the third dielectric layer D1-3 where the transistor 112 is located is greater than the thickness Tc of the copper barrier layer 118. For example, the thickness Tc of the barrier layer 118 may be between about 5 nm and about 500 nm. The thickness Td of any of the redistribution lines 116 (for example, the first redistribution line C1, the second redistribution line C2, or the third redistribution line C3) may be between approximately 2 μm and 8 μm. In the manufacturing process of the redistribution circuit structure layer 110 in this embodiment, a transistor 112 process that needs to be performed in a relatively high-temperature process environment (for example, between about 300 degrees and 400 degrees) is first made, and then the transistor 112 is fabricated on the transistor 112. The redistribution circuit 116 process is performed in a relatively low temperature process environment (for example, about 200 degrees), so the transistor 112 on the bottom is not damaged.

Next, referring to FIG. 1D and FIG. 1E, a protective film layer 20 is formed on the redistribution circuit structure layer 110. For example, the redistribution line structure layer 110 has a first side S1 and a second side S2 opposite to each other. The first side S1 can contact the first carrier board 10, and the transistor 112 and the first conductive via V1 are formed on and located on the first side S1. The protective film layer 20 may be disposed on the second side S2 so that the redistribution circuit structure layer 110 is located between the first carrier board 10 and the protective film layer 20. For example, the protective film layer 20 may be sufficiently rigid to provide support in subsequent processes. In some embodiments, the protective film layer 20 may include a release film, so that the second side S2 of the self-weight distribution circuit structure layer 110 is peeled off later. After the protective film layer 20 is formed, a peeling process and a transfer process can be performed. In some embodiments, a stripping process may be performed first to peel off the first side S1 of the first carrier board 10 from the redistribution circuit structure layer 110 to expose the surface of the first dielectric layer D1, and then, perform a transfer board. In the manufacturing process, the redistribution line structure layer 110 is turned up and down 180 degrees, so that the first side S1 of the redistribution line structure layer 110 faces upward, which facilitates subsequent processes on the first dielectric layer D1. In other embodiments, the transfer process may be performed first and then the peeling process is performed, but the embodiments of the present invention are not limited thereto.

Referring to FIG. 1F, after the stripping process is performed, at least one wafer 120 may be disposed on the first side S1 of the redistribution circuit structure layer 110 to be close to the transistor 112. For example, the active surface 120a of the wafer 120 may be provided with a plurality of pads 122, and the pads 122 of the wafer 120 and the first conductive vias V1 and / or around the transistor 112 may be flipped. The first redistribution line C1 is electrically connected to shorten the distance of electrical conduction between the chip 120 and the transistor 112. In some embodiments, after the stripping process is completed, at this time, the first dielectric layer D1 (such as the first dielectric layer D1-1 shown in FIG. 1A) covers the first conductive via V1 and the first redistribution line C1. A plurality of openings can be formed on the first side S1 of the redistribution circuit structure layer 110, that is, on the first dielectric layer D1, by laser perforation or other suitable manufacturing techniques to expose the first conductive via V1 and / Or the first redistribution circuit C1, and subsequently, a metal with higher conductivity (such as tin) can be filled in these openings, and then electrically connected to the wafer 120, thereby reducing the wafer 120 and the redistribution circuit structure layer 110. The impedance. In other embodiments, the chip 120 may also be electrically connected to the redistribution circuit structure layer 110 by using a solder ball or other suitable methods. The manufacturing technology of the embodiment of the present invention is not limited thereto.

After the wafer 120 is disposed, an encapsulant 130 may be formed on the first side S1 of the redistribution circuit structure layer 110. For example, the molding compound 130 may be formed on the first side S1 of the redistribution circuit structure layer 110 with a molding material (such as epoxy resin) or other suitable dielectric material through a molding process, so that at least The wafer 120 is covered to isolate the wafer 120 from the external environment. However, the material and manufacturing technology of the encapsulant 130 in the embodiment of the present invention are not limited thereto.

Referring to FIG. 1G and FIG. 1H, after forming the encapsulant 130, the protective film layer 20 can be selectively peeled from the second side S2 of the redistribution wiring structure layer 110 to expose the surface of the third dielectric layer D3. Subsequently, the carrier board 140 is disposed on the second side S2 of the redistribution circuit structure layer 110, wherein the carrier board 140 is electrically connected to the chip 120 through the conductive vias 114 of the redistribution circuit structure layer 110. In some embodiments, the carrier board 140 may be a printed circuit board, a semiconductor integrated circuit carrier board, or a substrate of a semiconductor process wafer, but embodiments of the present invention are not limited thereto. For example, the carrier board 140 may have a plurality of pads 142. The pads 142 of the carrier board 140 may be combined with the third conductive vias V3 of the redistribution circuit layer 110 to allow the chip 120 to pass through the redistribution circuit structure layer. 110 is electrically connected to the carrier board 140. So far, the manufacturing process of the chip package structure 100A has been completed. For example, the chip package structure 100A can be performed in a panel-level package (PLP) process, that is, after the packaging step is completed at the panel stage, the chip package structure 100A can be cut. In other embodiments, it may also be performed in a wafer level packaging (WLP) process, and the present invention is not limited thereto.

FIG. 2 is a schematic cross-sectional view of a chip package structure according to a second embodiment of the present invention. The chip package structure 100B of this embodiment is similar to the chip package structure 100A of FIG. 1H. Therefore, the same or similar reference numerals indicate the same or similar components, so the components described in FIG. 1A to FIG. 1H will not be repeated here. . Please refer to FIG. 2, the chip package structure 100B includes chips 120-A and 120-B disposed on the redistribution circuit structure layer 110-B, and the wafers 120-A and 120-B can pass through the redistribution circuit structure layer 110-B. They are electrically connected to each other. In some embodiments, the wafers 120-A and 120-B may be wafers having the same function. In other embodiments, the chips 120-A and 120-B may have different functions. For example, the chips 120-A and 120-B include a logic chip, a memory chip, an input / output chip, etc., but the embodiment of the present invention is not limited thereto. It should be understood that although two wafers are shown in FIG. 2, in other embodiments, the number of wafers in the chip packaging structure may be configured with more than two wafers according to design requirements, and embodiments of the present invention are not limited. The number of wafers.

In this embodiment, the transistor located in the first dielectric layer D1 may be a thin film transistor (labeled ESD in FIG. 2) having an electrostatic discharge protection function. For example, at least two ESD protection transistors ESD may be provided to re-distribute the wiring structure layer 110-B to be electrically connected to the wafers 120-A and 120-B, respectively. In some embodiments, the first conductive via V1 disposed around the ESD protection transistor ESD and the conductive material layer 1126 (see FIG. 1A) disposed on the ESD protection transistor ESD may pass through the redistribution circuit 116 and be located at The conductive vias 114 in other layers electrically connect the ESD protection transistor ESD to the wafers 120-A and 120-B. At least a part of these conductive vias 114 (including the first conductive via V1 or the conductive material layer 1126 of the electrostatic discharge protection transistor ESD and the conductive vias in other layers) and at least a part of the redistribution circuit 116 may A voltage source line Vdd and a ground line Vss are formed. In some embodiments, the chips 120-A and 120-B electrically connected to each other may share the voltage source line Vdd and the ground line Vss.

In some embodiments, at least one end of the chips 120-A, 120-B may be provided with an input / output (I / O) pin PIN. Generally, electrostatic discharge may enter the chip through the pin PIN. In the embodiment of the present invention, the electrostatic discharge protection transistor ESD is formed in the process of forming the redistribution circuit structure layer 110-B, which can prevent the electrostatic discharge from damaging the functional circuits of the wafers 120-A and 120-B. In addition, compared with the conventional method of providing an electrostatic discharge protection element, the arrangement of the embodiment of the present invention can greatly reduce the area occupied by the electrostatic discharge protection transistor in the chip packaging structure, and there is no need to provide an intermediary including an electrostatic discharge protection element. Plate, thereby saving manufacturing costs. For example, in this embodiment, the ESD protection transistor ESD may be disposed on a side close to the wafers 120-A and 120-B to release the electrostatic discharge current nearby. In some embodiments, the ESD protection transistor ESD includes a first end E1 and a second end E2 connected to the ESD protection transistor. In some embodiments, the ESD protection transistor ESD further includes a third terminal E1 electrically connected to the pins PIN of the chips 120-A and 120-B. It should be understood that although in FIG. 2, the first end E1, the second end E2, and the third end E3 are sequentially arranged on the same side from left to right, in other embodiments, it may also be based on design requirements. There are different sequence configurations or on different sides of the ESD protection transistor ESD. For example, the first terminal E1 of the ESD protection transistor ESD can be electrically connected to the voltage source line Vdd, and the second terminal E2 of the ESD protection transistor ESD can be electrically connected to the ground line Vss, thereby the The wave current is introduced into the voltage source line Vdd and the ground line Vss to avoid damaging the chips 120-A and 120-B.

3 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention. The chip package structure 100C of this embodiment is similar to the chip package structure 100A of FIG. 1H and the chip package structure 100B of FIG. 2. Therefore, the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Referring to FIG. 3, in the redistribution circuit structure layer 110-C of the chip package structure 100C, the ESD protection transistor ESD is, for example, disposed on the second dielectric layer D2, and on opposite sides of the second dielectric layer D2 Barrier layers 118-A and 118-B can be configured separately to prevent ESD protection transistor ESD and redistribution on other dielectric layers (such as first dielectric layer D1 and / or third dielectric layer D3) Line 116.

For example, a barrier layer 118-A can be formed on the first carrier board first, and then a transistor process is performed on the barrier layer 118-A to form an ESD protection transistor ESD and a second dielectric layer D2. And redistribution lines and conductive vias in the second dielectric layer D2. Next, a barrier layer 118-B is formed, and then a third dielectric layer D3 and redistribution lines and conductive vias in the third dielectric layer D3 are formed on the second dielectric layer D2. on. Subsequently, the first dielectric layer is formed on the other side of the second dielectric layer D2 relative to the third dielectric layer D3 after laminating the protective film layer, removing the first carrier plate, and performing the transfer process. D1 and redistribution lines and conductive vias in the first dielectric layer D1. After that, the wafer 120 is disposed on the first dielectric layer D1. Then, the protective film layer is removed to bond the carrier 150 to the third dielectric layer D3.

In this embodiment, the third terminal E3, the first terminal E1, and the second terminal E2 of the ESD protection transistor ESD of FIG. 3 are illustrated as being arranged from left to right in order to be electrically connected to the chip 120 Pin PIN, voltage source line Vdd and ground line Vss. In other embodiments, the chip package structure 100C may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and the chips are electrically connected to each other through the redistribution circuit structure layer 110-C.

4 is a schematic cross-sectional view of a chip package structure according to a fourth embodiment of the present invention. Referring to FIG. 4, the redistribution circuit structure layer 110 -D of the chip package structure 100D of this embodiment may be disposed on the carrier board 150, and an ESD protection transistor ESD is disposed in the third dielectric layer D3. For example, a transistor process may be performed on the first carrier to form an ESD protection transistor ESD, a third dielectric layer D3, and redistribution lines and conductive vias in the third dielectric layer D3. Next, a barrier layer 118 is formed on the third dielectric layer D3. Secondly, a second dielectric layer D2 is formed on the barrier layer 118 and the redistribution lines and conductive vias are formed therein, and then a first dielectric layer D1 and the redistribution line is formed on the second dielectric layer D2. With conductive vias. Subsequently, the first carrier board is removed, and the wafer 120 and the carrier board 150 are respectively disposed on the first dielectric layer D1 and the third dielectric layer D3. That is, compared with the method described in FIG. 1A to FIG. 1H, the wafer packaging structure 100D of this embodiment is formed, and after the redistribution circuit structure layer 110 -D is formed, the transfer board process is not required. Therefore, in this embodiment, the ESD protection transistor ESD is located on the first side S1 of the redistribution circuit structure layer 110-D and connected to the carrier board 150, and away from the second side S2 where the wafer 120 is located. For example, the carrier board 150 includes a glass substrate, a ceramic substrate, or other suitable carrier boards, and the carrier board 150 may have no wiring. In some embodiments, the chip package structure 100D may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and the chips are electrically connected to each other through the redistribution circuit structure layer 110-D. In other embodiments, the carrier board 150 may also be similar to the carrier board of FIG. 1H, and the pads on the carrier board are directly and electrically connected to the redistribution circuit structure layer 110-D, which will not be repeated here.

FIG. 5 is a schematic cross-sectional view of a chip package structure according to a fifth embodiment of the present invention. The chip package structure 100E of this embodiment is similar to the chip package structure 100D of FIG. 4. Therefore, the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Please refer to FIG. 5. The difference between the chip package structure 100E of this embodiment and the chip package structure 100D of FIG. 4 is, for example, that the ESD protection transistor ESD of this embodiment is disposed on the second dielectric layer D2, and therefore redistributed. The circuit structure layer 110-E includes at least two barrier layers 118-A and 118-B respectively disposed on opposite sides of the second dielectric layer D2 where the ESD protection transistor ESD is located. The method for forming the chip package structure 100E in this embodiment may be similar to the method for forming the chip package structure 100C in FIG. 3, and details are not described herein again. In other embodiments, the chip package structure 100E may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and the chips are electrically connected to each other through the redistribution circuit structure layer 110-E.

FIG. 6 is a schematic cross-sectional view of a chip package structure according to a sixth embodiment of the present invention. The chip package structure 100F of this embodiment is similar to the chip package structure 100A of FIG. 1H. Therefore, the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Please refer to FIG. 6. In the redistribution circuit structure layer 110-F of the chip package structure 100F, the transistor located in the first dielectric layer D1 may be a thin film transistor with a switch control function (labeled as SWT in FIG. 6). ). The switch control transistor SWT can be electrically connected to the chip 120-C through the redistribution circuit 116 and / or the conductive via 114, so that the input signal of the chip 120-C can be adjusted and selected. For example, the chip 120-C may include a voltage source terminal F1 connected to the voltage source line Vdd in the redistribution line structure layer 110-F, a ground terminal F2 connected to the ground line Vss in the redistribution line structure layer 110-F, and Connected to the pin terminal F3 of the third terminal E3 of the switch control transistor SWT. In some embodiments, the switch control transistor SWT may be electrically connected to the pin terminal F3 of the chip 120-C through the redistribution circuit 116 located in the first dielectric layer D1. In other embodiments, the chip package structure 100F may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and these chips are electrically connected to each other through the redistribution circuit structure layer 110-F. The chip may share the voltage source line Vdd and the ground line Vss, for example.

FIG. 7 is a schematic cross-sectional view of a chip package structure according to a seventh embodiment of the present invention. The chip package structure 100G of this embodiment is similar to the chip package structure 100F of FIG. 6, and therefore the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Referring to FIG. 7, the chip 120-D may include a plurality of pin terminals F3, and any one of the pin terminals F3 may be electrically connected to the switch control transistor SWT. In the redistribution circuit structure layer 110-G of the chip package structure 100G of this embodiment, the switch control transistor SWT is formed in, for example, the second dielectric layer D2, and the opposite sides of the second dielectric layer D2 may be The barrier layers 118-A and 118-B are respectively configured to block the switch control transistor SWT and the redistribution lines 116 located in other dielectric layers (such as the first dielectric layer D1 and / or the third dielectric layer D3). . In other embodiments, the chip package structure 100G may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and these chips are electrically connected to each other through the redistribution circuit structure layer 110-G. The chip may share the voltage source line Vdd and the ground line Vss, for example.

FIG. 8 is a schematic cross-sectional view of a chip package structure according to an eighth embodiment of the present invention. The chip package structure 100H of this embodiment is similar to the chip package structure 100G of FIG. 7, and therefore the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Referring to FIG. 8, the redistribution circuit structure layer 110 -H of the chip packaging structure 100H of this embodiment may be similar to the chip packaging structure 100D of FIG. 4, and the redistribution circuit structure layer 110 -H is formed on the carrier board 150. That is, the redistribution circuit structure layer 110-H can be formed on the carrier board 150 according to the method described in FIG. 1A to FIG. 120-D is disposed on the redistribution line structure layer 110-H. Therefore, in this embodiment, the position of the switch-control transistor SWT in the second dielectric layer D2 is close to the side of the carrier 150, and in the embodiment shown in FIG. 7, the switch-control transistor SWT is located in the first dielectric layer D2. The position in the second dielectric layer D2 is near the side of the wafer 120-D. In other embodiments, the chip package structure 100H may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and these chips are electrically connected to each other through the redistribution circuit structure layer 110-H. The chip may share the voltage source line Vdd and the ground line Vss, for example.

FIG. 9 is a schematic cross-sectional view of a chip package structure according to a ninth embodiment of the present invention. The chip package structure 100I of this embodiment is similar to the chip package structure 100H of FIG. 8. Therefore, the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Referring to FIG. 9, the switch control transistor SWT in the chip package structure 100I is located on the first side S1 of the redistribution circuit structure layer 110 -I to the connection substrate 150 and is far from the second side S2 where the chip 120 -D is located. The difference between the chip package structure 100I of this embodiment and the chip package structure 100H of FIG. 8 further includes that the chip package structure 100I of this embodiment is provided with a single barrier layer 118.

FIG. 10 is a schematic cross-sectional view of a chip package structure according to a tenth embodiment of the present invention. Referring to FIG. 10, the chip package structure 100J of this embodiment includes a plurality of transistors with different functions, such as an electrostatic discharge protection transistor ESD and a switch control transistor SWT. The configuration of the chip package structure 100J of this embodiment is similar to the chip package structure 100F of FIG. 6 in combination with the chip package structure 100A of FIG. 1H. The ESD protection transistor ESD and the switch control transistor SWT can be arranged close to the chip 120-E at the same time. In the dielectric layer on the side, details are not repeated here. The chip package structure 100J can prevent the damage caused by the inrush of a large amount of static discharge current through the electrostatic discharge protection transistor ESD without increasing the structure size and process complexity. At the same time, the switch can be used to control the transistor SWT to the chip. 120-E adjusts and selects the input signal. In other embodiments, the chip package structure 100J may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and these chips are electrically connected to each other through the redistribution circuit structure layer 110-J. The chip may share the voltage source line Vdd and the ground line Vss, for example.

11 is a schematic cross-sectional view of a chip package structure according to an eleventh embodiment of the present invention. The chip package structure 100K of this embodiment is similar to the chip package structure 100J of FIG. 10, and therefore the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Please refer to FIG. 11. The configuration of the chip package structure 100K is similar to that of the chip package structure 100C of FIG. 3 combined with the chip package structure 100G of FIG. In D2, the barrier layers 118-A and 118-B may be respectively disposed on opposite sides of the second dielectric layer D2, and details are not described herein again. In other embodiments, the chip package structure 100K may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and these chips are electrically connected to each other through the redistribution circuit structure layer 110-K. The chip may share the voltage source line Vdd and the ground line Vss, for example.

FIG. 12 is a schematic cross-sectional view of a chip package structure according to a twelfth embodiment of the present invention. Referring to FIG. 12, the chip package structure 100L of this embodiment is similar to the chip package structure 100K of FIG. 11, and therefore the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Please refer to FIG. 12. The configuration of the chip package structure 100L is similar to that of the chip package structure 100E of FIG. 5 and the chip package structure 100H of FIG. 8. The ESD protection transistor ESD and the switch control transistor SWT can be configured on the second dielectric layer at the same time. The side of D2 near the carrier plate 150 will not be described in detail here. In other embodiments, the chip package structure 100L may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and these chips are electrically connected to each other through the redistribution circuit structure layer 110-L. The chip may share the voltage source line Vdd and the ground line Vss, for example.

13 is a schematic cross-sectional view of a chip package structure according to a thirteenth embodiment of the present invention. Referring to FIG. 13, the chip package structure 100M of this embodiment is similar to the chip package structure 100L of FIG. 12, and therefore the same or similar reference numerals indicate the same or similar components, and details are not described herein again. Please refer to FIG. 13. The configuration of the chip package structure 100M is similar to that of the chip package structure 100D of FIG. 4 and the chip package structure 100I of FIG. 9. The ESD protection transistor ESD and the switch control transistor SWT can be configured at the same time as being connected to the carrier board 150. The first side S1, details are not repeated here. In other embodiments, the chip package structure 100M may also be configured similar to the chip package structure of FIG. 2 including a plurality of chips, and these chips are electrically connected to each other through the redistribution circuit structure layer 110-M. The chip may share the voltage source line Vdd and the ground line Vss, for example.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧ the first carrier board

20‧‧‧ protective film

100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M‧‧‧ chip package structure

110, 110-B, 110-C, 110-D, 110-E, 110-F, 110-G, 110-H, 110-I, 110-J, 110-K, 110-L, 110-M‧ ‧‧Redistribution line structure layer

112‧‧‧Transistor

1122‧‧‧Semiconductor material layer

1124‧‧‧Metal material layer

1126‧‧‧Conductive material layer

114‧‧‧ conductive via

116‧‧‧ Redistribution Line

118, 118-A, 118-B‧‧‧ barrier layer

118a‧‧‧ opening

120, 120-A, 120-B, 120-C, 120-D, 120-E‧‧‧

120a‧‧‧active surface

122‧‧‧ pad

130‧‧‧ encapsulated colloid

140, 150‧‧‧ carrier board

142‧‧‧pad

C1‧‧‧First Redistribution Route

C2‧‧‧Second Redistribution Line

C3‧‧‧ Third Redistribution Line

D1‧‧‧First dielectric layer

D1-1‧‧‧First dielectric layer

D1-2‧‧‧Second dielectric layer

D1-3‧‧‧Third dielectric layer

D2‧‧‧Second dielectric layer

D3‧‧‧Third dielectric layer

ESD‧‧‧ Electrostatic discharge protection transistor

E1‧‧‧First end

E2‧‧‧Second End

E3‧‧‧ third end

F1‧‧‧Voltage source terminal

F2‧‧‧ Ground

F3‧‧‧pin

PIN‧‧‧pin

S1‧‧‧First side

S2‧‧‧Second side

SWT‧‧‧Switch control transistor

Ta, Tc, Td‧‧‧thickness

Tb‧‧‧ thickness total

V1‧‧‧First conductive via

V2‧‧‧Second conductive via

V3‧‧‧Third conductive via

Vdd‧‧‧ voltage source line

Vss‧‧‧ ground line

1A to 1H are schematic cross-sectional views of a method for manufacturing a chip package structure according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a chip package structure according to a second embodiment of the present invention. 3 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention. 4 is a schematic cross-sectional view of a chip package structure according to a fourth embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a chip package structure according to a fifth embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a chip package structure according to a sixth embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a chip package structure according to a seventh embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a chip package structure according to an eighth embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a chip package structure according to a ninth embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of a chip package structure according to a tenth embodiment of the present invention. 11 is a schematic cross-sectional view of a chip package structure according to an eleventh embodiment of the present invention. FIG. 12 is a schematic cross-sectional view of a chip package structure according to a twelfth embodiment of the present invention. 13 is a schematic cross-sectional view of a chip package structure according to a thirteenth embodiment of the present invention.

Claims (20)

A chip packaging structure includes: a redistribution line structure layer including: at least one redistribution line; at least one transistor electrically connected to the at least one redistribution line; and a plurality of conductive vias electrically connected to the at least one redistribution A circuit and the at least one transistor; at least one wafer is disposed on the redistribution circuit structure layer and is electrically connected to the redistribution circuit structure layer; and a packaging gel is disposed on the redistribution circuit structure layer And at least cover the at least one wafer. The chip package structure according to item 1 of the scope of patent application, wherein the redistribution circuit structure layer further includes a plurality of dielectric layers, and one of the plurality of dielectric layers includes a first dielectric electron layer sequentially stacked. , A second dielectric layer, and a third dielectric layer, and the at least one transistor is located in the plurality of dielectric layers, and the at least one transistor includes: a semiconductor material layer located in the second dielectric Layer; a metal material layer located in the third dielectric layer; and a conductive material layer connected to the semiconductor material layer through the third dielectric layer and the second dielectric layer, and the A layer of conductive material surrounds the layer of metallic material. The chip package structure according to item 2 of the patent application scope, wherein the semiconductor material layer includes a polycrystalline silicon semiconductor layer, a metal oxide semiconductor layer, or an amorphous silicon semiconductor layer. The chip package structure according to item 2 of the scope of patent application, wherein the redistribution circuit structure layer further comprises: at least one barrier layer, the semiconductor disposed on the at least one redistribution circuit and the at least one transistor. Between layers of material. The chip package structure according to item 4 of the scope of patent application, wherein a thickness of any one of the plurality of dielectric layers is greater than a thickness of the second dielectric layer plus a thickness of the third dielectric layer And the sum of the thickness of the second dielectric layer and the thickness of the third dielectric layer is greater than the thickness of the at least one barrier layer. The chip package structure according to item 5 of the scope of patent application, wherein the thickness of the at least one barrier layer is between 5 nm and 500 nm. The chip package structure according to item 5 of the patent application scope, wherein the thickness of any one of the plurality of dielectric layers is between 0.1 μm and 20 μm. The chip package structure according to item 4 of the scope of patent application, wherein the material of the at least one barrier layer includes silicon nitride, silicon oxide, or titanium nitride. The chip package structure according to item 1 of the patent application scope, wherein the at least one transistor has a first end and a second end, the at least one redistribution line includes a voltage source line and a ground line, and the at least one transistor The first terminal of is electrically connected to the voltage source line, and the second terminal of the at least one transistor is electrically connected to the ground line. The chip package structure according to item 1 of the scope of patent application, further comprising: a carrier board, the at least one wafer and the carrier board are respectively located on opposite sides of the redistribution circuit structure layer, wherein the carrier board passes through The plurality of conductive vias of the redistribution circuit structure layer are electrically connected to the at least one chip. The chip package structure according to item 1 of the patent application scope, wherein the thickness of the at least one redistribution line is between 2 micrometers and 8 micrometers. The chip package structure according to item 1 of the patent application scope, wherein the at least one transistor comprises an electrostatic discharge protection transistor or a switch control transistor. A method for manufacturing a chip package structure includes: forming a redistribution line structure layer, wherein the redistribution line structure layer has a first side and a second side opposite to each other, and forming the redistribution line structure layer includes: forming at least one A transistor and a plurality of conductive vias on the first side; and forming at least one redistribution line to electrically connect the at least one transistor, wherein the conductive vias electrically connect the at least one redistribution line and the At least one transistor; setting at least one wafer on the second side of the redistribution circuit structure layer, wherein the at least one wafer is electrically connected to the redistribution circuit structure layer; and forming a packaging gel on the redistribution circuit structure layer; The circuit structure layer is redistributed to cover at least the at least one wafer. The method for manufacturing a chip package structure according to item 13 of the scope of patent application, further comprising: forming the redistribution circuit structure layer on a first carrier board, wherein the first side of the redistribution circuit structure layer Contacting the first carrier board; and inverting the redistribution circuit structure layer, and before disposing the at least one wafer, removing the first carrier board to expose the first redistribution circuit structure layer. One side. The method for manufacturing a chip package structure according to item 14 of the scope of patent application, further comprising: after forming the redistribution circuit structure layer, providing a protective film layer on the second side of the redistribution circuit structure layer. So that the redistribution circuit structure layer is located between the first carrier board and the protective film layer; and after forming the encapsulation gel on the redistribution circuit structure layer, removing the protective film Layer to expose the second side of the redistribution line structure layer. The method for manufacturing a chip package structure according to item 15 of the scope of patent application, further comprising: after removing the protective film layer, setting a carrier board on the second side of the redistribution circuit structure layer, wherein The carrier board is electrically connected to the at least one chip through the plurality of conductive vias of the redistribution circuit structure layer. The method of manufacturing a chip package structure according to item 13 of the scope of the patent application, wherein the redistribution circuit structure layer further includes a plurality of dielectric layers, and one of the plurality of dielectric layers includes a first stacked in order. Forming a dielectric material layer, a second dielectric material layer, and a third dielectric material layer, forming the at least one transistor includes: forming a semiconductor material layer on the first dielectric material layer; forming the metal material layer on the second dielectric material layer; A dielectric material layer; and forming the conductive material layer to connect to the semiconductor material layer through the third dielectric material layer and the second dielectric material layer, wherein the conductive material layer surrounds the metal material layer . The method for manufacturing a chip package structure according to item 17 of the application, wherein forming the redistribution circuit structure layer further includes: forming at least one barrier layer in the plurality of dielectric layers, wherein the at least one The barrier layer is located between at least one redistribution line and the semiconductor material layer of the at least one transistor. The method for manufacturing a chip package structure according to item 18 of the scope of patent application, wherein the thickness of any one of the plurality of dielectric layers is greater than the thickness of the second dielectric layer plus the thickness of the third dielectric layer. The sum of the thicknesses, and the sum of the thickness of the second dielectric layer and the thickness of the third dielectric layer is greater than the thickness of the at least one barrier layer. The method for manufacturing a chip package structure according to item 13 of the scope of the patent application, wherein the at least one transistor includes an electrostatic discharge protection transistor or a switch control transistor.