TW201935575A - 用於屏蔽系統級封裝組件免受電磁干擾的方法 - Google Patents

用於屏蔽系統級封裝組件免受電磁干擾的方法 Download PDF

Info

Publication number
TW201935575A
TW201935575A TW108103843A TW108103843A TW201935575A TW 201935575 A TW201935575 A TW 201935575A TW 108103843 A TW108103843 A TW 108103843A TW 108103843 A TW108103843 A TW 108103843A TW 201935575 A TW201935575 A TW 201935575A
Authority
TW
Taiwan
Prior art keywords
component
substrate
trench
coating
package component
Prior art date
Application number
TW108103843A
Other languages
English (en)
Other versions
TWI787448B (zh
Inventor
洪萱
丹尼爾 瑪仕立克
卓綺茁
茱麗葉 葛蕾絲 珊雀斯
Original Assignee
德商漢高智慧財產控股公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 德商漢高智慧財產控股公司 filed Critical 德商漢高智慧財產控股公司
Publication of TW201935575A publication Critical patent/TW201935575A/zh
Application granted granted Critical
Publication of TWI787448B publication Critical patent/TWI787448B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0073—Shielding materials
    • H05K9/0081—Electromagnetic shielding materials, e.g. EMI, RFI shielding
    • H05K9/0084—Electromagnetic shielding materials, e.g. EMI, RFI shielding comprising a single continuous metallic layer on an electrically insulating supporting structure, e.g. metal foil, film, plating coating, electro-deposition, vapour-deposition
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B27/08—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B27/10—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material of paper or cardboard
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/12—Layered products comprising a layer of synthetic resin next to a fibrous or filamentary layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/32—Layered products comprising a layer of synthetic resin comprising polyolefins
    • B32B27/322—Layered products comprising a layer of synthetic resin comprising polyolefins comprising halogenated polyolefins, e.g. PTFE
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/38—Layered products comprising a layer of synthetic resin comprising epoxy resins
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B29/00—Layered products comprising a layer of paper or cardboard
    • B32B29/002—Layered products comprising a layer of paper or cardboard as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B29/005—Layered products comprising a layer of paper or cardboard as the main or only constituent of a layer, which is next to another layer of the same or of a different material next to another layer of paper or cardboard layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B29/00—Layered products comprising a layer of paper or cardboard
    • B32B29/02—Layered products comprising a layer of paper or cardboard next to a fibrous or filamentary layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B5/00—Layered products characterised by the non- homogeneity or physical structure, i.e. comprising a fibrous, filamentary, particulate or foam layer; Layered products characterised by having a layer differing constitutionally or physically in different parts
    • B32B5/02—Layered products characterised by the non- homogeneity or physical structure, i.e. comprising a fibrous, filamentary, particulate or foam layer; Layered products characterised by having a layer differing constitutionally or physically in different parts characterised by structural features of a fibrous or filamentary layer
    • B32B5/024—Woven fabric
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B5/00—Layered products characterised by the non- homogeneity or physical structure, i.e. comprising a fibrous, filamentary, particulate or foam layer; Layered products characterised by having a layer differing constitutionally or physically in different parts
    • B32B5/22—Layered products characterised by the non- homogeneity or physical structure, i.e. comprising a fibrous, filamentary, particulate or foam layer; Layered products characterised by having a layer differing constitutionally or physically in different parts characterised by the presence of two or more layers which are next to each other and are fibrous, filamentary, formed of particles or foamed
    • B32B5/24—Layered products characterised by the non- homogeneity or physical structure, i.e. comprising a fibrous, filamentary, particulate or foam layer; Layered products characterised by having a layer differing constitutionally or physically in different parts characterised by the presence of two or more layers which are next to each other and are fibrous, filamentary, formed of particles or foamed one layer being a fibrous or filamentary layer
    • B32B5/26—Layered products characterised by the non- homogeneity or physical structure, i.e. comprising a fibrous, filamentary, particulate or foam layer; Layered products characterised by having a layer differing constitutionally or physically in different parts characterised by the presence of two or more layers which are next to each other and are fibrous, filamentary, formed of particles or foamed one layer being a fibrous or filamentary layer another layer next to it also being fibrous or filamentary
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/345—Arrangements for heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
    • H05K9/0031—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields combining different shielding materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/204—Di-electric
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/206—Insulating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/212—Electromagnetic interference shielding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/08—PCBs, i.e. printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Textile Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Near-Field Transmission Systems (AREA)

Abstract

本發明提供一種用於屏蔽系統級封裝(SIP)組件免受電磁干擾(EMI)的方法，其包含在單個層壓製程中將預形成EMI屏蔽膜層壓在該組件上。該EMI屏蔽膜可係可在真空層壓製程中模製以覆蓋該SIP組件且大致上填充形成於該組件中毗鄰部件模組之間之溝槽。因此，透過單個EMI屏蔽膜之該施加，該SIP組件經屏蔽而免受EMI。

Description

用於屏蔽系統級封裝組件免受電磁干擾的方法
本發明大體上係關於電子封裝之電磁干擾(EMI)屏蔽，且更特定而言係關於一種EMI屏蔽膜及一種用於將EMI屏蔽膜施加至經分段系統級封裝(SIP)電子封裝的方法。
持續需要具有經增加功能性及經減少大小之電子裝置，且特定而言需要諸如智慧電話及平板電腦之行動計算裝置。然而，此等裝置通常包含需要電磁屏蔽之電路。舉例而言，某些裝置包含易受射頻干擾之射頻收發器電路。時脈信號係射頻干擾源之另一實例。針對本發明之目的，術語「電磁干擾」(EMI)意欲包含寬頻波形信號，包含自電子裝置中之部件或自其它源發出之射頻(RF)信號及其他頻率信號。
電磁屏蔽通常用於減少對電子裝置內之部件之操作之EMI。當前，可藉由電路之間之金屬屏蔽罩或導電膏來形成EMI屏蔽。屏蔽罩或導電膏之導電態樣起作用以減輕電磁信號傳輸以便最小化對電子部件操作之電磁干擾。然而，習用EMI屏蔽解決方案限制了封裝大小之減少，且因此限制了電子裝置設計者回應於使用者偏好而減少外觀尺寸大小之能力。
EMI屏蔽之特別有益施加係介於系統級封裝(SIP)中之經分段部件或部件群組之間。出於各種緣由，可在SIP中分段部件或部件群組，其中SIP之經分段部分執行系統之特定功能，且因此可放置於基板上作為預定義功能「模組」。SIP之經分段部分通常藉由在介電外模製中形成之間隙或溝槽實體分離。SIP之經分段部分可經合意地屏蔽而免受由SIP之不同部分產生之EMI。因此，通常在每一經分段部分周圍且遍及SIP(包含在分段溝槽內)提供EMI屏蔽。
通過努力減小總系統大小，設計者一直尋求減小溝槽寬度。然而，在典型溝槽寬度現在在10 μm至100 μm之範圍中之情形下，用EMI屏蔽材料覆蓋溝槽之表面可係困難的。習用EMI屏蔽方法已藉助在經外模製介電材料之外表面周圍之導電膏之印刷及金屬之濺射、電鍍或旋塗之組合而在溝槽中及經外模製介電質之外表面周圍塗佈EMI材料。實例習用製程包含將可固化液態填充材料噴射印刷至溝槽中，後續接著固化材料及清潔經外模製介電質之外表面，以然後在經外模製介電質之外表面周圍接收經沈積金屬層作為保形塗層。此方法歸因於形成EMI屏蔽之兩處理步驟而係複雜且昂貴的，且由於緩慢的噴射填充製程及金屬沈積製程而係耗時的。
另一習用方法包含將液態膏材料印刷至溝槽中及介電層之外表面周圍。然而，申請人發現，難以沿著溝槽之表面均勻地施加EMI屏蔽膏，尤其對於極高寬深比(高深度，低寬度)溝槽設計而言。因此，難以避免溝槽中未充分屏蔽之區域。
因此，本發明之目標係提供一種EMI屏蔽施加製程，其消除習用方法之步驟以加速輸送量且減少與用於金屬汽相沈積之經控制環境相關聯之成本。
因此，本發明之目標亦係提供一種EMI屏蔽施加製程，其促進SIP之表面上(包含在分段SIP之部分之高寬深比溝槽內)EMI屏蔽材料之高品質及徹底塗佈。
藉助本發明，可在單個層壓製程中將EMI屏蔽膜施加至系統級封裝(SIP)組件。適合於EMI屏蔽之導電膜係抵靠著絕緣層真空層壓，且大致上填充形成至該絕緣層中之溝槽以既在該封裝上亦在該封裝之經分段部分之間形成連續EMI屏蔽。該SIP組件包含：基板；安裝在該基板上之複數個部件模組，其中每一部件模組包含一或多個部件；覆蓋該基板上之該等部件之絕緣體；及形成於該絕緣體中毗鄰部件模組之間之溝槽。該溝槽具有介於10 μm至100 μm之間之最大寬度。
在某些實施例中，提供一種在介於20°C與250°C之間之操作溫度下具有小於1 GPa之拉伸模數之自支撐屏蔽預型件。該自支撐預型件可加熱至可流動狀態，且抵靠著該絕緣體之外表面真空層壓且層壓至該溝槽中以形成可大致上填充該溝槽且覆蓋該絕緣體之該外表面之塗層。該塗層可接著固化至至少50 MPa之拉伸模數。
在某些實施例中，一種用於形成SIP組件之方法包含：提供基板及導電跡線，該基板具有導電接地平面，其與該基板之主動表面隔開，且該導電跡線自該接地平面延伸至該主動表面。在該基板之該主動表面上安裝複數個部件模組以形成該基板之經組裝表面，其中每一部件模組包含一或多個部件。然後可將該等經安裝部件模組囊封於在該經組裝表面與外表面之間延伸之絕緣層中。在毗鄰部件模組之間且穿過該介電層至該跡線形成溝槽，其中該溝槽具有介於10 μm至100 μm之間之最大寬度。然後，抵靠著該介電層之該外表面真空層壓自支撐預型件屏蔽膜且層壓至該溝槽中以形成大致上填充該溝槽且覆蓋該介電層之該外表面之塗層。該自支撐預型件屏蔽膜在介於20°C與250°C之操作溫度下展現小於1 GPa之拉伸模數。該屏蔽膜亦可展現小於0.1 Ω * cm之體積電阻率。
可用至少50 psi之力抵靠著該介電層之該外表面加壓該塗層及/或加壓至該(等)溝槽中。可在該塗層所需之任何固化步驟之前、同時或之後執行該加壓。若必要，則可將該塗層固化至至少50 MPa之拉伸模數。
可藉由切穿該基板及該介電層而自該組件單粒化複數個SIP裝置。此等經單粒化SIP裝置中之一或多者可安裝在載體上以供在諸如行動裝置之電子裝置中使用。該SIP裝置中之一或多個部件可包含至少一處理器，且該SIP裝置包含劃界至少兩個部件模組之該等溝槽中之至少一者。大致上填充該溝槽之該塗層較佳地減弱及/或反射至少10 db之電磁干擾。併入有該SIP裝置之行動裝置可包含用於接收無線資料之接收器及用於傳輸無線資料之傳輸器。
現將在參考意欲表示本發明之各種可能之組態之附圖所闡述之詳細實施例方面呈現上文所列舉之目標及優點連同本發明所表示之其他目標、特徵及進步。將本發明之其他實施例及態樣視為為熟習此項技術者所掌握。
除非以其他方式顯而易見或另有陳述，方向性參考(諸如「上部」、「下部」、「內」、「外」、「頂部」、「底部」、「垂直」、「水平」、「向上」、「向下」、「上方」、「下方」及諸如此類)意欲係相對於如圖中所展示之本發明之特定實施例之定向。此外，圖式中之既定參考編號當其顯現在不同圖中時指示相同或類似結構且相似參考編號識別本發明之類似結構元件及/或特徵。
本發明之實施例闡述電磁干擾(EMI)屏蔽方法及組態。本發明之屏蔽結構減輕對併入有系統級封裝(SIP)組件之電子裝置中之電部件、機械部件以及其他部件及子系統之EMI。由SIP表示之單個封裝可包含安裝在基板上之複數個部件。實例配置包含安裝在由習用PCB材料(諸如玻璃纖維填充之環氧樹脂)形成之印刷電路板(PCB)上之被動部件及主動部件兩者。應理解，可在電子裝置中使用SIP組件，諸如包含行動電話、平板電腦、電腦、腕表及諸如此類之可攜式電子裝置。
圖1圖解說明諸如行動裝置10之例示性可攜式電子裝置，行動裝置10具有殼體12及SIP組件14，但不存在任何經外模製介電質。SIP組件14包含諸如PCB之基板16及安裝在基板16上之複數個部件20-28。部件20-28可包含諸如處理器、積體電路、無線收發器、接收器及傳輸器之主動部件，及諸如電阻器及電容器之被動部件。如圖1中所圖解說明，理論上，複數個部件20-28可劃分成部件模組30-32，其中劃界係由虛線33、34所圖解說明。部件20-28可基於其等功能性分組為不同模組，其中部件20-22包含在部件模組30中，部件25-28包含在部件模組31中，且組件23、24包含在部件模組32中。將一個模組中之部件與另一模組中之彼等部件屏蔽可係較佳的，在缺乏此屏蔽之情形下，有害EMI可能影響各別部件之效能。舉例而言，無線通信積體電路22可位於部件模組30中以屏蔽自(舉例而言)部件模組31中之部件25發出之信號。
圖2係SIP組件14之示意性端視圖。示意性部件20a、20b安裝在基板16上且囊封於形成介電層18之經外模製介電材料中。基板16上之複數個部件模組30-32形成基板16之經組裝表面35。經組裝表面35沿著基板16之表面且在部件模組30-32之部件周圍延伸。絕緣層18可囊封經組裝表面35，其中絕緣層18在經組裝表面35與外表面19之間延伸。
絕緣層18可由各種材料形成，諸如環氧樹脂或通常為熱固性材料、熱塑性材料或在電絕緣經組裝表面35中使用之其他材料。在某些實施例中，絕緣層18可由既電絕緣亦導熱之材料形成以促進離開部件20-28之熱轉移。在某些實施例中。絕緣層18可稱為介電質或介電層。
基板16可係電絕緣材料(諸如環氧樹脂疊層)之印刷電路板(PCB)。舉例而言，基板16可包含電絕緣材料層，諸如聚四氟乙烯、諸如阻燃劑4(FR–4)、FR–1、棉紙之酚醛棉紙材料及使用環氧樹脂材料層壓在一起之諸如CEM–1或CEM–3或編織玻璃材料之環氧樹脂材料。可形成穿過電絕緣層之諸如跡線、溝槽、導通體之互聯結構以將部件20-22之電信號路由穿過基板16。
基板16可包含電耦合至接地平面42之金屬跡線40。金屬跡線40及接地平面42較佳地可由導電材料形成且可保護基板16免受來自切削製程(包含溝槽之形成)之損壞，如下文更詳細闡述。在某些實施例中，金屬跡線40能夠反射在切削/燒蝕絕緣層18之部分中使用之入射雷射能量以形成溝槽。
諸如雷射之切削裝置可在絕緣層18中形成一或多個溝槽44。溝槽44劃界部件模組30-32，溝槽44通常作為其中沈積EMI屏蔽材料之區域以便屏蔽EMI以免自一個部件模組傳播至毗鄰部件模組。如圖4中所圖解說明，可在毗鄰部件模組30、31之間且穿過絕緣層18至跡線40而形成溝槽44。在藉助雷射切削工具形成溝槽44之實施例中，跡線40可能夠反射雷射能量以有效地充當對雷射切削/燒蝕穿透至SIP 14中之阻礙。跡線40亦充當在經組裝表面35處曝露於溝槽44之導電接觸點。因此，在溝槽44處經屏蔽之EMI可透過跡線40傳導至接地平面42。溝槽44具有介於10 μm與100 μm之間之最大寬度尺寸「w」。
如上文所闡述，在溝槽中沈積薄導電屏蔽層以屏蔽部件模組之間之EMI係已知的。此等習用屏蔽層通常透過化學汽相沈積、物理汽相沈積或電化學電鍍技術來沈積且由諸如銅或鋁之導電金屬形成。習用EMI屏蔽方法然後將單獨EMI屏蔽層施加至絕緣層之外表面以覆蓋絕緣層之上部表面及側表面。此單獨屏蔽層結合上文所闡述之溝槽屏蔽層來操作以實現延伸至部件模組之間之溝槽中之薄「屏蔽罩」。
在圖5至圖7中所圖解說明之實施例中，在自支撐膜預型件50中提供EMI屏蔽材料，其可在單個層壓製程中層壓於SIP 14上以塗佈溝槽44及覆蓋絕緣層18之至少外表面19。EMI屏蔽膜預型件50亦可經層壓以覆蓋基板16之側邊緣17，且電接觸在基板16之一或多個側邊緣17處之導電平面42。可在單個層壓製程中執行EMI屏蔽膜預型件50之層壓以既在溝槽44內亦在SIP 14之外表面周圍提供EMI屏蔽。藉由用單個自支撐膜既在溝槽44內亦在外表面19周圍施加EMI屏蔽層，可極大加速經EMI屏蔽之SIP單元之處理輸送量。
EMI 屏蔽材料
EMI屏蔽膜預型件50較佳地係導電的自支撐主體，其能夠有效地減弱及/或反射電磁輻射之至少某些頻率。EMI屏蔽可包含入射能量之反射及吸收中之一或多者，且預期本發明之屏蔽膜能夠具有任一個或兩個特性。本發明中使用之EMI屏蔽材料可展現小於0.1 Ω * cm，較佳地介於約2.0 * 10-6 Ω * cm 與0.1 Ω * cm之間之體積電阻率，且可達到約5.0 * 10-6 Ω * cm與1.0 * 10-2 Ω * cm之間。「有效EMI屏蔽」意欲意指在介於10 MHz與10 GHz之間下介於1 dB/5 μm與200 dB/5 μm之間。
EMI屏蔽膜預型件50之態樣係其展現充分撓性/伸長率從而可在單個層壓製程中形成在SIP 14周圍且形成至窄溝槽44中。為了維持採用SIP之板之緊湊性，期望溝槽44係儘可能窄的，其中最大寬度尺寸「w」介於1 μm與100 μm之間。申請人發現，成功地施加習用導電膏以既大致上填充溝槽44亦覆蓋絕緣層18之外表面19係困難的。因此，EMI屏蔽膜預型件50可係撓性但可自支撐之膜。針對本發明之目的，術語「自支撐膜」應意指一種具有小於0.5 mm之厚度且在20°C下且在無組態維持支撐之情形下能夠維持其三維組態之膜。術語「組態維持支撐」意欲意指抵抗所施加力而接觸膜以維持在缺乏此所施加力之情形下所界定之膜之最初組態的結構。
如上文所闡述，EMI屏蔽膜預型件50較佳地係具有介於1 μm與500 μm，較佳地介於5 μm與200 μm，且更佳地介於5 μm與80 μm之間之厚度「t」的自支撐膜。膜厚度可係大致上均勻的。膜預型件50亦可較佳地係撓性的，在20°C下具有至少2%，較佳地至少3%且更佳地至少5%之伸長率。可在伊斯特朗電子拉力機(Instron 5566)上以25 mm/min之負載速度使用50 N荷重元使用應力應變測試方法來判定膜之伸長率。經測試之膜具有5 mm x 10 mm x 0.3 mm厚之尺寸。EMI屏蔽膜預型件50在20°C下可係大致上非膠黏的。
EMI屏蔽膜預型件50可由聚合物基質及分散於聚合物基質中之填料形成。實例導電填料包含微粒形式之金屬，諸如銅、鋁、銀、金、諸如鎳鐵合金之金屬合金及其他導電材料。實例磁干擾吸收填料包含鐵、鎳及鎳鐵合金。在實施例中，EMI屏蔽膜預型件50之聚合物基質可包含熱塑性或熱固性樹脂，包含(舉例而言)環氧樹脂、聚胺基甲酸酯樹脂、聚丙烯酸酯樹脂。
在某些實施例中，EMI屏蔽膜預型件50可包含多個層，包含具有不同EMI屏蔽性質之層。多層預型件50之各種層可係基於聚合物或基於非聚合物的，包含一或多個金屬箔層。用作預型件50之多層膜之不同層可吸收及/或反射電磁輻射之不同或重疊頻率範圍。在某些實施例中，多層膜或預型件50之層可具有不同或重疊物理性質，諸如伸長率、拉伸模數、體積電阻率、導熱率、玻璃轉變溫度等。在某些實施例中，EMI屏蔽膜預型件50可係導熱的，具有沿著厚度方向之至少0.5 W/m * K，且更佳地至少約1.0 W/m * K之導熱率。
在某些實施例中，EMI屏蔽膜預型件50可視為導電黏合劑。
EMI屏蔽材料可係可固化的，其中自支撐EMI屏蔽膜預型件50可係處於經預固化狀態以供在SIP處層壓。經預固化膜預型件50可在介於20°C與250°C之間之操作溫度下展現小於1 GPa之拉伸模數，但維持足以在20°C下自支撐之結構性質。在某些實施例中，經層壓預型件50可隨著升高之溫度(舉例而言在大於60°C下持續至少十分鐘，且較佳地在至少100°C之溫度下持續至少20分鐘)而固化。EMI屏蔽膜預型件50亦可係可固化的或替代地可透過其他固化機制固化的，包含輻射及觸媒添加。自預型件50之經固化層壓在20°C下可展現大於50 MPa、大於250 MPa、或大於1GPa之拉伸模數。在其他實施例中，自支撐EMI屏蔽膜預型件50可係非固化的或處於經固化狀態，其中在SIP 14處之層壓期間或之後不需要或無可用的實質上進一步交聯。在任一情形下，EMI屏蔽膜預型件50較佳地係可施加至SIP 14且層壓為溝槽44內及外表面19周圍之塗層之自支撐主體。
層壓製程
可在單個層壓製程中將EMI屏蔽膜預型件50固定至SIP 14。在一項實施例中，可抵靠絕緣層18之外表面19且視情況進一步抵靠基板16之側表面17真空層壓EMI屏蔽膜預型件50。真空層壓較佳地在溝槽44中形成塗層且覆蓋絕緣層18之外表面19，且視情況覆蓋基板16之側表面17。圖6中圖解說明將EMI屏蔽膜預型件50真空層壓至SIP 14上之較佳配置。
在某些實施例中，將預型件50層壓至SIP 14上可大致上填充溝槽44且覆蓋絕緣層18之外表面19。為了「大致上填充」溝槽44，EMI屏蔽材料消除或幾乎消除由溝槽44在絕緣層18中界定之所有空隙空間。然而，在其他實施例中，將預型件50層壓至SIP 14上在溝槽44中形成塗層，如在圖6A中所圖解說明。此塗層較佳地藉由在金屬跡線40處之導電點與接地平面42之間圍繞各別部件模組30-32形成連續EMI屏蔽層而囊封各別部件20a、20b。經層壓塗層可具有介於約1 µm與500 µm之間，較佳地介於約5 µm與200 µm之間且更佳地介於約5 µm與80 µm之間之厚度。
用於施加EMI屏蔽膜預型件50之實例製程包含加熱預型件50至可流動狀態。針對本發明之目的，術語「可流動狀態」應意指小於1 GPa之拉伸模數。在某些實施例中，EMI屏蔽膜預型件50可加熱至至少50°C以達成可流動狀態，且較佳地介於50°C與175°C之間。在其他實施例中，在層壓之前或與層壓同時，不需要將EMI屏蔽膜預型件50加熱至環境室溫以上或20°C，使得自支撐預型件50在環境室溫或20°C下係處於充分流動狀態以供真空層壓。
經加熱或未經加熱EMI屏蔽膜預型件50可抵靠SIP 14(包含絕緣層18之外表面19)真空層壓且真空層壓至溝槽44中以在溝槽44中形成塗層且覆蓋絕緣層18之外表面19。亦可抵靠絕緣層18之外表面上、基板16之側表面17上層壓EMI屏蔽膜預型件50且層壓至溝槽44中以形成大致上填充溝槽44且覆蓋絕緣層18之外表面19及基板16之側表面17之塗層。EMI屏蔽膜預型件50可經層壓以建立與接地平面42及金屬跡線40中之一者或兩者之電接觸。EMI屏蔽膜預型件50亦可經層壓以便建立與SIP 14之一或多個導電區域之電接觸。
可透過真空層壓製程將EMI屏蔽膜預型件50施加至SIP 14，該真空層壓製程包含將預型件50放置於絕緣層18之外表面19處且將組件定位於真空層壓機之層壓室中，將層壓室中之溫度設定為介於0°C與200°C之間，較佳地介於20°C與175°C之間且更佳地介於25°C與75°C之間，且將壓力減小至小於500 mm Hg，較佳地小於250 mm Hg，且更佳地介於100 mm Hg與200 mm Hg之間。在某些實施例中，維持此等溫度及壓力條件持續1至10分鐘。當減少之壓力施加於SIP 14之空隙區中之膜預型件下面時，可在膜之上部表面施加力以抵靠絕緣層18之外表面19加壓膜且加壓至溝槽44中。至少50 psi且較佳地介於0.1 MPa與1.0 MPa之間之加壓力可藉由可充氣氣囊施加，當減少之壓力施加於SIP 14之空隙區中時，可充氣氣囊抵靠預型件50充氣。圖7A至圖7B圖解說明可充氣氣囊92在層壓製程中抵靠膜預型件50上充氣且施加力。加壓力及減少之壓力起作用以抵靠絕緣層18之外表面19層壓預型件50且層壓至溝槽44中。
可以至少50 psi之力抵靠絕緣層18之外表面19加壓藉由將預型件50層壓至SIP 14上而形成之塗層。此加壓力之施加在圖7C中圖解說明，且由力箭頭「F」表示。可藉助壓力機構施加加壓力「F」以進一步抵靠絕緣層18之外表面19壓迫EMI屏蔽膜預型件50且壓迫至溝槽44中。加壓力「F」可藉由真空層壓機之可充氣氣囊92或砧壓機(未展示)來供應。
可在如圖7A至圖7C中所圖解說明之加壓操作之前，之同時，之後或缺乏此操作情形下，使由經層壓EMI屏蔽膜預型件50形成之塗層原位固化。在某些實施例中，塗層可在20°C下固化至至少1 GPa之拉伸模數。
圖8圖解說明用於形成具有EMI屏蔽膜之SIP組件之流程圖。製程包含在步驟72中提供基板或PCB。如在步驟74中所展示，在基板之表面上安裝部件。在步驟76中，使用合意製程形成絕緣層。舉例而言，絕緣層可經模製且隨後轉移至基板之經組裝表面或可在基板之經組裝表面原位模製。如在此項技術中已知，絕緣層可係射出模製的、燒結的、基質模製的、壓縮模製的、擠出模製的及諸如此類。為了使絕緣層原位形成，介電材料可於原位模製或透過沈積製程沈積。
可在步驟78中藉由沿著劃界邊界在絕緣層中切削或燒蝕通道/溝槽而劃界部件模組。適合於形成劃界溝槽/通道之切削工具包含雷射切削工具、鋸切工具或機械加工工具。
在步驟80中，接著將EMI屏蔽膜層壓在絕緣層上方及溝槽/通道內。經層壓EMI屏蔽層塗佈溝槽/通道，且建立與金屬跡線及接地平面之電接觸以形成圍繞各別部件模組之EMI屏蔽。EMI屏蔽層由EMI屏蔽膜預型件形成，該EMI屏蔽膜預型件可係具有物理性質之自支撐膜，該等物理性質促進絕緣層上方及溝槽/通道內之合意層壓。
批次處理
在某些實施例中，可在單粒化之前，在批次製程中同時EMI屏蔽複數個SIP裝置。圖9中圖解說明安裝在基板上且劃界為複數個部件模組之部件之陣列110。可(諸如)藉由真空層壓至陣列110上而層壓EMI屏蔽膜150以塗佈溝槽144且覆蓋介電陣列118之外表面119。將EMI屏蔽膜150層壓至陣列110上可在單個層壓製程中執行，如上文關於SIP 14所闡述。繼層壓製程(包含EMI屏蔽膜150之任何加壓及/或固化)之後，可藉由在切削線111處切穿陣列110及EMI屏蔽膜150而自陣列110單粒化複數個SIP裝置114。以此方式，可在單個批次製程(包含單個EMI屏蔽膜層壓製程)中形成複數個SIP裝置114。
圖12至圖15中圖解說明替代性批次製程，其中藉由在諸如PCB之基板216上安裝複數個部件而形成陣列210，基板216具有接地平面242及電耦合至接地平面242且延伸至基板216之上部表面之複數個導電跡線240，該上部表面形成經組裝表面235之部分。部件可囊封於介電陣列218中。可用各種切削工具沿著切削線211切削陣列210以將陣列初始地分離為子陣列裝置282，子陣列裝置282可用黏合劑286安裝至載體284上，如圖13中所展示。子陣列裝置282可以充足間距「S」放置於載體284處以准許當定位於載體284處時在毗鄰子陣列裝置282之各別面對表面處形成EMI屏蔽膜。透過層壓製程(諸如真空層壓製程)將EMI屏蔽膜250施加至圖13中所圖解說明之配置以囊封子陣列裝置282之曝露表面，包含溝槽244內，且在某些實施例中大致上填充溝槽244。圖14中圖解說明經層壓配置。然後可將子陣列裝置282單粒化為複數個經EMI屏蔽SIP，該等經EMI屏蔽SIP藉由在切削線292處切穿EMI屏蔽膜250且自與載體284之接合移除子陣列裝置282而形成。圖15中展示複數個經單粒化SIP裝置295。圖16中示意性地圖解說明併入有本發明之SIP裝置之行動裝置300。SIP裝置302安裝在殼體301上且包含至少一處理器304。行動裝置300之其他相關部件包含用於接收無線資料之接收器306及用於傳輸無線資料之傳輸器308。
在某些實施例中，SIP裝置302亦可包含記憶體裝置310及示意性地圖解說明為元件312之複數個被動部件。應理解，行動裝置300可包含數個其他部件及元件以使得行動裝置300可充分操作，儘管出於簡化之目的未展示此等部件及元件。
本文已非常詳細地闡述本發明以便順應專利法規並向熟習此項技術者提供應用新穎原理及根據需要構築並使用本發明之實施例所需之資訊。然而，應理解，可藉由特定不同裝置來實施本發明且可在不違背本發明自身之範疇之情形下達成各種修改。
10‧‧‧行動裝置
12‧‧‧殼體
14‧‧‧系統級封裝組件/系統級封裝
16‧‧‧基板
17‧‧‧基板之側邊緣/側邊緣/基板之側表面
18‧‧‧介電層/絕緣層
19‧‧‧外表面/絕緣層之外表面
20‧‧‧部件
20a‧‧‧示意性部件/各別部件
20b‧‧‧示意性部件/各別部件
21‧‧‧部件
22‧‧‧部件/無線通信積體電路
23‧‧‧部件
24‧‧‧部件
25‧‧‧部件
26‧‧‧部件
27‧‧‧部件
28‧‧‧部件
30‧‧‧部件模組/毗鄰部件模組/各別部件模組
31‧‧‧部件模組/毗鄰部件模組/各別部件模組
32‧‧‧部件模組/各別部件模組
33‧‧‧虛線
34‧‧‧虛線
35‧‧‧基板之經組裝表面/經組裝表面/電絕緣經組裝表面
40‧‧‧金屬跡線/跡線
42‧‧‧接地平面/導電平面
44‧‧‧溝槽/窄溝槽
50‧‧‧自支撐膜預型件/EMI屏蔽膜預型件/膜預型件/多層預型件/預型件/多層膜或預型件/經預固化膜預型件/經層壓預型件/自支撐預型件
92‧‧‧可充氣氣囊
110‧‧‧部件之陣列/陣列
111‧‧‧切削線
114‧‧‧系統級封裝裝置
118‧‧‧介電陣列
119‧‧‧介電陣列之外表面
144‧‧‧溝槽
150‧‧‧電磁干擾屏蔽膜
210‧‧‧陣列
211‧‧‧切削線
216‧‧‧基板
218‧‧‧介電陣列
235‧‧‧經組裝表面
240‧‧‧導電跡線
242‧‧‧接地平面
244‧‧‧溝槽
250‧‧‧電磁干擾屏蔽膜
282‧‧‧子陣列裝置
284‧‧‧載體
286‧‧‧黏合劑
292‧‧‧切削線
295‧‧‧系統級封裝裝置
300‧‧‧行動裝置
301‧‧‧殼體
302‧‧‧系統級封裝裝置
304‧‧‧處理器
306‧‧‧接收器
308‧‧‧傳輸器
310‧‧‧記憶體裝置
312‧‧‧元件
圖1係包含系統級封裝組件之可攜式電子裝置之示意性圖解說明。
圖2係圖1中所展示之系統級封裝組件之示意性端視圖。
圖3係系統級封裝組件之剖視圖。
圖4係具有形成於介電層中之溝槽之系統級封裝組件之剖視圖。
圖5係EMI屏蔽膜及系統級封裝組件之圖解說明。
圖6係在系統級封裝組件處層壓之EMI屏蔽膜之剖視圖。
圖6A係在系統級封裝組件處層壓之EMI屏蔽膜之剖視圖。
圖7A係放置在系統級封裝組件處之EMI屏蔽膜及經放氣壓力氣囊之剖視圖。
圖7B係藉由經放氣壓力氣囊在系統級封裝組件處層壓及加壓之EMI屏蔽膜之剖視圖。
圖7C係層壓及加壓在系統級封裝組件處之EMI屏蔽膜之剖視圖。
圖8係用於形成具有EMI屏蔽膜之系統級封裝組件之流程圖。
圖9係安裝在基板上且劃界為複數個部件模組之部件陣列之剖視圖。
圖10係圖9中所圖解說明之具有層壓至其之EMI屏蔽膜之陣列之剖視圖。
圖11係自圖10中所圖解說明之陣列單粒化之複數個系統級封裝裝置之剖視圖。
圖12係安裝在基板上且劃界為複數個部件模組之部件之剖視圖。
圖13係來自圖12之安裝至載體之子陣列裝置之剖視圖。
圖14係圖13中所圖解說明之具有層壓至其之EMI屏蔽膜之複數個子陣列裝置之剖視圖。
圖15係經單粒化系統級封裝裝置之剖視圖。
圖16係併入有本發明之系統級封裝裝置之行動裝置之示意性圖解說明。

Claims (17)

  1. 一種用於屏蔽系統級封裝組件免受電磁干擾之方法，其中該系統級封裝組件包含：基板；安裝在該基板上之複數個部件模組，其中每一部件模組包含一或多個部件；覆蓋該基板上之該等部件之絕緣體；及形成在該絕緣體中毗鄰部件模組之間之溝槽，其中該溝槽具有介於10 μm與100 μm之間之最大寬度，該方法包括： 提供自支撐EMI屏蔽膜預型件，其在介於20°C與250°C之間下具有小於1 GPa之拉伸模數； 抵靠該絕緣體之外表面真空層壓該自支撐EMI屏蔽膜預型件且真空層壓至該溝槽中以在該溝槽中形成塗層且覆蓋該絕緣體之該外表面；及 固化該塗層至至少50 MPa之拉伸模數。
  2. 如請求項1之用於屏蔽系統級封裝組件之方法，其包含在固化之前，抵靠該絕緣體加壓該塗層。
  3. 如請求項2之用於屏蔽系統級封裝組件之方法，其包含在固化之前，用至少50 psi之力抵靠該絕緣體之該外表面加壓該塗層。
  4. 如請求項1之用於屏蔽系統級封裝組件之方法，其中該預型件包含分散於聚合物樹脂基質中之導電微粒填料。
  5. 如請求項1之用於屏蔽系統級封裝組件之方法，其包含在真空層壓之前，加熱該預型件至至少50°C。
  6. 如請求項1之用於屏蔽系統級封裝組件之方法，其包含抽空該溝槽以抵靠該絕緣體之該外表面真空層壓該經加熱預型件且真空層壓至該溝槽中。
  7. 如請求項1之用於屏蔽系統級封裝組件之方法，其中固化該塗層包含加熱該塗層至至少60°C持續至少十分鐘。
  8. 如請求項7之用於屏蔽系統級封裝組件之方法，其中該經固化塗層在20°C下展現至少1 GPa之拉伸模數。
  9. 如請求項1之用於屏蔽系統級封裝組件之方法，其中該塗層大致上填充該溝槽。
  10. 一種用於形成系統級封裝組件之方法，其包括： 提供基板及導電跡線，該基板具有與該基板之主動表面隔開之導電接地平面，且該導電跡線自該接地平面延伸至該主動表面； 在該基板之該主動表面處安裝複數個部件模組以形成該基板之經組裝表面，其中每一部件模組包含一或多個部件； 將該基板之該經組裝表面囊封於介電層中，其中該介電層在該經組裝表面與外表面之間延伸； 在毗鄰部件模組之間且穿過該介電層至該跡線形成溝槽，該溝槽具有介於10 μm與100 μm之間之最大寬度； 抵靠該介電層之該外表面真空層壓自支撐EMI屏蔽膜預型件且真空層壓至該溝槽中以在該溝槽中形成接觸該跡線且覆蓋該介電層之該外表面之塗層，該自支撐EMI屏蔽膜預型件在介於20°C與250°C之間下具有小於1 GPa之拉伸模數。
  11. 如請求項10之用於形成系統級封裝組件之方法，其包含固化該塗層至至少50 MPa之拉伸模數。
  12. 如請求項10之用於形成系統級封裝組件之方法，其包含用至少50 psi之力抵靠該介電層之該外表面加壓該塗層。
  13. 如請求項12之用於形成系統級封裝組件之方法，其包含藉由切穿該基板及該介電層而單粒化複數個系統級封裝裝置。
  14. 如請求項13之用於形成系統級封裝組件之方法，其包含在該介電層中形成複數個溝槽，其中每一溝槽劃界第一組一或多個部件模組與第二組一或多個模組。
  15. 如請求項10之用於形成系統級封裝組件之方法，其中該塗層大致上填充該溝槽。
  16. 如請求項10之用於形成系統級封裝組件之方法，其中該塗層接觸該導電接地平面。
  17. 一種行動裝置，其包括： 殼體； 接收器，其用於接收無線資料； 傳輸器，其用於傳輸無線資料；及 系統級封裝組件，該系統級封裝組件包括 基板； 安裝在該基板上之複數個部件模組，其中每一部件模組包含一或多個部件， 覆蓋該基板上之該等部件之絕緣體，及 形成在該絕緣體中毗鄰部件模組之間之溝槽，其中該溝槽具有介於10 μm至100 μm之間之最大寬度， 該溝槽中之塗層，其覆蓋該絕緣體之該外表面且具有至少50 MPa之拉伸模數， 其中該系統級封裝組件安裝在該殼體上， 其中該系統級封裝組件之該一或多個部件包含至少一處理器，且 其中該系統級封裝組件包含劃界至少兩個部件模組之該等溝槽中之至少一者， 其中大致上填充該溝槽之該塗層減弱至少10 db之電磁干擾。
TW108103843A 2018-02-01 2019-01-31 用於屏蔽系統級封裝組件免受電磁干擾的方法 TWI787448B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201862625162P 2018-02-01 2018-02-01
US62/625,162 2018-02-01

Publications (2)

Publication Number Publication Date
TW201935575A true TW201935575A (zh) 2019-09-01
TWI787448B TWI787448B (zh) 2022-12-21

Family

ID=67478874

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108103843A TWI787448B (zh) 2018-02-01 2019-01-31 用於屏蔽系統級封裝組件免受電磁干擾的方法

Country Status (6)

Country Link
US (2) US10834858B2 (zh)
EP (1) EP3747049A4 (zh)
JP (1) JP7334169B2 (zh)
CN (1) CN111684590A (zh)
TW (1) TWI787448B (zh)
WO (1) WO2019152762A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI748427B (zh) * 2020-04-24 2021-12-01 大陸商宏啟勝精密電子（秦皇島）有限公司 電路板及其製造方法
TWI820587B (zh) * 2021-04-09 2023-11-01 群創光電股份有限公司 電子裝置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11363746B2 (en) * 2019-09-06 2022-06-14 Teradyne, Inc. EMI shielding for a signal trace
WO2021124805A1 (ja) * 2019-12-20 2021-06-24 株式会社村田製作所 電子部品モジュール
CN114375111B (zh) * 2020-10-14 2023-06-02 华为技术有限公司 一种封装模块、封装方法及电子设备

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004202602A (ja) 2002-12-24 2004-07-22 Sony Corp 微小構造体の製造方法、及び型材の製造方法
WO2004093506A2 (en) 2003-04-15 2004-10-28 Wavezero, Inc. Electomagnetic interference shielding for a printed circuit board
US7633170B2 (en) 2005-01-05 2009-12-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method thereof
KR100606654B1 (ko) 2005-08-01 2006-08-01 삼성전자주식회사 전자파 장해 저감용 페라이트 차폐 구조를 구비하는 반도체패키지 및 그 제조 방법
US20080067650A1 (en) 2006-09-15 2008-03-20 Hong Kong Applied Science and Technology Research Institute Company Limited Electronic component package with EMI shielding
TWI334215B (en) 2007-01-26 2010-12-01 Advanced Semiconductor Eng Semiconductor package having electromagnetic shielding cap
US7633015B2 (en) 2008-03-31 2009-12-15 Apple Inc. Conforming, electro-magnetic interference reducing cover for circuit components
US7741567B2 (en) 2008-05-19 2010-06-22 Texas Instruments Incorporated Integrated circuit package having integrated faraday shield
US7772046B2 (en) 2008-06-04 2010-08-10 Stats Chippac, Ltd. Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference
US8263437B2 (en) 2008-09-05 2012-09-11 STATS ChiPAC, Ltd. Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit
US8168470B2 (en) 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
CN101800215B (zh) 2009-02-11 2012-07-04 日月光半导体制造股份有限公司 无线通讯模组封装构造
JP2010206044A (ja) * 2009-03-05 2010-09-16 Toshiba Corp 半導体装置の製造方法
JP2010245931A (ja) * 2009-04-08 2010-10-28 Panasonic Corp アンテナ一体型モジュール部品とその製造方法と、これを用いた電子機器
JP2011018873A (ja) 2009-05-22 2011-01-27 Sony Ericsson Mobilecommunications Japan Inc 電磁シールド方法および電磁シールド用フィルム
US8212340B2 (en) * 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20110291032A1 (en) 2010-05-27 2011-12-01 Industrial Technology Research Institute Electromagnetic shielding composition, electromagnetic shielding device, anti-electrostatic device and method of manufacturing electromagnetic shielding structure
KR101855294B1 (ko) 2010-06-10 2018-05-08 삼성전자주식회사 반도체 패키지
US8183130B2 (en) 2010-06-15 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer around back surface and sides of semiconductor wafer containing IPD structure
TWI540698B (zh) 2010-08-02 2016-07-01 日月光半導體製造股份有限公司 半導體封裝件與其製造方法
WO2012031362A1 (en) 2010-09-07 2012-03-15 Corporation De L ' Ecole Polytechnique De Montreal Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributed-sensors and electrical signal propagation
US20120126378A1 (en) 2010-11-24 2012-05-24 Unisem (Mauritius ) Holdings Limited Semiconductor device package with electromagnetic shielding
US8969136B2 (en) * 2011-03-25 2015-03-03 Stats Chippac Ltd. Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereof
US8791015B2 (en) 2011-04-30 2014-07-29 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over active surface of semiconductor die
KR20130035620A (ko) 2011-09-30 2013-04-09 삼성전자주식회사 Ｅｍｉ 쉴드된 반도체 패키지 및 ｅｍｉ 쉴드된 기판 모듈
US8872312B2 (en) 2011-09-30 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. EMI package and method for making same
US8420437B1 (en) 2011-12-05 2013-04-16 Powertech Technology Inc. Method for forming an EMI shielding layer on all surfaces of a semiconductor package
JP2013207213A (ja) * 2012-03-29 2013-10-07 Tdk Corp 電子部品モジュール及びその製造方法
CN102711428B (zh) 2012-06-21 2015-11-18 广州方邦电子有限公司 一种高屏蔽效能的极薄屏蔽膜及其制作方法
US9070627B2 (en) 2013-09-11 2015-06-30 Broadcom Corporation Interposer package-on-package structure
US9713255B2 (en) 2014-02-19 2017-07-18 Intel Corporation Electro-magnetic interference (EMI) shielding techniques and configurations
WO2015129546A1 (ja) 2014-02-25 2015-09-03 住友ベークライト株式会社 電磁波シールドフィルム、フレキシブルプリント基板、電子部品搭載基板、及び電子部品の被覆方法
JP6303597B2 (ja) 2014-02-28 2018-04-04 東洋インキＳｃホールディングス株式会社 電子部品モジュールの製造方法
US9913412B2 (en) 2014-03-18 2018-03-06 Apple Inc. Shielding structures for system-in-package assemblies in portable electronic devices
US20150291911A1 (en) 2014-04-14 2015-10-15 Battelle Memorial Institute Triacylglycerol Based Composition
US9820373B2 (en) * 2014-06-26 2017-11-14 Apple Inc. Thermal solutions for system-in-package assemblies in portable electronic devices
TW201601915A (zh) * 2014-07-07 2016-01-16 聯茂電子股份有限公司 電磁波干擾遮蔽薄膜
TWI614870B (zh) * 2014-07-25 2018-02-11 矽品精密工業股份有限公司 封裝結構及其製法
US9536841B2 (en) * 2014-08-01 2017-01-03 Cyntec Co., Ltd. Semiconductor package with conformal EM shielding structure and manufacturing method of same
JP6254509B2 (ja) * 2014-11-07 2017-12-27 信越化学工業株式会社 電磁波シールド性支持基材付封止材及び封止後半導体素子搭載基板、封止後半導体素子形成ウエハ並びに半導体装置
US9929100B2 (en) 2015-04-17 2018-03-27 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
TWI562318B (en) 2015-09-11 2016-12-11 Siliconware Precision Industries Co Ltd Electronic package and fabrication method thereof
US20170118877A1 (en) * 2015-10-22 2017-04-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Circuit package with bond wires to provide internal shielding between electronic components
US10461007B2 (en) * 2015-12-22 2019-10-29 Intel Corporation Semiconductor package with electromagnetic interference shielding
US20170179041A1 (en) * 2015-12-22 2017-06-22 Intel Corporation Semiconductor package with trenched molding-based electromagnetic interference shielding
US10163810B2 (en) * 2015-12-26 2018-12-25 Intel Corporation Electromagnetic interference shielding for system-in-package technology
KR20170105809A (ko) 2016-03-10 2017-09-20 삼성전기주식회사 전자부품 패키지 및 그 제조방법
WO2017171813A1 (en) * 2016-03-31 2017-10-05 Intel Corporation Electromagnetic interference shielding for semiconductor packages using bond wires
KR101858952B1 (ko) 2016-05-13 2018-05-18 주식회사 네패스 반도체 패키지 및 이의 제조 방법
US10056337B2 (en) * 2017-01-23 2018-08-21 International Business Machines Corporation Thin 3D die with electromagnetic radiation blocking encapsulation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI748427B (zh) * 2020-04-24 2021-12-01 大陸商宏啟勝精密電子（秦皇島）有限公司 電路板及其製造方法
US11985764B2 (en) 2020-04-24 2024-05-14 Hongqisheng Precision Electronics (Qinhuangdao) Co., Ltd. Circuit board and method for manufacturing the same
TWI820587B (zh) * 2021-04-09 2023-11-01 群創光電股份有限公司 電子裝置

Also Published As

Publication number Publication date
JP7334169B2 (ja) 2023-08-28
JP2021512498A (ja) 2021-05-13
EP3747049A4 (en) 2021-10-27
KR20200115463A (ko) 2020-10-07
US20210092884A1 (en) 2021-03-25
US10834858B2 (en) 2020-11-10
US11304346B2 (en) 2022-04-12
US20200084924A1 (en) 2020-03-12
WO2019152762A1 (en) 2019-08-08
CN111684590A (zh) 2020-09-18
EP3747049A1 (en) 2020-12-09
TWI787448B (zh) 2022-12-21

Similar Documents

Publication Publication Date Title
TWI787448B (zh) 用於屏蔽系統級封裝組件免受電磁干擾的方法
US8847184B2 (en) Composite film for board level EMI shielding
US9991211B2 (en) Semiconductor package having an EMI shielding layer
EP1764834B1 (en) Electromagnetic shielding of packages with a laminate substrate
US10356903B1 (en) System-in-package including opposing circuit boards
US20080029890A1 (en) Embedded chip package process and circuit board with embedded chip
US20090288852A1 (en) Electronic device and method of manufacturing the same
JP2011151372A (ja) 電子部品モジュールの製造方法及び電子部品モジュール
US11929542B2 (en) Sputtered SiP antenna
US20140198459A1 (en) Stacked package device and manufacturing method thereof
US20190372210A1 (en) Wireless module and electronic device
WO2013035819A1 (ja) 電子部品モジュール及び該電子部品モジュールの製造方法
US20180160525A1 (en) Circuit board device
KR20170097345A (ko) 전자 소자 모듈 및 그 제조 방법
CN112201652A (zh) 线路板及其制作方法
KR102683256B1 (ko) 전자기 간섭으로부터 시스템-인-패키지 조립체를 차폐하는 방법, 시스템-인-패키지 조립체를 형성하는 방법, 및 모바일 기기
JP2010258137A (ja) 高周波モジュールおよびその製造方法
CN106653734B (zh) 具有电磁干扰屏蔽的半导体装置及其制造方法
US20190279935A1 (en) Semiconductor package having package substrate containing non-homogeneous dielectric layer
US20240203899A1 (en) System-in-package module and method for manufacturing the same
TWI550728B (zh) 封裝結構及其製造方法
KR101350610B1 (ko) 반도체 패키지
CN116864492A (zh) 共形屏蔽结构及其制备方法
CN114496814A (zh) 一种电磁屏蔽封装方法以及电磁屏蔽封装结构