TW201933548A - 具有分層保護機制的半導體裝置及相關系統、裝置及方法 - Google Patents

具有分層保護機制的半導體裝置及相關系統、裝置及方法 Download PDF

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TW201933548A
TW201933548A TW107145862A TW107145862A TW201933548A TW 201933548 A TW201933548 A TW 201933548A TW 107145862 A TW107145862 A TW 107145862A TW 107145862 A TW107145862 A TW 107145862A TW 201933548 A TW201933548 A TW 201933548A
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Taiwan
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enclosure
die
substrate
metal
shell
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TW107145862A
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English (en)
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TWI710068B (zh
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衛 周
伯德 Ｋ 史崔特
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美商美光科技公司
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    • H01L23/20—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device gaseous at the normal operating temperature of the device
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Abstract

一種半導體裝置包含：一第一晶粒；一第二晶粒，其經附接於該第一晶粒上方；一第一金屬圍封殼及一第二金屬圍封殼，其等兩者直接接觸該第一晶粒及該第二晶粒，且在該第一晶粒與該第二晶粒之間垂直延伸，其中該第一金屬圍封殼周邊地環繞一組一或多個內部互連件，且該第二金屬圍封殼周邊地環繞該第一金屬圍封殼而未直接接觸該第一金屬圍封殼；一第一圍封殼連接器，其將該第一金屬圍封殼電連接至一第一電壓位準；一第二圍封殼連接器，其將該第二金屬圍封殼電連接至一第二電壓位準；且其中該第一金屬圍封殼、該第二金屬圍封殼、該第一圍封殼連接器及該第二圍封殼連接器經組態以提供一圍封電容。

Description

具有分層保護機制的半導體裝置及相關系統、裝置及方法
本技術係關於半導體裝置，且特定言之係關於具有一分層保護機制之半導體裝置。
半導體裝置晶粒(包含記憶體晶片、微處理器晶片及成像器晶片)通常包含安裝於另一結構(例如，一基板、另一晶粒等)上且包在一塑膠保護罩中之一半導體晶粒。晶粒包含諸如用於記憶體胞、處理器電路及成像器裝置之功能特徵以及電連接至功能特徵之互連件。互連件可電連接至保護罩外部之終端以將晶粒連接至較高階電路。
如圖1中繪示，一半導體裝置100 (例如，一三維互連(3DI)類型之裝置或一半導體封裝裝置)可包含其上具有晶粒互連件104之一晶粒102，晶粒102連接至其上具有基板互連件108之一基板結構106 (例如，一印刷電路板(PCB)、一半導體或晶圓級基板、另一晶粒等)。晶粒102及基板結構106可透過晶粒互連件104及基板互連件108彼此電耦合。此外，晶粒互連件104及基板互連件108可(例如，透過一接合程序，諸如擴散接合或混合接合)彼此直接接觸或透過一中間結構(例如，焊料)接觸。半導體裝置100可進一步包含一囊封劑(諸如一底膠填充110)，該囊封劑包圍或囊封晶粒102、晶粒互連件104、基板結構106、基板互連件108、其等之一部分或其等之一組合。
隨著其他領域之技術進步及增加的應用，市場一直在尋找更快且更小之裝置。為了滿足市場需求，半導體裝置之實體大小或尺寸正在被推向極限。例如，正努力減小晶粒102與基板結構106之間之一分離距離(例如，針對3DI裝置及晶粒堆疊封裝)。
然而，歸因於各種因素(例如，底膠填充110之黏度位準、陷留空氣/氣體、底膠填充110之不均勻流動、互連件之間之空間等)，囊封程序可能不可靠，諸如在晶粒102與基板結構106之間留下空隙114 (例如，其中互連件之部分未能直接接觸底膠填充110)。空隙114可能引起互連件之間(例如，基板互連件108之間及/或晶粒互連件104之間)之短路及洩漏而引起半導體裝置100之一電氣故障。此外，由於裝置愈來愈小，製造成本可增長(例如，基於使用奈米粒子底膠填充而非傳統底膠填充)。
根據本技術之一些實施例，一種半導體裝置包括：一第一晶粒；一第二晶粒，其附接於該第一晶粒上方；一第一金屬圍封殼及一第二金屬圍封殼，其等兩者直接接觸該第一晶粒及該第二晶粒且在該第一晶粒與該第二晶粒之間垂直延伸，其中該第一金屬圍封殼周邊地環繞一組一或多個內部互連件且該第二金屬圍封殼周邊地環繞該第一金屬圍封殼而未直接接觸該第一金屬圍封殼；一第一圍封殼連接器，其將該第一金屬圍封殼電連接至一第一電壓位準；一第二圍封殼連接器，其將該第二金屬圍封殼電連接至一第二電壓位準；且其中該第一金屬圍封殼、該第二金屬圍封殼、該第一圍封殼連接器及該第二圍封殼連接器經組態以提供一圍封電容。
根據本技術之一些實施例，一種製造一半導體裝置之方法包括：提供一晶粒，該晶粒包含晶粒互連件、一晶粒內部圍封殼及一晶粒外部圍封殼，其中：該等晶粒互連件自一晶粒底表面突出，該晶粒內部圍封殼自該晶粒底表面突出且周邊地包圍該等晶粒互連件，且該晶粒外部圍封殼自該晶粒底表面突出且周邊地包圍該晶粒內部圍封殼而未直接接觸該晶粒內部圍封殼；提供一基板，該基板包含基板互連件、一基板內部圍封殼及一基板外部圍封殼，其中：該等基板互連件自一基板頂表面突出，該基板內部圍封殼自該基板頂表面突出且周邊地包圍該等基板互連件，且該基板外部圍封殼自該基板頂表面突出且周邊地包圍該基板內部圍封殼而未直接接觸該基板內部圍封殼；及將該等基板互連件接合至該等晶粒互連件、將該基板內部圍封殼接合至該晶粒內部圍封殼，且將該基板外部圍封殼接合至該晶粒外部圍封殼。
根據本技術之一些實施例，一種包含具有至少兩個晶粒之一晶粒堆疊之半導體裝置包括：複數個互連件，其等電耦合該晶粒堆疊之兩個或更多個相鄰晶粒；一第一金屬密封部件及一第二金屬密封部件，其等安置於一對相鄰晶粒之間，其中該第一金屬密封部件圍封一或多個互連件且巢套於該第二金屬密封部件內；一第一連接機構，其直接接觸該第一金屬密封部件用於將該第一金屬密封部件電耦合至一第一電壓位準；及一第二連接機構，其直接接觸該第二金屬密封部件用於將該第二金屬密封部件電耦合至一第二電壓位準，以提供包圍該一或多個互連件、該對相鄰晶粒之至少一者之一中心部分或其等之一組合之一圍封電容。
(若干)相關申請案
本申請案含有與Wei Zhou、Bret Street及Mark Tuttle之標題為「SEMICONDUCTOR DEVICE WITH A PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS」之一先前申請之美國專利申請案相關的標的物。相關申請案經讓與給Micron Technology公司，且係由2017年8月31日申請之申請案第15/693,230號識別。該案之標的物係以引用的方式併入本文中。
本申請案含有與Wei Zhou及Bret Street之標題為「SEMICONDUCTOR DEVICE WITH AN ELECTRICALLY-COUPLED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS」之一同時申請之美國專利申請案相關的標的物。相關申請案經讓與給Micron Technology公司，且係由檔案號010829-9263.US00識別。該案之標的物係以引用的方式併入本文中。
本文中揭示之技術係關於半導體裝置、具有半導體裝置之系統及用於製造半導體裝置之相關方法。術語「半導體裝置」一般指代包含一或多個半導體材料之一固態裝置。半導體裝置之實例包含邏輯裝置、記憶體裝置及二極體等。此外，術語「半導體裝置」可指代一成品裝置或在成為一成品裝置之前之各個處理階段處的一總成或其他結構。取決於使用其之內容背景，術語「基板」可指代支撐電子組件(例如，一晶粒)之一結構，諸如一晶圓級基板或一單粒化晶粒級基板、用於晶粒堆疊或3DI應用之另一晶粒，或一印刷電路板(PCB)。一般技術者將認知，可在晶圓級或晶粒級執行本文中描述之方法之適合步驟。此外，除非上下文另有指示，否則本文中揭示之結構可使用習知半導體製造技術形成。可例如使用化學氣相沈積、物理氣相沈積、原子層沈積、旋塗及/或其他適合技術來沈積材料。類似地，可例如使用電漿蝕刻、濕式蝕刻、化學-機械平坦化或其他適合技術來移除材料。
下文在保護半導體晶粒及相關電連接且進一步利用保護結構來提供包圍有效信號(active signal)之電容諸如用於屏蔽有效信號的內容背景中描述本技術之許多實施例。例如，半導體裝置(例如，3DI封裝解決方案)可各自包含其上具有晶粒互連件之一或多個半導體晶粒，該一或多個半導體晶粒連接至一基板結構(例如，一PCB或另一晶粒)。為保護晶粒及晶粒互連件(例如，針對環境因素，諸如水分、碎屑等)，半導體裝置可各自包含沿一水平面包圍晶粒互連件之多個金屬(例如，銅、鋁、合金等)圍封殼。金屬圍封殼可進一步在晶粒與基板之間垂直延伸及/或直接接觸晶粒及基板，以圍封晶粒互連件且將晶粒互連件與外部環境隔離。因而，半導體裝置可使用金屬圍封殼代替任何囊封劑(例如，底膠填充)以將晶粒互連件與周圍外部空間及/或環境隔離。
對於包圍一組晶粒互連件之一組金屬圍封殼，一第一金屬圍封殼可包圍晶粒互連件且一或多個圍封殼(例如，一第二金屬圍封殼)可包圍第一金屬圍封殼而未直接接觸第一金屬圍封殼。在一些實施例中，該組金屬圍封殼可同心地配置。在一些實施例中，該組金屬圍封殼可為非同心的。
該組金屬圍封殼可經組態以提供一電容位準。在一些實施例中，半導體裝置可包含根據一組中之一對相鄰金屬圍封殼之間之一圍封殼分離距離的一圍封殼分離空間。在一些實施例中，圍封殼分離空間可填充有直接接觸相鄰金屬圍封殼之一介電材料(例如，形成一介電層)。分離空間及/或介電材料可提供包圍進行通過晶粒互連件之有效信號的一電容位準。例如，金屬圍封殼之一或多者可電連接至一第一電壓位準(例如，接地)且其他金屬圍封殼之一或多者可電連接至一第二電壓位準(例如，供應電壓)。因此，電力輸送可透過圍封電容改良。再者，環境保護及電屏蔽可基於分層金屬圍封殼而改良。
在一些實施例中，半導體裝置可包含各自包含多個晶粒之一或多個晶粒堆疊。晶粒堆疊可各自包含安置於一對相鄰晶粒之間之一組金屬圍封殼。不同對之相鄰晶粒之間之各層金屬圍封殼(例如，最外圍封殼、最內圍封殼、一第一中間圍封殼等)可諸如使用矽穿孔(TSV)、導電膏、導線(例如，接合導線)或其等之一組合電連接。
此外，一或多個金屬圍封殼可經電耦合以傳導電信號或一電位(例如，用於提供一接地連接或一源電壓)。在一些實施例中，最外金屬圍封殼可(例如，經由一直接接觸或透過另一導體)連接至一電磁干擾(EMI)屏蔽。在一些實施例中，第一金屬圍封殼及第二金屬圍封殼之一者或兩者可經接地。在一些實施例中，第一金屬圍封殼及第二金屬圍封殼可替代地連接至電源及接地(例如，將最外環接地)。
如本文中使用，術語「垂直」、「橫向」、「上」及「下」可指代鑑於圖中展示之定向，半導體晶粒總成中之特徵部之相對方向或位置。例如，「上」或「最上」可指代定位成比另一特徵部更靠近一頁面之頂部的一特徵部。然而，此等術語應廣義地解釋為包含具有其他定向(諸如倒轉或傾斜定向)之半導體裝置，其中取決於定向，頂部/底部、上/下、上方/下方、向上/向下及左/右可互換。
圖2係根據本技術之一實施例之一半導體裝置200 (例如，一半導體晶粒總成，其包含一3DI裝置或一晶粒堆疊封裝)之一平面圖。半導體裝置200可包含安裝於一基板(例如，另一晶粒或一PCB)上或連接至該基板之一或多個半導體晶粒。例如，半導體裝置200可包含一半導體晶粒202 (「晶粒202」)。在晶粒之間(諸如在晶粒202上方及/或下方)，半導體裝置200可包含經組態以直接連接且電耦合結構(例如，晶粒及/或PCB)之內部互連件218。在一些實施例中，內部互連件218可為源自接合或結合(舉例而言，諸如透過擴散接合或混合接合)柱、墊或互連結構之結構。
半導體裝置200可進一步包含沿一平面包圍/環繞內部互連件218之一周邊(periphery)或一周界(perimeter)之一或多個金屬(例如，銅、鋁、合金等)圍封殼。例如，半導體裝置200可包含至少一第一金屬圍封殼220 (「第一圍封殼220」)及一第二金屬圍封殼222 (「第二圍封殼222」)。在一些實施例中，第一圍封殼220可為包圍內部互連件218之一內部圍封殼，且第二圍封殼222可包圍第一圍封殼220，其等兩者皆沿一水平面。第一圍封殼220可巢套於第二圍封殼222內而彼此未直接接觸。
第一圍封殼220及第二圍封殼222各自可為形成周邊地包圍內部互連件218之一壁的一連續及固體金屬(諸如銅或焊料)結構。在一些實施例中，第一圍封殼220及第二圍封殼222 (例如，固體銅或焊料結構)可透過一接合程序(例如，擴散接合程序、熱壓縮接合、質量回焊(mass reflow)等)形成。在一些實施例中，第一圍封殼220及第二圍封殼222可各自具有小於或等於20 µm之一垂直尺寸或一高度。在一些實施例中，第一圍封殼220及第二圍封殼222可同心地配置。在一些實施例中，圍封殼可包含可透過熱壓縮接合或質量回焊而接合之焊料。
在晶粒之間或在一晶粒與一PCB基板之間，第一圍封殼220、第二圍封殼222或其等之一組合可用作一內部空間224 (「經圍封空間224」)之水平或周邊邊界(舉例而言，諸如沿一水平面標記周邊邊緣之垂直結構/平面)。經圍封空間224可為真空的或填充有惰性/特定氣體及/或其他介電材料，惟內部互連件218除外(例如，其中無任何囊封劑材料或底膠填充)。因此，第一圍封殼220及/或第二圍封殼222可將內部互連件218與圍封殼之相對側上之外部空間隔離。
在一些實施例中，一對圍封殼(例如，第一圍封殼220及第二圍封殼222)可係由一圍封殼分離空間226分離。例如，圍封殼分離空間226可為第一圍封殼220與第二圍封殼222之間的空間。如圖2中繪示，經圍封空間224可為第一圍封殼220內之空間，且圍封殼分離空間226可為包圍第一圍封殼220之一空間，其中第二圍封殼222形成周邊邊界。在一些實施例中，經圍封空間224可為由第二圍封殼222包圍之空間，且圍封殼分離空間226可為經圍封空間224之一外部周邊部分。
在一些實施例中，圍封殼(例如，最外圍封殼，諸如如圖2中繪示之第二圍封殼222)可係定位於距一晶粒周邊邊緣240之一邊緣偏移距離228 (例如，沿一水平方向量測之一距離)處。例如，邊緣偏移距離228可為晶粒周邊邊緣240與一第二外表面232 (例如，第二圍封殼222之外部周邊表面)之間之沿一水平方向的距離。在一些實施例中，最外圍封殼可經定位，使得其之一邊緣或一表面沿一垂直平面或線與晶粒周邊邊緣240共面或重合(例如，其中邊緣偏移距離228為0)。
在一些實施例中，圍封殼可分離達一圍封殼分離距離230。例如，圍封殼分離距離230可為一第二內表面234 (例如，第二圍封殼222之內部周邊表面)與一第一外表面236 (例如，第一圍封殼220之外部周邊表面)之間之沿一水平方向的距離。圍封殼分離距離230可對應於經圍封空間224。
半導體裝置200可具有圍封殼分離距離230，及經組態以提供一圍封電容242的圍封殼(例如，第一圍封殼220及第二圍封殼222)。圍封電容242可提供包圍內部互連件218及/或有效信號的電容。例如，圍封殼之一或多者(例如，第二圍封殼222或第一圍封殼220)可經連接至一第一電壓位準(例如，接地)，且其他圍封殼之一或多者(例如，第一圍封殼220或第二圍封殼222)可經連接至一第二電壓位準(例如，供應電壓)。此外，圍封電容242可係基於圍封殼分離距離230及/或圍封殼分離空間226中之氣體/真空/介電材料。
分離達圍封殼分離距離230且經組態以提供圍封電容242的圍封殼可改良射頻(RF)屏蔽且增加封裝級電容。圍封電容242亦可改良高電流突波裝置的電路完整性。
圍封殼可進一步提供半導體裝置之整體大小的減小。因為不需要底膠填充，所以接合線厚度可減小，而導致多晶粒堆疊之一非常低的封裝高度。此外，排除焊料(舉例而言，諸如源自Cu-Cu擴散接合之固體銅結構)的圍封殼藉由消除柱凸塊來提供製造成本的減低。再者，排除焊料的圍封殼藉由提供無焊料帽的清潔接頭來移除與焊料橋接、塌陷、匱乏、金屬間化合物(IMC)、電磁(EM)效應等相關聯的故障模式，而提供故障率的降低。
本發明亦因為封裝高度減小而提供製造成本及故障率之減低。圍封殼可保護且隔離內部互連件218免受環境因素(例如，水分、碎屑等)之影響，此消除對底膠填充(例如，奈米粒子底膠填充)之需要。因此，可基於使用圍封殼取代底膠填充而消除與底膠填充層壓或流動程序相關聯之成本及錯誤率(其等兩者隨著相鄰晶粒之間之空間減小而迅速增加)。此外，圍封殼提供滿足先前由底膠填充提供之機械、熱及電氣特質或優點的一接頭。
為闡釋性目的，圍封殼被展示為具有一矩形形狀、均勻厚度或寬度且與一對應晶粒之一形狀或輪廓同心。然而，應瞭解，圍封殼可為不同的。例如，圍封殼可具有一橢圓形形狀、一不規則或不對稱形狀或任何N邊多邊形形狀。再者，例如，圍封殼可在不同部分處具有變化厚度或寬度。再者，例如，圍封殼可相對於內部互連件218或其之一配置、晶粒之形狀或輪廓或其等之一組合偏移或非同心。
圖3係根據本技術之一實施例之沿圖2之線2--2取得之一半導體裝置之一橫截面視圖。半導體裝置200可包含安裝於一基板(例如，另一晶粒或一PCB)上或連接至該基板之一或多個半導體晶粒。例如，半導體裝置200可包含一晶粒堆疊302，晶粒堆疊302包含多個半導體晶粒304 (「晶粒304」)，其中第一圍封殼220及第二圍封殼222安置於一或多對相鄰晶粒之間。在一或多對相鄰晶粒之間，第一圍封殼220及/或第二圍封殼222可包圍經圍封空間306 (例如，圖2之經圍封空間224之例項)，且圍封殼分離空間308 (例如，圖2之圍封殼分離空間226之例項)可由第一圍封殼220及第二圍封殼222形成，其等兩者皆沿水平方向。沿垂直方向，對置相鄰晶粒之一第一邊界表面322及一第二邊界表面324可形成經圍封空間306及圍封殼分離空間308之邊界。經圍封空間306及/或圍封殼分離空間308可為真空的或填充有惰性/特定氣體或其他介電材料，如上文論述。
在一些實施例中，晶粒堆疊302可在晶粒304之一或多者中包含用於跨或穿過對應晶粒電耦合電路/組件之TSV。內部互連件218可(例如，透過直接接觸及/或透過另一電導體，諸如一跡線)連接至一或多個TSV，諸如內部TSV及/或周邊TSV。此外，一或多個TSV可將一或多個金屬圍封殼電連接至一電信號或電位(例如，電接地或供應電壓)。
例如，晶粒之一或多者可包含定位於對應晶粒之(若干)周邊部分上之一或多個第一周邊TSV 342及/或一或多個第二周邊TSV 344。第一周邊TSV 342及第二周邊TSV 344可用於跨晶粒電耦合第一圍封殼220及/或第二圍封殼222及/或將第一圍封殼220及/或第二圍封殼222電耦合至電信號/電位。如圖3中繪示，第一周邊TSV 342可跨一晶粒直接接觸並電耦合(舉例而言，諸如藉由穿過該晶粒而電連接)第一圍封殼220之例項，且第二周邊TSV 344可跨一晶粒直接接觸並電耦合第二圍封殼222之例項。再者，例如，晶粒之一或多者可包含定位於對應晶粒之一內部或中心部分上之一或多個內部TSV 346。如圖3中繪示，內部TSV 346可跨一晶粒直接接觸並電耦合內部互連件218之例項。
半導體裝置200可包含附接至一裝置基板362 (例如，PCB)或附接於裝置基板362上方之晶粒堆疊302。裝置基板362可包含用於電耦合至晶粒堆疊302之接合墊366。例如，半導體裝置200可包含直接接觸接合墊366及TSV之一或多者以將晶粒堆疊302電耦合至裝置基板362及/或其他電組件/電路的裝置互連件364 (例如，焊料)。在一些實施例中，裝置互連件364可嵌入於安置於晶粒堆疊302之一底表面與裝置基板362之一頂表面之間的底膠填充/囊封劑368 (「底膠填充368」)中。在一些實施例中，一或多個金屬圍封殼可取代底膠填充368，及/或內部互連件218可取代裝置互連件364。
在一些實施例中，TSV可將圍封殼電連接成組。例如，晶粒堆疊302可包含一第一晶粒372 (例如，最下方晶粒，諸如直接接觸裝置互連件364、底膠填充368等之晶粒)、附接於第一晶粒372正上方之一第二晶粒374、附接於第二晶粒374正上方之一第三晶粒376等。半導體裝置200可包含介於第一晶粒372與第二晶粒374之間之一第一層級圍封殼群組382 (例如，第一圍封殼220及第二圍封殼222)、一第二層級圍封殼群組384 (例如，一額外/第二組之第一圍封殼220及第二圍封殼222)等。
針對此配置，第一周邊TSV 342可沿一垂直方向連接一或多個內部圍封殼(例如，第一圍封殼220之例項)，且第二周邊TSV 344可沿一垂直方向連接一或多個外部/周邊圍封殼(例如，第二圍封殼222之例項)。在一些實施例中，晶粒堆疊中之全部垂直對應圍封殼可電連接在一起。例如，全部內部圍封殼可諸如使用第一周邊TSV 342電耦合在一起，及/或全部外部圍封殼可諸如使用第二周邊TSV 344電耦合在一起。
在一些實施例中，圍封殼可經對準用於垂直連接。例如，跨不同層級圍封殼群組之內部圍封殼之中心部分及/或周邊邊緣/部分/表面可沿一垂直線/平面重合。再者，例如，跨不同層級圍封殼群組之外部圍封殼之中心部分及/或周邊邊緣/部分/表面可沿一垂直線/平面重合。
使用電連接器(例如，跡線、接合墊366、裝置互連件364或其等之一組合)及TSV，圍封殼可各自連接至一電壓位準(例如，電接地、供應電壓等)。因此，圍封殼可用於跨一水平方向或跨晶粒提供圍封電容242。
另外，跨晶粒垂直地連接多個圍封殼(例如，沿如圖3中展示之一垂直方向，諸如將第一層級圍封殼群組382連接至第二層級圍封殼群組384)可進一步增加半導體裝置200之圍封電容242。使用周邊TSV垂直地連接多個圍封殼可增加能夠保持電荷之表面積及/或質量。因此，圍封電容242及封裝級電容可基於跨晶粒連接圍封殼而增加。因此，垂直連接之圍封殼(例如，圍封殼之一內部組及一外部組)可進一步改良RF屏蔽能力。
圖4係根據本技術之一實施例之一半導體裝置400 (例如，一半導體晶粒總成，其包含一3DI裝置或一晶粒堆疊封裝)之一平面圖。半導體裝置400可類似於圖2之半導體裝置200，但其具有填充金屬圍封殼之間之一圍封殼空間之介電材料。
例如，半導體裝置400可包含安裝於一基板(例如，另一晶粒或一PCB)上或連接至該基板之一或多個半導體晶粒，包含圖4中繪示之一半導體晶粒402 (「晶粒402」)。再者，例如，半導體裝置400可包含經組態以直接連接且電耦合不同結構(例如，晶粒及/或PCB)上之電路之內部互連件418 (例如，源自接合或結合(諸如透過擴散接合或混合接合)柱、墊或互連結構之結構)。
再者，例如，半導體裝置400可進一步包含各自形成沿一平面包圍/環繞內部互連件418之一周邊或一周界之一壁的一或多個連續及固體金屬(例如，銅、鋁、合金等)圍封殼(例如，一第一金屬圍封殼420 (「第一圍封殼420」)、一第二金屬圍封殼422 (「第二圍封殼422」)等)。在一些實施例中，第一圍封殼420可為周邊地包圍內部互連件418且巢套於第二圍封殼422內之一內部圍封殼(例如，一經巢套圍封殼)，第二圍封殼422周邊地包圍第一圍封殼420，其等兩者皆沿一水平面。在一些實施例中，第一圍封殼420及第二圍封殼422 (例如，固體銅結構)可透過一擴散接合程序形成。在一些實施例中，第一圍封殼420及第二圍封殼422可各自具有小於或等於40 µm之一垂直尺寸或一高度。在一些實施例中，第一圍封殼420及第二圍封殼422可同心地配置。
在晶粒之間或在一晶粒與一PCB基板之間，第一圍封殼420、第二圍封殼422或其等之一組合可用作一內部空間424 (「經圍封空間424」)之水平或周邊邊界(舉例而言，諸如沿一水平面標記周邊邊緣之垂直結構/平面)。經圍封空間424可為真空的或填充有惰性/特定氣體及/或其他介電材料，惟內部互連件418除外(例如，其中無任何囊封劑材料或底膠填充)。因此，第一圍封殼420及/或第二圍封殼422可將內部互連件418與圍封殼之相對側上之外部空間隔離。
在一些實施例中，圍封殼(例如，最外圍封殼，諸如如圖4中繪示之第二圍封殼422)可定位於距一晶粒周邊邊緣440之一邊緣偏移距離428 (例如，沿一水平方向量測之一距離)處。例如，邊緣偏移距離428可為晶粒周邊邊緣440與一第二外表面432 (例如，第二圍封殼422之外部周邊表面)之間之沿一水平方向之距離。在一些實施例中，最外圍封殼可經定位使得其之一邊緣或一表面沿一垂直平面或線與晶粒周邊邊緣440共面或重合(例如，其中邊緣偏移距離428為0)。
在一些實施例中，圍封殼可分離達一圍封殼分離距離430。例如，圍封殼分離距離430可為一第二內表面434 (例如，第二圍封殼422之內部周邊表面)與一第一外表面436 (例如，第一圍封殼420之外部周邊表面)之間之沿一水平方向之距離。圍封殼分離距離430可對應於經圍封空間424。
半導體裝置400可具有圍封殼分離距離430及經組態以提供一圍封電容442之圍封殼(例如，第一圍封殼420及第二圍封殼422)。圍封電容442可提供包圍內部互連件418及/或有效信號之電容。例如，圍封殼之一或多者(例如，第二圍封殼422或第一圍封殼420)可連接至一第一電壓位準(例如，接地)，且其他圍封殼之一或多者(例如，第一圍封殼420或第二圍封殼422)可連接至一第二電壓位準(例如，供應電壓)。
在一些實施例中，一對圍封殼(例如，第一圍封殼420及第二圍封殼422)可由一圍封殼分離空間(例如，第一圍封殼420與第二圍封殼422之間之空間)分離，該圍封殼分離空間由一介電材料426 (例如，可能由一施加電場極化之一電絕緣體)填充。如圖4中繪示，介電材料426可介於第一圍封殼420與第二圍封殼422之間且直接接觸第一圍封殼420及第二圍封殼422兩者。例如，介電材料426可介於第一外表面436與第二內表面434之間且直接接觸第一外表面436及第二內表面434。
連同圍封殼分離距離430，介電材料426可經組態以達成圍封電容442之一所要位準。與使圍封殼分離空間為真空或填充有氣體相比，第一圍封殼420與第二圍封殼422之間之介電材料426可增加圍封電容442。
分離達圍封殼分離距離430且填充有介電材料426用於提供圍封電容442之圍封殼可改良射頻(RF)屏蔽且增加封裝級電容。圍封電容442亦可改良高電流突波裝置之電路完整性。
圖5係根據本技術之一實施例之沿圖4之線4--4取得之一半導體裝置之一橫截面視圖。類似於圖2之半導體裝置200，半導體裝置400可包含安裝於一基板(例如，另一晶粒或一PCB)上或連接至該基板之一或多個半導體晶粒。例如，半導體裝置400可包含一晶粒堆疊502，晶粒堆疊502包含多個半導體晶粒504 (「晶粒504」)，其中第一圍封殼420及第二圍封殼422安置於一或多對相鄰晶粒之間。此外，半導體裝置400可包含經圍封空間506 (例如，圖4之經圍封空間424之例項)及介於一或多對相鄰晶粒之間之介電材料508 (例如，圖4之介電材料426之例項)。
在一些實施例中，晶粒堆疊502可在晶粒504之一或多者中包含用於跨或穿過對應晶粒電耦合電路/組件之TSV。例如，晶粒之一或多者可包含定位於對應晶粒之(若干)周邊部分上之一或多個第一周邊TSV 542及/或一或多個第二周邊TSV 544。如圖5中繪示，第一周邊TSV 542可跨一晶粒直接接觸並電耦合第一圍封殼420之例項，且第二周邊TSV 544可跨一晶粒直接接觸並電耦合第二圍封殼422之例項。再者，例如，晶粒之一或多者可包含定位於對應晶粒之一內部或中心部分上之一或多個內部TSV 546。內部TSV 546可跨一晶粒直接接觸並電耦合內部互連件418之例項。
半導體裝置400可包含附接至一裝置基板562 (例如，PCB)或附接於裝置基板562上方之晶粒堆疊502。裝置基板562可包含用於電耦合至晶粒堆疊502之接合墊566。例如，半導體裝置400可包含直接接觸接合墊566及TSV之一或多者以將晶粒堆疊502電耦合至裝置基板562及/或其他電組件/電路之裝置互連件564 (例如，焊料)。在一些實施例中，裝置互連件564可嵌入於安置於晶粒堆疊502之一底表面與裝置基板562之一頂表面之間的底膠填充/囊封劑568 (「底膠填充568」)中。在一些實施例中，一或多個金屬圍封殼可取代底膠填充568，及/或內部互連件418可取代裝置互連件564。
使用電連接器(例如，跡線、接合墊566、裝置互連件564或其等之一組合)及TSV，圍封殼可各自連接至一電壓位準(例如，電接地、供應電壓等)。因此，圍封殼可用於跨一水平方向或跨晶粒提供圍封電容442。
另外，跨晶粒(例如，沿如圖5中展示之一垂直方向)垂直地連接多個圍封殼可進一步增加半導體裝置400之圍封電容442。使用周邊TSV垂直地連接多個圍封殼可增加能夠保持電荷之表面積及/或質量。因此，圍封電容442及封裝級電容可基於跨晶粒連接圍封殼而增加。因此，垂直連接之圍封殼(例如，圍封殼之一內部組及一外部組)可進一步改良RF屏蔽能力。
圖6係根據本技術之一實施例之一半導體裝置600 (例如，一半導體晶粒總成，其包含一3DI裝置或一晶粒堆疊封裝)之一平面圖。半導體裝置600可類似於圖2之半導體裝置200及/或圖4之半導體裝置400，但其具有巢套於一外部金屬圍封殼內之多個非重疊內部金屬圍封殼。
例如，半導體裝置600可包含經安裝於一基板(例如，另一晶粒或一PCB)上或經連接至該基板之一或多個半導體晶粒，包含圖6中繪示之一半導體晶粒602 (「晶粒602」)。再者，例如，半導體裝置600可包含內部互連件，諸如源自接合或結合(諸如透過擴散接合或混合接合)柱、墊或互連結構之結構。在一些實施例中，半導體裝置600可包含經組態以直接連接且電耦合不同結構(例如，晶粒及/或PCB)上之電路的各別互連件組，諸如一第一互連件組604及一第二互連件組606。
再者，例如，半導體裝置600可進一步包含各自形成沿一平面(例如，水平面)包圍/環繞互連件及/或其他圍封殼之一周邊或一周界之一壁的一或多個連續及固體金屬(例如，銅、鋁、合金等)圍封殼。在一些實施例中，半導體裝置600可包含經巢套於一外部圍繞金屬圍封殼(例如，一外部圍封殼616)內的多個非重疊內部金屬圍封殼(例如，一第一內部圍封殼612及一第二內部圍封殼614)。第一內部圍封殼612可包圍/環繞第一互連件組604，且第二內部圍封殼614可包圍/環繞第二互連件組606。外部圍封殼616可包圍/環繞巢套於其中之內部圍封殼(例如，第一內部圍封殼612及第二內部圍封殼614)及圍封/包圍於其中之互連件組(例如，第一互連件組604及第二互連件組606)。
在晶粒之間或在一晶粒與一PCB基板之間，圍封殼可用作經圍封空間之水平或周邊邊界(舉例而言，諸如沿一水平面標記周邊邊緣之垂直結構/平面)。外部圍封殼可環繞一空間，且內部圍封殼中可環繞各別及排他空間。例如，外部圍封殼616可環繞一外部經圍封空間626。第一內部圍封殼612可環繞一第一內部空間622，且第二內部圍封殼614可環繞與第一內部空間622分離且排他之一第二內部空間624。第一內部空間622及第二內部空間624兩者可為外部經圍封空間626內的空間/部分。
經圍封空間可為真空的或經填充有惰性/特定氣體(例如，其中無任何囊封劑材料或底膠填充)。在一些實施例中，圍封殼之間之經圍封空間的部分可經填充有介電材料(例如，圖4之介電材料426)。因此，圍封殼可將互連件與結構之相對側上的外部空間隔離。
在一些實施例中，內部圍封殼可為分離的，而無任何直接接觸。在一些實施例中，內部圍封殼可經電連接在一起，或共用/重疊其中之部分。在一些實施例中，圍封殼(例如，固體銅結構)可係透過一擴散接合程序形成。在一些實施例中，圍封殼可各自具有小於或等於60 µm之一垂直尺寸或一高度。
在一些實施例中，外部圍封殼616可定位成與晶粒之一周邊邊緣/表面共面。在一些實施例中，外部圍封殼616可自周邊邊緣/表面水平偏移，如上文論述。
內部圍封殼可與外部圍封殼分離達類似於上文論述之圍封殼分離距離之一或多個圍封殼分離距離。例如，第一內部圍封殼612可對應於一第一分離距離且第二內部圍封殼614可對應於一第二分離距離，其等兩者皆相對於外部圍封殼616。
半導體裝置600可具有圍封殼分離距離及經組態以提供圍封電容642之圍封殼。圍封電容642可提供各自包圍一組內部互連件及/或有效信號之電容。與分離距離、介電填料等一起，用於圍封殼之電連接可經組態以達成包圍各組有效信號之圍封電容642之所要位準。例如，圍封殼之一或多者(例如，外部圍封殼616)可連接至一第一電壓位準(例如，接地)，且其他圍封殼之一或多者(例如，內部圍封殼)可連接至一不同電壓位準(例如，供應電壓或不同電壓位準)。環繞有效信號/電路之所得電容可改良射頻(RF)屏蔽且增加封裝級電容。圍封電容642亦可改良高電流突波裝置之電路完整性。
圖7係根據本技術之一實施例之沿圖6之線6--6取得之一半導體裝置之一橫截面視圖。類似於圖2之半導體裝置200及/或圖4之半導體裝置400，半導體裝置600可包含安裝於一基板(例如，另一晶粒或一PCB)上或連接至該基板之一或多個半導體晶粒。例如，半導體裝置600可包含一晶粒堆疊702，晶粒堆疊702包含多個半導體晶粒704 (「晶粒704」)，其中圍封殼(諸如第一內部圍封殼712 (例如，圖6之第一內部圍封殼612之例項)、第二內部圍封殼714 (例如，圖6之第二內部圍封殼614之例項)、外部圍封殼716 (例如，圖6之外部圍封殼616之例項)等)安置於一或多對相鄰晶粒之間。此外，半導體裝置600可包含介於一或多對相鄰晶粒之間之經圍封空間，諸如第一內部空間722 (例如，圖6之第一內部空間622之例項)、第二內部空間724 (圖6之第二內部空間624之例項)、外部經圍封空間726 (圖6之外部經圍封空間626之例項)等。
在一些實施例中，晶粒堆疊702可在晶粒704之一或多者中包含用於跨或穿過對應晶粒電耦合電路/組件之TSV。例如，晶粒之一或多者可包含一或多個第一圍封殼TSV 742、一或多個第二圍封殼TSV 744、一或多個外部圍封殼TSV 746、一或多個互連件TSV等。第一圍封殼TSV 742可跨一對應晶粒直接接觸並電耦合相鄰對之第一內部圍封殼712，第二圍封殼TSV 744可跨一對應晶粒直接接觸並電耦合相鄰對之第二內部圍封殼714，且外部圍封殼TSV 746可跨一對應晶粒直接接觸並電耦合相鄰對之外部圍封殼716。類似地，互連件TSV可跨一晶粒直接接觸並電耦合對應組之內部互連件。
類似於上文論述之半導體裝置，半導體裝置600可包含附接至一裝置基板(例如，PCB)或附接於該裝置基板上方之晶粒堆疊702。裝置基板可包含用於電耦合至晶粒堆疊702之接合墊、裝置互連件(例如，焊料)。在一些實施例中，裝置互連件可嵌入於安置於晶粒堆疊702之一底表面與裝置基板之一頂表面之間的底膠填充/囊封劑中。在一些實施例中，一或多個金屬圍封殼可取代底膠填充，及/或內部互連件可取代裝置互連件。
使用電連接器(例如，跡線、接合墊、裝置互連件或其等之一組合)及TSV，圍封殼可各自連接至一電壓位準(例如，電接地、供應電壓等)。因此，圍封殼可用於跨一水平方向或跨晶粒提供圍封電容642。
另外，跨晶粒(例如，沿如圖5中展示之一垂直方向)垂直地連接多個圍封殼可進一步增加半導體裝置400之圍封電容442。使用周邊TSV垂直地連接多個圍封殼可增加能夠保持電荷之表面積及/或質量。因此，圍封電容442及封裝級電容可基於跨晶粒連接圍封殼而增加。因此，垂直連接之圍封殼(例如，圍封殼之一內部組及一外部組)可進一步改良RF屏蔽能力。
圖8至圖11係繪示根據本技術之一實施例之在一製造方法中之選定階段處的一半導體裝置之橫截面視圖。如圖8中繪示，方法可包含用於提供一第一晶粒802之一階段。第一晶粒802可包含在一第一晶粒底表面下方突出之第一晶粒互連件804 (舉例而言，諸如內部互連件之一部分之用於提供至第一晶粒802內之電路之電連接的固體金屬結構)。第一晶粒802可進一步包含一或多個第一晶粒內部圍封殼(例如，一第一晶粒內部圍封殼810)及一第一晶粒外部圍封殼811。第一晶粒內部圍封殼及第一晶粒外部圍封殼811各自可為諸如金屬圍封殼結構之一部分之一固體金屬結構。第一晶粒內部圍封殼可各自沿一水平面環繞對應晶粒互連件(例如，第一晶粒互連件804)之一周界，且第一晶粒外部圍封殼811可沿一水平面環繞第一晶粒內部圍封殼810。
可使用一各別製造程序(例如，晶圓或晶粒級製造程序)來製造具有第一晶粒互連件804及晶粒圍封殼之第一晶粒802。該各別製造程序可根據一突出部量測值812 (例如，金屬結構之一高度，諸如在晶粒底表面與第一晶粒互連件804及晶粒圍封殼之一遠端部分之間量測之一長度)產生第一晶粒互連件804及晶粒圍封殼。在一些實施例中，突出部量測值812可包含小於20 µm之一距離。根據突出部量測值812，第一晶粒互連件804及晶粒圍封殼之遠端部分(例如，相對於晶粒底表面)可沿平行於晶粒底表面之一水平面共面。在一些實施例中，圍封殼可包含可透過熱壓縮接合或質量回焊接合之焊料。
在一些實施例中，各別製造程序可包含形成直接接觸互連件及/或圍封殼之一或多個TSV (例如，內部TSV及/或周邊TSV)。在一些實施例中，可將一介電填料814 (例如，介電環氧樹脂或膏)施覆於內部圍封殼之一或多者與外部圍封殼之間、內部圍封殼之間等。
如圖9中繪示，方法可包含用於提供一基板906 (例如，一PCB或另一晶粒，諸如第二晶粒、內部晶粒之一者等)之一階段。基板906可包含在一基板頂表面上方突出之基板互連件904 (舉例而言，諸如內部互連件之一部分之用於提供至基板906之電連接的固體金屬結構)。基板906可進一步包含一或多個基板內部圍封殼(例如，一基板內部圍封殼910)及一基板外部圍封殼911。基板內部圍封殼及基板外部圍封殼911各自可為諸如金屬圍封殼結構之一部分之一固體金屬結構。基板內部圍封殼可各自沿一水平面環繞對應基板互連件(例如，基板互連件904)之一周界，且基板外部圍封殼911可沿一水平面環繞基板內部圍封殼。
可使用一各別製造程序(例如，晶圓或晶粒級製造程序或用於製造一印刷電路板之一程序)製造具有基板互連件904及基板圍封殼之基板906。類似於圖8中繪示之階段，該各別製造程序可根據一突出部量測值912 (例如，金屬結構之一高度，諸如在第二邊界表面與基板互連件904及基板圍封殼之一遠端部分之間量測之一長度)產生基板互連件904及基板圍封殼。在一些實施例中，突出部量測值912可包含小於20 µm之一距離。根據突出部量測值912，基板互連件904及基板圍封殼之遠端部分(例如，相對於基板頂表面)可沿平行於基板頂表面之一水平面共面。在一些實施例中，圍封殼可包含可透過熱壓縮接合或質量回焊接合之焊料。
在一些實施例中，各別製造程序可包含形成直接接觸互連件及/或圍封殼之一或多個TSV (例如，內部TSV及/或周邊TSV)。在一些實施例中，可將一介電填料914 (例如，介電環氧樹脂或膏)施覆於內部圍封殼之一或多者與外部圍封殼之間、內部圍封殼之間等。
如圖10中繪示，方法可包含用於對準基板906及晶粒802之一階段。基板906及晶粒802可基於其對準參考部分(例如，一中心部分、一周邊邊緣或表面等)沿一線或一平面(例如，圖10之一垂直線或平面)對準。結構可經對準使得晶粒圍封殼(例如，第一晶粒內部圍封殼810及第一晶粒外部圍封殼811)及基板圍封殼(例如，基板內部圍封殼910及基板外部圍封殼911)沿一線或一平面(例如，一垂直線或平面)對準。此外，結構可經對準使得晶粒圍封殼及基板圍封殼彼此直接接觸。第一晶粒互連件804及基板互連件904可類似地對準。
在一些實施例中，可在對準結構之前硬化或設定圍封殼之間之介電材料。在一些實施例中，可在對準結構之後在圍封殼之間施覆介電材料。
如圖11中繪示，方法可包含用於接合金屬結構(例如，將晶粒圍封殼接合至基板圍封殼及/或將第一晶粒互連件804接合至基板互連件904)之一階段。例如，圖11可表示一擴散接合程序1100 (例如，Cu-Cu擴散接合)，其包含用於基於固態擴散而結合金屬之一固態焊接程序(例如，其在具有或不具有將結構推至一起之壓力/力之情況下利用在本質上低於結構之熔點之溫度下的聚結)。擴散接合程序1100可包含產生一真空條件或用惰性氣體填充空間(例如，經圍封空間)、加熱金屬表面、將金屬結構壓在一起或其等之一組合。
基於接合階段，金屬結構可接合或熔合且形成一連續結構。例如，晶粒圍封殼及基板圍封殼可經接合以形成上文論述之各種內部及外部圍封殼。再者，例如，可接合第一晶粒互連件804及基板互連件904以形成上文論述之內部互連件。
將晶粒圍封殼擴散接合至基板圍封殼(例如，Cu-Cu擴散接合)及將第一晶粒互連件804與基板互連件904擴散接合(例如，Cu-Cu擴散接合)提供減少的製造故障及降低的成本。擴散接合程序可消除焊料，藉此減少與焊接程序相關聯之任何潛在故障且降低成本。此外，可使用一個接合程序接合互連件及圍封殼，此可進一步簡化製造程序。
在一些實施例中，接合階段可包含硬化/固化圍封殼之間之介電材料。例如，用於接合階段之條件/環境可包含固化介電材料所需之設定一溫度、施用一光或一化學試劑、等待等。在一些實施例中，可在接合結構之後(例如，透過在一稍後階段填充之一施覆埠/孔)將介電材料施覆於圍封殼之間且進行固化。
圖12係繪示根據本技術之一實施例之製造一半導體裝置的一例示性方法1200 (「方法1200」)之一流程圖。例如，方法1200可經實施以製造圖2及圖3之半導體裝置200、圖4及圖5之半導體裝置400及/或圖6及圖7之半導體裝置600。再者，例如，方法1200可包含圖8至圖11中繪示之階段。
方法1200可包含提供一或多個半導體晶粒(例如，圖2至圖7中繪示之一或多個晶粒)，如方塊1202處繪示。提供半導體晶粒可對應於圖8中繪示之階段。經提供晶粒可包含晶粒互連件(例如，圖8之第一晶粒互連件804)及自晶粒底表面向下突出之晶粒圍封殼(例如，圖8之內部圍封殼810或圖8之外部圍封殼811)。晶粒圍封殼可在晶粒底表面上或沿晶粒底表面周邊地包圍晶粒互連件。經提供晶粒可進一步具有與晶粒圍封殼之底部或遠端部分或表面共面之晶粒互連件之底部或遠端部分或表面。例如，晶粒互連件及晶粒圍封殼之底部或遠端部分可沿平行於晶粒底表面且自晶粒底表面垂直偏移達圖8之突出部量測值812的一水平面共面。
在一些實施例中，晶粒圍封殼可包含銅、鋁、鎳、其他金屬或其等之一組合。在一些實施例中，晶粒圍封殼可包含直接接觸晶粒底表面或直接附接至一金屬壁結構之一遠端表面或部分的焊料。在一些實施例中，晶粒圍封殼之各者可電連接至一信號或一電壓位準(舉例而言，諸如一電壓源或接地)。
可使用一各別製造程序製造或形成晶粒，如方塊1220處繪示。例如，晶粒製造程序可包含晶圓級處理，諸如用於形成積體電路之一摻雜程序及用於分離個別晶粒之一單粒化程序。再者，例如，晶粒製造程序可包含形成TSV。
方法1200可進一步包含提供一基板(例如，圖9之基板906)，如方塊1204處繪示。提供基板可對應於圖9中繪示之階段。經提供基板可包含基板互連件(例如，圖9之基板互連件904)及自基板頂表面向上突出之基板圍封殼(例如，圖9之內部圍封殼910及圖9之外部圍封殼911)。基板圍封殼可在基板頂表面上或沿基板頂表面周邊地包圍基板互連件。經提供基板可進一步具有與基板圍封殼之頂部或遠端部分或表面共面之基板互連件之頂部或遠端部分或表面。例如，基板互連件及基板圍封殼之頂部或遠端部分可沿平行於基板頂表面且自基板頂表面垂直偏移達圖9之突出部量測值912的一水平面共面。
在一些實施例中，基板圍封殼可包含銅、鋁、鎳、其他金屬或其等之一組合。在一些實施例中，基板圍封殼可包含直接接觸基板頂表面或直接附接至一金屬壁結構之一遠端表面或部分的焊料。在一些實施例中，基板圍封殼之各者可電連接至一信號或一電壓位準(舉例而言，諸如一電壓源或接地)。
可使用一各別製造程序製造或形成基板，如方塊1240處繪示。例如，(例如，用於製造另一晶粒之)基板製造程序可包含類似於方塊1220所繪示之程序之晶圓級處理。再者，例如，(例如，用於製造PCB基板之)基板製造程序可包含焊料遮罩塑形、跡線形成、平坦化等。再者，例如，基板製造程序可包含形成TSV。
方法1200可進一步包含對準結構(例如，晶粒及基板)，如方塊1206處繪示。對準結構可對應於圖10中繪示之階段。例如，對準程序可將晶粒對準於基板上方，其中各晶粒互連件之一部分沿垂直線與各基板互連件之一對應部分重合及/或晶粒圍封殼之一部分沿垂直線與基板圍封殼重合。再者，例如，對準程序可將晶粒對準於基板上方，其中晶粒圍封殼直接接觸基板圍封殼。
方法1200可進一步包含接合結構(例如，將晶粒互連件接合至基板互連件及/或將晶粒圍封殼接合至基板圍封殼)，如方塊1208處繪示。接合程序可對應於圖11中繪示之階段。接合程序可包含控制結構之一或多者之溫度(例如，加熱以接合且接著冷卻以固化經結合結構)、對結構施加壓力或其等之一組合。例如，接合程序可包含如方塊1212處所繪示之擴散接合(例如，熱壓縮接合或TCB)及/或如方塊1214處所繪示之回焊焊料(例如，在施用焊料之情況中，質量回焊)。
透過接合程序，可形成圍封殼、經圍封空間、互連件等。由於金屬(例如，銅、焊料等)充分阻擋水分及其他碎屑，故製造程序不再需要底膠填充。因而，接合程序可接合結構而不需要經圍封空間中或基板頂表面與晶粒底表面之間之空間中的任何底膠填充。此外，上文描述之接合程序可消除氧化物至氧化物接合(例如，針對混合接合)及/或對晶圓表面條件(例如，表面粗糙度控制)之要求，此可導致較低製造成本及錯誤。
圖13係繪示根據本技術之實施例之併有一半導體裝置之一系統之一方塊圖。具有上文關於圖2至圖12描述之特徵之半導體裝置之任一者可併入至無數更大及/或更複雜系統之任何者中，該等系統之一代表性實例係圖13中示意性地展示之系統1390。系統1390可包含一處理器1392、一記憶體1394 (例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置1396及/或其他子系統或組件1398。上文關於圖2至圖12描述之半導體總成、裝置及裝置封裝可包含於圖13中展示之元件之任何者中。所得系統1390可經組態以執行各種各樣的適合運算、處理、儲存、感測、成像及/或其他功能之任何者。因此，系統1390之代表性實例包含但不限於電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路設備、手持式裝置(例如，掌上型電腦、可穿戴電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等)、平板電腦、多處理器系統、基於處理器之電子器件或可程式化消費性電子器件、網路電腦及迷你電腦。系統1390之額外代表性實例包含燈、相機、車輛等。關於此等及其他實例，系統1390可容置於一單一單元中或分佈在多個互連單元上(例如，透過一通信網路)。因此，系統1390之組件可包含本地及/或遠端記憶體儲存裝置及各種各樣的適合電腦可讀媒體之任何者。
從前文將瞭解，本文中已為繪示之目的描述本技術之特定實施例，但可在不脫離本發明之情況下進行各種修改。另外，在特定實施例之內容背景中描述之本發明之某些態樣可在其他實施例中組合或消除。此外，雖然已在特定實施例之內容背景中描述與該等實施例相關聯之優點，但其他實施例亦可展現此等優點。並非全部實施例皆必需展現此等優點以落於本發明之範疇內。因此，本發明及相關聯技術可涵蓋本文中未明確展示或描述之其他實施例。
100‧‧‧半導體裝置
102‧‧‧晶粒
104‧‧‧晶粒互連件
106‧‧‧基板結構
108‧‧‧基板互連件
110‧‧‧底膠填充
114‧‧‧空隙
200‧‧‧半導體裝置
202‧‧‧半導體晶粒/晶粒
218‧‧‧內部互連件
220‧‧‧第一金屬圍封殼/第一圍封殼
222‧‧‧第二金屬圍封殼/第二圍封殼
224‧‧‧內部空間/經圍封空間
226‧‧‧圍封殼分離空間
228‧‧‧邊緣偏移距離
230‧‧‧圍封殼分離距離
232‧‧‧第二外表面
234‧‧‧第二內表面
236‧‧‧第一外表面
240‧‧‧晶粒周邊邊緣
242‧‧‧圍封電容
302‧‧‧晶粒堆疊
304‧‧‧半導體晶粒/晶粒
306‧‧‧經圍封空間
308‧‧‧圍封殼分離空間
322‧‧‧第一邊界表面
324‧‧‧第二邊界表面
342‧‧‧第一周邊矽穿孔(TSV)
344‧‧‧第二周邊矽穿孔(TSV)
346‧‧‧內部矽穿孔(TSV)
362‧‧‧裝置基板
364‧‧‧裝置互連件
366‧‧‧接合墊
368‧‧‧底膠填充/囊封劑
372‧‧‧第一晶粒
374‧‧‧第二晶粒
376‧‧‧第三晶粒
382‧‧‧第一層級圍封殼群組
384‧‧‧第二層級圍封殼群組
400‧‧‧半導體裝置
402‧‧‧半導體晶粒/晶粒
418‧‧‧內部互連件
420‧‧‧第一金屬圍封殼/第一圍封殼
422‧‧‧第二金屬圍封殼/第二圍封殼
424‧‧‧內部空間/經圍封空間
426‧‧‧介電材料
428‧‧‧邊緣偏移距離
430‧‧‧圍封殼分離距離
432‧‧‧第二外表面
434‧‧‧第二內表面
436‧‧‧第一外表面
440‧‧‧晶粒周邊邊緣
442‧‧‧圍封電容
502‧‧‧晶粒堆疊
504‧‧‧半導體晶粒/晶粒
506‧‧‧經圍封空間
508‧‧‧介電材料
542‧‧‧第一周邊矽穿孔(TSV)
544‧‧‧第二周邊矽穿孔(TSV)
546‧‧‧內部矽穿孔(TSV)
562‧‧‧裝置基板
564‧‧‧裝置互連件
566‧‧‧接合墊
568‧‧‧底膠填充/囊封劑
600‧‧‧半導體裝置
602‧‧‧半導體晶粒/晶粒
604‧‧‧第一互連件組
606‧‧‧第二互連件組
612‧‧‧第一內部圍封殼
614‧‧‧第二內部圍封殼
616‧‧‧外部圍封殼
622‧‧‧第一內部空間
624‧‧‧第二內部空間
626‧‧‧外部經圍封空間
702‧‧‧晶粒堆疊
704‧‧‧半導體晶粒/晶粒
712‧‧‧第一內部圍封殼
714‧‧‧第二內部圍封殼
716‧‧‧外部圍封殼
722‧‧‧第一內部空間
724‧‧‧第二內部空間
726‧‧‧外部經圍封空間
742‧‧‧第一圍封殼矽穿孔(TSV)
744‧‧‧第二圍封殼矽穿孔(TSV)
746‧‧‧外部圍封殼矽穿孔(TSV)
802‧‧‧第一晶粒
804‧‧‧第一晶粒互連件
810‧‧‧第一晶粒內部圍封殼
811‧‧‧第一晶粒外部圍封殼
812‧‧‧突出部量測值
814‧‧‧介電填料
904‧‧‧基板互連件
906‧‧‧基板
910‧‧‧基板內部圍封殼
911‧‧‧基板外部圍封殼
912‧‧‧突出部量測值
914‧‧‧介電填料
1100‧‧‧擴散接合程序
1200‧‧‧方法
1202‧‧‧方塊
1204‧‧‧方塊
1206‧‧‧方塊
1208‧‧‧方塊
1212‧‧‧方塊
1214‧‧‧方塊
1220‧‧‧方塊
1240‧‧‧方塊
1390‧‧‧系統
1392‧‧‧處理器
1394‧‧‧記憶體
1396‧‧‧輸入/輸出裝置
1398‧‧‧其他子系統或組件
圖1係一半導體裝置之一橫截面視圖。
圖2係根據本技術之一實施例之一半導體裝置之一平面圖。
圖3係根據本技術之一實施例之沿圖2之線2--2取得之一半導體裝置之一橫截面視圖。
圖4係根據本技術之一實施例之一半導體裝置之一平面圖。
圖5係根據本技術之一實施例之沿圖4之線4--4取得之一半導體裝置之一橫截面視圖。
圖6係根據本技術之一實施例之一半導體裝置之一平面圖。
圖7係根據本技術之一實施例之沿圖6之線6--6取得之一半導體裝置之一橫截面視圖。
圖8至圖11係繪示根據本技術之一實施例之在一製造方法中之選定階段處的一半導體裝置之橫截面視圖。
圖12係繪示根據本技術之一實施例之製造一半導體裝置的一例示性方法之一流程圖。
圖13係繪示根據本技術之實施例之併有一半導體裝置的一系統之一方塊圖。

Claims (20)

  1. 一種半導體裝置，其包括： 一第一晶粒； 一第二晶粒，其經附接於該第一晶粒上方； 一第一金屬圍封殼，其直接接觸該第一晶粒及該第二晶粒且在該第一晶粒與該第二晶粒之間垂直延伸，其中該第一金屬圍封殼周邊地環繞一組一或多個內部互連件； 一第二金屬圍封殼，其直接接觸該第一晶粒及該第二晶粒且在該第一晶粒與該第二晶粒之間垂直延伸，其中該第二金屬圍封殼周邊地環繞該第一金屬圍封殼而未直接接觸該第一金屬圍封殼； 一第一圍封殼連接器，其直接接觸該第一金屬圍封殼，其中該第一圍封殼連接器用於將該第一金屬圍封殼電連接至一第一電壓位準；及 一第二圍封殼連接器，其直接接觸該第二金屬圍封殼，其中該第二圍封殼連接器用於將該第二金屬圍封殼電連接至一第二電壓位準； 其中該第一金屬圍封殼、該第二金屬圍封殼、該第一圍封殼連接器及該第二圍封殼連接器經組態以提供一圍封電容。
  2. 如請求項1之半導體裝置，其中該第一金屬圍封殼及該第二金屬圍封殼分離達一圍封殼分離距離，其中該圍封殼分離距離與該圍封電容相關。
  3. 如請求項2之半導體裝置，其中該第一金屬圍封殼及該第二金屬圍封殼形成該第一晶粒與該第二晶粒之間之一圍封殼分離空間，其中該圍封殼分離空間係真空的或經填充有一氣體。
  4. 如請求項2之半導體裝置，其中該第一金屬圍封殼及該第二金屬圍封殼形成該第一晶粒與該第二晶粒之間之一圍封殼分離空間，其中該圍封殼分離空間經填充有一介電材料。
  5. 如請求項4之半導體裝置，其中該介電材料與該圍封電容相關以進一步增加該圍封電容。
  6. 如請求項2之半導體裝置，其中該第一金屬圍封殼及該第二金屬圍封殼係沿一水平面同心地配置，其中該圍封殼分離距離在該第一金屬圍封殼與該第二金屬圍封殼之間係均勻的。
  7. 如請求項1之半導體裝置，其中： 該第二金屬圍封殼係環繞一整體經圍封空間之一外部圍封殼； 該第一金屬圍封殼係環繞該整體經圍封空間內之一第一內部空間之一第一內部圍封殼；及 該半導體裝置進一步包括： 一第二內部圍封殼，其直接接觸該第一晶粒及該第二晶粒且在該第一晶粒與該第二晶粒之間垂直延伸，其中該第二內部圍封殼周邊地環繞另一組互連件及在該整體經圍封空間內且與該第一內部空間互斥之一第二內部空間。
  8. 如請求項1之半導體裝置，進一步包括： 一第三晶粒，其經附接於該第二晶粒上方； 一上部層級內部圍封殼，其直接接觸該第二晶粒及該第三晶粒且在該第二晶粒與該第三晶粒之間垂直延伸；及 一上部層級外部圍封殼，其直接接觸該第二晶粒及該第三晶粒且在該第二晶粒與該第三晶粒之間垂直延伸，其中該上部層級外部圍封殼周邊地環繞該上部層級內部圍封殼； 其中： 該第一金屬圍封殼係一下部層級內部圍封殼； 該第二金屬圍封殼係一下部層級外部圍封殼； 該第一圍封殼連接器包含延伸穿過該第二晶粒且直接接觸該下部層級內部圍封殼及該上部層級內部圍封殼的一或多個第一矽穿孔(TSV)；及 該第二圍封殼連接器包含延伸穿過該第二晶粒且直接接觸該下部層級外部圍封殼及該上部層級外部圍封殼的一或多個第二TSV。
  9. 如請求項1之半導體裝置，其中： 該上部層級內部圍封殼及該下部層級內部圍封殼之各者上的一或多個點、表面或部分係沿一第一垂直線重合；及 該上部層級外部圍封殼及該下部層級外部圍封殼之各者上的一或多個點、表面或部分係沿一第二垂直線重合。
  10. 如請求項1之半導體裝置，其中： 該第二金屬圍封殼係沿一水平方向之一最外圍封殼；及 該第二金屬圍封殼經電耦合至電接地。
  11. 一種製造一半導體裝置之方法，其包括： 提供一晶粒，該晶粒包含晶粒互連件、一晶粒內部圍封殼及一晶粒外部圍封殼，其中： 該等晶粒互連件自一晶粒底表面突出， 該晶粒內部圍封殼自該晶粒底表面突出且周邊地包圍該等晶粒互連件，及 該晶粒外部圍封殼自該晶粒底表面突出且周邊地包圍該晶粒內部圍封殼而未直接接觸該晶粒內部圍封殼； 提供一基板，該基板包含基板互連件、一基板內部圍封殼，及一基板外部圍封殼，其中： 該等基板互連件自一基板頂表面突出， 該基板內部圍封殼自該基板頂表面突出且周邊地包圍該等基板互連件，及 該基板外部圍封殼自該基板頂表面突出且周邊地包圍該基板內部圍封殼而未直接接觸該基板內部圍封殼；及 將該等基板互連件接合至該等晶粒互連件、將該基板內部圍封殼接合至該晶粒內部圍封殼，且將該基板外部圍封殼接合至該晶粒外部圍封殼。
  12. 如請求項11之方法，進一步包括： 將該晶粒內部圍封殼、該基板內部圍封殼或其等之一組合連接至一第一電壓位準；及 將該晶粒外部圍封殼、該基板外部圍封殼或其等之一組合連接至一第二電壓位準以提供一圍封電容。
  13. 如請求項12之方法，其中該第二電壓位準係一電接地。
  14. 如請求項11之方法，其中： 提供該晶粒包含：提供具有沿一水平方向分離達一圍封殼分離距離之該晶粒內部圍封殼及該晶粒外部圍封殼的該晶粒；及 提供該基板包含：提供具有沿該水平方向分離達該圍封殼分離距離之該基板內部圍封殼及該基板外部圍封殼的該基板。
  15. 如請求項11之方法，其中： 提供該晶粒包含提供一第一晶粒； 提供該基板包含提供一第二晶粒； 將該基板內部圍封殼接合至該晶粒內部圍封殼包含：形成包括在該第一晶粒與該第二晶粒之間延伸之一固體金屬結構之一第一金屬圍封殼；及 將該基板外部圍封殼接合至該晶粒外部圍封殼包含：形成包括在該第一晶粒與該第二晶粒之間延伸之一固體金屬結構之一第二金屬圍封殼。
  16. 如請求項15之方法，其中形成該第一金屬圍封殼及該第二金屬圍封殼包含：形成包圍一圍封殼分離空間之該第一金屬圍封殼及該第二金屬圍封殼，其中該圍封殼分離空間係真空的或經填充有一氣體。
  17. 如請求項11之方法，進一步包括： 在該晶粒內部圍封殼與該晶粒外部圍封殼之間，施覆一第一組之一介電材料；及 在該基板內部圍封殼與該基板外部圍封殼之間，施覆一第二組之該介電材料。
  18. 如請求項17之方法，進一步包括在接合之前，固化該第一組及該第二組之介電材料。
  19. 如請求項17之方法，其中接合包含固化該第一組及該第二組之介電材料。
  20. 一種包含具有至少兩個晶粒之一晶粒堆疊之半導體裝置，其包括： 複數個互連件，其等電耦合該晶粒堆疊之兩個或更多個相鄰晶粒； 一第一金屬密封部件及一第二金屬密封部件，其等經安置於一對相鄰晶粒之間，其中該第一金屬密封部件圍封一或多個互連件且經巢套於該第二金屬密封部件內； 一第一連接機構，其直接接觸該第一金屬密封部件，用於將該第一金屬密封部件電耦合至一第一電壓位準；及 一第二連接機構，其直接接觸該第二金屬密封部件，用於將該第二金屬密封部件電耦合至一第二電壓位準，以提供包圍該一或多個互連件、該對相鄰晶粒之至少一者之一中心部分或其等之一組合之一圍封電容。
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