TW201931619A - Method for manufacturing solar cell - Google Patents

Abstract

The present invention is for efficiently manufacturing a back-contact solar cell. A manufacturing method for a solar cell 10 that includes a crystal substrate 11 includes first through fifth steps. In the second step, a first lift-off layer LF1 and a second lift-off layer LF2 are formed on a p-type semiconductor layer 13p so as to be layered in that order. In the fourth step, an n-type semiconductor layer 13n is formed layered onto the second lift-off layer LF2 remaining after the third step and onto a non-formation region where no p-type semiconductor layer 13p has been formed. In the fifth step, a first etching solution is used to remove the first lift-off layer LF1 and the second lift-off layer LF2 so that the n-type semiconductor layer 13n layered onto the second lift-off layer LF2 is also removed. The etching speeds of the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2 by the first etching solution fulfil a specific relational expression.

Description

Manufacturing method of solar cell

The invention relates to a method for manufacturing a solar cell.

Generally, a solar cell is a double-sided electrode type in which electrodes are disposed on both main surfaces (light-receiving surface and back surface) of a semiconductor substrate. Recently, as a solar cell having no shielding loss caused by the electrode, an electrode disposed only on the back surface has been developed Back contact (back electrode) solar cell.

A back-contact solar cell must have a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer on the back surface with high accuracy. Compared with a double-sided electrode type solar cell, the manufacturing method is complicated. As a technique for simplifying the manufacturing method, as shown in Patent Document 1, a technique for forming a semiconductor layer pattern using a lift-off method can be cited.

That is, the development of the following patterning technology is being promoted: using silicon oxide (SiOx) or silicon nitride as a lift-off layer (also referred to as a masking layer or a sacrificial layer), and removing the lift-off layer to remove the lift-off layer formed thereon Over the semiconductor layer to form a semiconductor layer pattern.
[Prior technical literature]
[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2013-120863

[Problems to be solved by the invention]

However, in order to form a high-precision semiconductor layer pattern by using the lift-off method, there have been problems such that the lift-off layer itself must be patterned before the lift-off layer is removed, and the productivity is not necessarily high.

The present invention has been made to solve the above problems. Furthermore, the object is to efficiently produce a back-contact solar cell.
[Technical means to solve the problem]

The method for manufacturing a solar cell including a crystalline substrate according to the present invention includes:
In a first step, a first conductive semiconductor layer is formed on a main surface side of one of the crystal substrates;
The second step is based on the above-mentioned first conductive semiconductor layer, sequentially depositing and forming a first lift-off layer and a second lift-off layer including a silicon-based thin film material;
The third step is a part of the one main surface, removing the second lift-off layer, the first lift-off layer, and the first conductive semiconductor layer, thereby generating non-formation of the first conductive semiconductor layer. Region, on the other hand, the first conductive semiconductor layer, the first lift-off layer, and the second lift-off layer remain on the remaining portion of the one main surface;
A fourth step is to deposit and form a second conductive semiconductor layer on the remaining second lift-off layer and the non-formation region; and a fifth step is to remove the first lift-off using a first etching solution. Layer and the second lift-off layer, and also remove the second conductive semiconductor layer deposited on the second lift-off layer; and the first conductive semiconductor layer, the first lift-off layer, and the second lift-off layer are opposite to The etching rate of the first etching solution satisfies the following relational expression.
Etching speed of the first conductive type semiconductor layer <etching speed of the second lift-off layer <etching speed of the first lift-off layer ... [Relational expression 1]
[Effect of the invention]

According to the present invention, a back-contact solar cell can be manufactured with high efficiency.

An embodiment of the present invention will be described below, but is not limited thereto. In addition, for convenience, there are cases where hatching or component symbols are omitted. In this case, refer to other drawings. In addition, for convenience, the dimensions of various components in the drawings are adjusted for easy observation.

Hereinafter, the solar cell 10 will be described in detail. FIG. 2 is a schematic cross-sectional view showing a configuration of a solar cell 10 using a crystalline substrate 11 made of silicon. There are two main surfaces 11S (11SU, 11SB) in the solar cell 10, and the main surface [front side main surface] 11SU side of the crystal substrate 11 corresponding to one side where light is incident is referred to as the front side. The 11SB side of the other main surface [back side main surface] corresponding to the opposite side is referred to as the back side. In addition, for convenience, the description will be made assuming that the front side is a side that receives light more actively (light-receiving side) than the back side and that the back side that is not actively receiving light is a non-light-receiving side.

This solar cell is a so-called heterojunction crystalline silicon solar cell, and is a back-contact (back electrode type) solar cell 10 in which an electrode layer is disposed on only one side (back side) of the main surface.

The solar cell 10 includes a crystalline substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode layer). 18).

In the following, for convenience, components corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be individually associated, and ｢p｣ / ｢n｣ may be attached to the end of the component number. In addition, since the conductivity types are different like p-type and n-type, one conductivity type may be referred to as "first conductivity type" and the other conductivity type may be referred to as "second conductivity type".

The crystalline substrate 11 may be a substrate formed of single crystal silicon or a semiconductor substrate formed of polycrystalline silicon. Hereinafter, a single crystal silicon substrate will be described as an example.

The conductivity type of the crystal substrate 11 may be either an n-type single crystal silicon substrate containing impurities (such as phosphorus atoms) that introduce electrons into the silicon atoms, or a p-type containing impurities (such as boron atoms) that introduce holes into the silicon atoms. The single crystal silicon substrate is described below by taking an n-type crystal substrate considered to have a long carrier life as an example.

In addition, from the viewpoint of blocking the received light, it is preferable that the crystalline substrate 11 has a texture structure TX (first texture) formed on the surface of the two main surfaces 11S in the form of mountains (convex) and valley (concave). structure]. The texture structure TX (concave-convex surface) is formed by, for example, anisotropic etching using a difference between the etching rate of the (100) plane of the crystal substrate and the etching rate of the (111) plane.

The thickness of the crystal substrate 11 is preferably 250 μm or less. In the case of measuring the thickness, the measurement direction is a vertical direction with respect to the average plane of the crystal substrate 11 (the so-called average plane means a plane that does not depend on the texture structure TX as a whole substrate). Therefore, the vertical direction, that is, the direction in which the thickness is measured is hereinafter referred to as the thickness direction.

When the thickness of the crystal substrate 11 is 250 μm or less, the amount of silicon used is reduced, so it is easy to secure the silicon substrate, and cost reduction can be achieved. Moreover, it is preferable from the viewpoint of efficiently recovering each carrier that the back contact structure of holes and electrons generated in the silicon substrate by photoexcitation is recovered only on the back side.

On the other hand, if the thickness of the crystal substrate 11 is too thin, it may result in a reduction in mechanical strength or failure to sufficiently capture external light (sunlight), thereby reducing the short-circuit current density. Therefore, the thickness of the crystal substrate is preferably 50 μm or more, and more preferably 70 μm or more. When a texture structure is formed on the main surface of the crystal substrate, the thickness of the crystal substrate is an average value of the distances between the straight lines connecting the vertexes of the convexities facing each other in the uneven structure on the light receiving side and the back surface side. Means.

The intrinsic semiconductor layer 12 (12U, 12p, 12n) covers the two main surfaces 11S (11SU, 11SB) of the crystalline substrate 11 to suppress the diffusion of impurities into the crystalline substrate 11 and performs surface passivation. In addition, the term ｢intrinsic (i-type)｣ is not limited to those who do not include conductive impurities, but also include trace amounts of n-type impurities to the extent that the silicon-based layer can function as an intrinsic layer. A substantially intrinsic layer of weak n-type plutonium or p-type impurities.

The material of the intrinsic semiconductor layer 12 is not particularly limited, and is preferably an amorphous silicon-based film, and more preferably a hydrogenated amorphous silicon-based film (a-Si: H film) containing silicon and hydrogen.

The thickness of the intrinsic semiconductor layer 12 is not particularly limited, but is preferably 2 nm or more and 20 nm or less. The reason is that when the thickness is 2 nm or more, the effect as a passivation layer is improved, and when the thickness is 20 nm or less, degradation of conversion characteristics due to high resistance can be suppressed.

The method for forming the intrinsic semiconductor layer 12 is not particularly limited, and a plasma CVD (Chemical Vapor Deposition) method is preferred. The reason is that the plasma CVD method can suppress the diffusion of impurities into the single crystal silicon and can effectively passivate the surface of the substrate. In addition, in the case of the plasma CVD method, by changing the hydrogen concentration in the film of the intrinsic semiconductor layer in the film thickness direction, an effective energy gap distribution can also be formed during carrier recovery.

Furthermore, as conditions for forming a thin film by a plasma CVD method, for example, the substrate temperature is preferably 100 ° C to 300 ° C, the pressure is 20 Pa to 2600 Pa, and the high-frequency power density is 0.003 W / cm ^{2 to} 0.5. W / cm ² or less.

In addition, in the case of the intrinsic semiconductor layer 12 as the raw material gas used in the formation of the thin film, a silicon-containing gas such as SiH ₄ or Si ₂ H ₆ or a mixture of these gases with H _{2 is} preferred.

Furthermore, by adding a gas containing a different element such as CH ₄ , NH ₃ , GeH ₄ to the above gas to form a silicon alloy such as silicon carbide, silicon nitride, or silicon germanium, the energy gap of the thin film can be appropriately changed.

Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 2, a p-type semiconductor layer 13 p is formed on a portion of the back surface side of the crystalline substrate 11 through the intrinsic semiconductor layer 12 p, and an n-type semiconductor layer 13 n is formed on the back surface side of the crystalline substrate 11 through the intrinsic semiconductor layer 12 n. other parts. That is, the intrinsic semiconductor layer 12 serves as an intermediate layer for performing passivation, and is interposed between the p-type semiconductor layer 13 p and the n-type semiconductor layer 13 n and the crystal substrate 11.

The film thickness of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, but is preferably 2 nm or more and 20 nm or less. The reason is that when the thickness is 2 nm or more, the effect as a passivation layer is improved, and when the thickness is 20 nm or less, degradation of conversion characteristics due to high resistance can be suppressed.

Further, regarding the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are patterned and arranged on the back surface side of the crystal substrate 11 so as to be electrically separated. The width of the conductive semiconductor layer 13 (for example, the length of a short side if it is a linear pattern) is preferably 50 μm or more and 3000 μm or less, more preferably 65 μm or more and 1000 μm or less, and further preferably 80 μm or more. And less than 500 μm.

In the case where carriers generated on the crystalline substrate 11 are taken out through the conductive semiconductor layer 13, since the hole is larger than the effective mass of the electron, a p-type semiconductor is preferred from the viewpoint of reducing the transmission loss. The layer 13p is narrower than the n-type semiconductor layer 13n. For example, the width of the p-type semiconductor layer 13p is preferably 0.5 times or more and 0.9 times or less, and more preferably 0.6 times or more and 0.8 times or less, compared with the width of the n-type semiconductor layer 13n.

In addition, the p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron, etc.) is added, and from the viewpoint of suppression of impurity diffusion or suppression of series resistance, it is preferably formed of amorphous silicon. On the other hand, the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (phosphorus or the like) is added, and it is also preferable that the n-type semiconductor layer 13n is formed of an amorphous silicon layer similarly to the p-type semiconductor layer 13p.

Further, as the source gas, a silicon-containing gas such as SiH ₄ or Si ₂ H ₆ or a mixed gas of a silicon-based gas and H ₂ is preferably used. As the dopant gas, B ₂ H ₆ or the like is preferably used for forming the p-type semiconductor layer ₁₃ p, and PH ₃ or the like is preferably used for forming the n-type semiconductor layer. In addition, since the amount of impurities such as B or P can be added in a small amount, a mixed gas obtained by diluting a dopant gas with a source gas can also be used.

In addition, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, a gas containing a different element such as CH ₄ , CO ₂ , NH ₃ , or GeH ₄ may be added to make the p-type semiconductor layer ₁₃ p or n-type. The semiconductor layer is 13n alloyed.

The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low-reflection layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light, and examples thereof include silicon oxide, silicon nitride, zinc oxide, and titanium oxide. In addition, as a method for forming the low reflection layer, for example, a resin material in which nano particles of an oxide such as zinc oxide or titanium oxide are dispersed may be applied.

The electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, thereby being electrically connected to the semiconductor layers 13. Thereby, the electrode layer 15 functions as a transmission layer that guides the carriers passing through the p-type semiconductor layer 13p or the n-type semiconductor layer 13n to the outside of the solar cell 10.

In addition, the electrode layer 15 may be formed of only a highly conductive metal. From the viewpoint of electrical bonding with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or suppressing the metal as an electrode material to the two semiconductor layers 13p, From the viewpoint of 13n atomic diffusion, it is preferable that the electrode layer 15 formed of a transparent conductive oxide is provided between the metal electrode layer and the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.

Therefore, in this specification, the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the electrode layer 15 made of metal is referred to as a metal electrode layer 18. In addition, as shown in a plan view of the back surface side of the crystalline substrate 11 in FIG. 3, among the p-type semiconductor layer 13p and the n-type semiconductor layer 13n in a comb-tooth shape, an electrode layer formed on the back of the comb is called a bus bar portion. In the case where the electrode layer formed on the comb tooth portion is referred to as a finger portion.

The transparent electrode layer 17 is not particularly limited as a material, and examples thereof include zinc oxide or indium oxide; or 0.5% to 15% by weight, preferably 1% to 10% by weight, added to the indium oxide. Various metal oxides such as titanium oxide, tin oxide, tungsten oxide, or molybdenum oxide are transparent conductive oxides.

The thickness of the transparent electrode layer 17 is preferably 20 nm to 200 nm. As a method of forming a transparent electrode layer suitable for such a film thickness, for example, a physical vapor deposition method (PVD) such as a sputtering method may be mentioned. Or a chemical vapor deposition (MOCVD) method utilizing the reaction of an organometallic compound with oxygen or water, and the like.

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver, copper, aluminum, and nickel.

The thickness of the metal electrode layer 18 is preferably 1 μm or more and 80 μm or less. As a method for forming the metal electrode layer 18 suitable for such a film thickness, printing methods such as inkjet or screen printing of a material paste, Or plating method. However, it is not limited to this. When a vacuum process is used, evaporation or sputtering can also be used.

The width of the comb-tooth portions of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is preferably the same as the width of the metal electrode layer 18 formed thereon. However, the width is not limited to this, and the width of the metal electrode layer 18 may be narrower than the width of the comb-tooth portion. In addition, as long as the metal electrode layers 18 can be prevented from leaking to each other, the width of the metal electrode layer 18 may be wider than the width of the comb-tooth portion.

Furthermore, an annealing process is performed at the stage of laminating the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low-reflection layer 14, and the electrode layer 15 on the crystalline substrate 11, so as to achieve passivation of each bonding interface, the semiconductor layer 13, and its interface. The generation of defect energy levels is suppressed, and the resistance of the transparent electrode layer 17 is reduced.

As an annealing process, the crystal substrate with each layer arrange | positioned is heat-processed by putting into the oven which has heated at 150 degreeC or more and 200 degrees C or less, for example. In this case, the gas atmosphere in the oven can also be the atmosphere, but by using hydrogen or nitrogen, a more effective annealing treatment can be performed. The annealing treatment may be an RTA (Rapid Thermal Annealing) treatment in which infrared rays are irradiated to the crystalline substrate on which the layers are arranged using an infrared heater.

Here, the manufacturing method of the back-contact solar cell 10 as described above will be described in detail while using FIGS. 1A to 1G. This manufacturing method includes the following first to fifth steps.

First, as shown in FIG. 1A, a crystalline substrate 11 having a texture structure is prepared. Then, as shown in FIG. 1B, for example, an intrinsic semiconductor 12U is formed on the main surface 11SU on the front side of the crystal substrate 11, and an anti-reflection layer 14 is further formed on the layer 12U. Furthermore, the anti-reflection layer 14 is formed of a material having a suitable light extraction coefficient and refractive index from the viewpoint of light confinement. Examples of such a material include silicon nitride, silicon oxide, and silicon oxynitride.

Next, as shown in FIG. 1C, an intrinsic semiconductor layer 12 p is formed on the main surface 11SB on the back side of the crystalline substrate 11 by, for example, an i-type amorphous silicon layer. Next, a p-type semiconductor layer 13p is formed on the intrinsic semiconductor layer 12p. That is, the p-type semiconductor layer 13 p is formed on the main surface 11SB side which is one of the main surfaces of the crystal substrate 11 [first step].

As shown in FIG. 1C, a double-layered lift-off layer LF [a first lift-off layer LF1, a second lift-off layer LF2] is formed on the p-type semiconductor layer 13p. If described in detail, the first lift-off layer LF1 and the second lift-off layer LF2 containing, for example, a silicon-based thin film material are sequentially deposited and formed on the p-type semiconductor layer 13p [second step]. That is, the first lift-off layer LF1 is formed on the p-type semiconductor layer 13p, and the second lift-off layer LF2 is formed on the first lift-off layer LF1.

Thereafter, as shown in FIG. 1D, the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p are removed from a part of the main surface 11SB of the crystal substrate 11, thereby generating the p-type semiconductor layer. The non-formation region NA of 13p, on the other hand, at least the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2 remain on the remainder of the main surface 11SB [third step].

This patterning step is realized by a photolithography method, for example, forming a resist film (not shown) on a part and etching a part not covered by the resist film. In the situation shown in FIG. 1D, the layers of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2 are patterned, whereby the A part of the main surface 11SB generates a non-formed area NA (the details of the non-formed area NA will be described later).

Examples of the etching solution used in the third step [second etching solution] include a mixed solution of hydrofluoric acid and an oxidizing solution (for example, nitrofluoric acid), or dissolving ozone in hydrofluoric acid. The resulting solution (hereinafter referred to as ozone / hydrofluoric acid). In this case, the etchant that contributes to the etching of the lift-off layer LF is hydrogen fluoride.

However, patterning is not limited to wet etching using a resist film and an etching solution. The patterning may be, for example, dry etching or pattern printing using an etching paste or the like.

Next, as shown in FIG. 1E, the non-formation area NA in the main surface 11SB of the crystalline substrate 11 is covered with the surface LF2s (see FIG. 1D) of the second lift-off layer LF2, and the stacked and remaining layers (second lift-off Layer LF2, first lift-off layer LF1, p-type semiconductor layer 13p, intrinsic semiconductor layer 12p), forming an intrinsic semiconductor layer 12n, and further forming an n-type semiconductor layer 13n (re- Or, the surface LF2s and the side surface SE are also referred to as a residual surface). That is, an n-type semiconductor layer 13n is deposited and formed on the non-formation region NA of the remaining second lift-off layer LF2 and one of the main surfaces 11SB of the crystal substrate 11 [fourth step].

Then, as shown in FIG. 1F, the double-layer lift-off layer LF is removed using an etching solution [the first etching solution], and the layers (the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n) deposited on the layer LF are also removed from the layer. The crystal substrate 11 is removed. That is, the first lift-off layer LF1 and the second lift-off layer LF2 are removed using an etching solution, and the n-type semiconductor layer 13n deposited on the second lift-off layer LF2 is also removed [5th step]. Examples of the etching solution used in the fifth step (patterning) include hydrofluoric acid.

The etching rate of the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2 with respect to the etchant satisfies the following relational expression 1.
Etching speed of the p-type semiconductor layer 13p <etching speed of the second lift-off layer LF2 <etching speed of the first lift-off layer LF1 ... [Relational expression 1]

Thereafter, as shown in FIG. 1G, a transparent electrode layer 17 (17p, 17n) is formed on the rear surface side of the crystalline substrate 11 so as to generate an isolation groove 25, for example, by a sputtering method using a mask. Alternatively, the transparent electrode layer 17 (17p, 17n) may be formed as follows: First, a film made of a transparent conductive oxide is formed without using a mask, and thereafter, a photolithography method is used to leave only the p-type semiconductor layer 13p. The etching is performed as a film made of a transparent conductive oxide on the n-type semiconductor layer 13n.

Furthermore, the isolation trench 25 makes it difficult for a leakage current to occur. Further, a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 using, for example, a mesh screen (not shown) having an opening. According to the above, the formation of each layer in the back-bonded solar cell 10 is completed.

If the above-mentioned manufacturing method of the solar cell 10 includes the first step to the fifth step, it can be considered as follows.

First, the lift-off layer LF is formed in two or more layers, and a layer with a faster etching rate is provided on the crystal substrate 11 side (see relational expression 1). The purpose is to use the difference in the etching speed in the lift-off layer LF to improve the accuracy of the etching and simplify the patterning step in the third step and the fifth step.

In order to prevent an undesired short circuit or a leakage current of the solar cell 10, it is important that the conductive semiconductor layer 13 or the electrode layer 15 is formed accurately with the accuracy of the etching. In the third step, a part of the lift-off layer LF functions as a mask to prevent the etching solution from adhering to the required portion of the p-type semiconductor layer [first conductive semiconductor layer] 13p. Therefore, the width of the patterned p-type semiconductor layer 13p depends on the width of the remaining lift-off layer LF.

Therefore, when the etching speed of the lift-off layer LF relative to the etching solution is too fast, the lift-off layer LF is easily etched excessively in the width direction (the width is narrower than the required width), so the pattern accuracy of the lift-off layer LF may be reduced. . Therefore, it is considered that the case where the etching rate of the lift-off layer with respect to the etching solution [second etching solution] is too fast is not good.

On the other hand, in the fifth step, the n-type semiconductor layer [the second conductive type semiconductor layer] 13n not only covers the lift-off layer LF remaining in the third step, but is also formed at a desired position (the remaining p-type semiconductor layer 13p The side is the non-molded area NA). In order to leave the n-type semiconductor layer 13n at a desired position in a pattern and remove the n-type semiconductor layer 13n on the lift-off layer LF, it is preferable that the lift-off layer LF is etched with respect to the etching solution [first etching solution]. Faster. From the viewpoint of productivity, the faster the etching speed, the shorter the processing time, which is preferable.

In this way, the lift-off layer LF is required to have opposite etching characteristics in the third step and the fifth step. As long as the lift-off layer LF satisfies [Relationship 1], this characteristic will be realized.

When the relational expression 1 is satisfied in the third step, in the non-molded area NA, the first lift-off layer LF1 is dissolved fastest, whereby the second lift-off layer LF2 thereon is also easily deviated from the crystalline substrate 11. (Of course, the second lift-off layer LF2 not only deviates, but also dissolves). Furthermore, the p-type semiconductor layer 13p exposed from the first lift-off layer LF1 is also dissolved.

In the third step, for example, as shown in FIG. 1D, the side surfaces of the layers (the second lift-off layer LF2, the first lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p) are stacked and remained. SE, even if the first lift-off layer LF1 under the second lift-off layer LF2 is eroded by etching, the first lift-off layer LF1 which is not eroded remains, so the second lift-off layer LF2 connected thereto remains . Therefore, the remaining second lift-off layer LF2 functions as the lift-off layer LF in the fifth step. Furthermore, since the p-type semiconductor layer 13p at a required portion must remain, the etching rate is slower than that of the first lift-off layer LF1 and the second lift-off layer LF2.

In the fifth step, if the first lift-off layer LF1 as the lower layer is completely removed, even if the second lift-off layer LF2 on the layer LF1 remains, the n-type semiconductor layer 13n will be removed. That is, the second conductive type semiconductor layer LF2 and further the n-type semiconductor layer 13n are lifted off.

As described above, the double-layer lift-off layer LF is a layer which is intended to be substantially completely removed in the fifth step. The etching rate is designed so as not to be excessively etched in the previous steps (for example, the third step). The etching speed of the p-type semiconductor layer 13p <the etching speed of the second lift-off layer LF2 <the etching speed of the first lift-off layer LF1 [Relational expression 1]. Also, as in the third step, the p-type semiconductor layer 13p required in the fifth step must also be left, so the etching speed of the p-type semiconductor layer 13p is faster than the first lift-off layer LF1 and the second lift-off layer LF2. The etching speed is slow.

As described above, when the p-type semiconductor layer 13p and the lift-off layer LF satisfying the relational expression 1 are used, for example, in a fifth step, the n-type semiconductor layer 13n is patterned without performing etching using a resist film. That is, if it is the manufacturing method of the solar cell 10 mentioned above, a patterning process can be simplified and the back-contact solar cell 10 can be manufactured efficiently. Moreover, the pattern accuracy is also improved, so that short circuit or leakage of the solar cell 10 can be prevented, and a high output can be obtained from the solar cell 10.

Furthermore, in the second step, a two-layer lift-off layer LF is formed on the p-type semiconductor layer 13p formed in the first step. Then, these lift-off layers LF are patterned (eg, etched) in the third step, and are removed together with the n-type semiconductor layer 13n in the fifth step. Therefore, the lift-off layer LF is preferably formed by using a material that is soluble in the etching solution used in the third step and the fifth step, such as a metal-based thin film material, a metal oxide-based thin film material, or a silicon-based thin film material. Furthermore, among such materials, a silicon-based thin film material is also preferable, for example, a double-layered lift-off layer LF mainly composed of silicon oxide is preferred.

In addition, when a film mainly composed of silicon oxide is used in the lift-off layer LF in this way, the etching solution in the fifth step is preferably hydrofluoric acid. In this case, the etchant for etching the lift-off layer LF is hydrogen fluoride. The number of stacked layers of the lift-off layer LF may be two or more, but it is preferably two from the viewpoint of productivity.

Of course, as a design for satisfying the etching rate in the relationship 1, it is preferable that the main component of the p-type semiconductor layer 13p is silicon, and the main components of the first lift-off layer LF1 and the second lift-off layer LF2 are silicon oxide. However, in order to control the etching speed, it is preferable to make a difference in density. The reason is that if the density is low, the etching rate is increased.

In addition, the refractive index of each layer varies depending on the density. Therefore, for example, it is preferably as follows (if the density is higher, the refractive index is also increased and the etching rate is lower, and if the density is lower, the refractive index is also changed. Low and increased etch rate).

That is, the first lift-off layer LF1 and the second lift-off layer LF2 are layers containing silicon oxide as a main component, and the refractive index measured using a wavelength of 550 nm preferably satisfies the following relational expression.
Refractive index of the second lift-off layer LF2> Refractive index of the first lift-off layer LF1 ... [Relationship Formula 2]

When the lift-off layer LF has three or more layers, it is sufficient to form a second lift-off layer LF2 having a higher refractive index than the first lift-off layer LF1 after the first lift-off layer LF1.

In terms of the composition of the lift-off layer LF, when the lift-off layer LF is a film containing silicon oxide as the main component, the value of x when the main component is expressed as SiOx preferably satisfies the following relationship. formula.
X of the first lift-off layer LF1> x of the second lift-off layer LF2 ... [Relationship 3]

The value of x is preferably in a range of 0.5 or more and 2.2 or less, more preferably 1.2 or more and 2.0 or less, and particularly preferably 1.4 or more and 1.9 or less. It is preferable to design the size relationship in each range.

Furthermore, here, the value of x is an upper limit of a value larger than the usual stoichiometric value (x = 2.0), because the oxygen may be excessively contained in the film formation process of the lift-off layer LF. .

However, the film thickness of the lift-off layer LF is preferably 50 nm or more and 600 nm or less, and particularly preferably 100 nm or more and 450 nm or less. Within this range, the second lift-off layer LF2 is preferably thicker than the first lift-off layer LF1.

Furthermore, in the patterning step using a laser, it may be difficult to suppress damage due to the scattering of light by the laser irradiation surface. However, since the texture structure TX is also formed on the back side of the crystal substrate 11, the light can be increased. Capture efficiency.

In the third step, etching may be performed until the intrinsic semiconductor layer 12 to expose a part of the crystal substrate 11. As a result, there is a case where the decrease in the lifetime of the carriers generated by the photoelectric conversion is suppressed.

In the fourth step, an n-type semiconductor layer 13n is formed. The n-type semiconductor layer 13 n is formed on the entire surface of the back surface side of the crystal substrate 11. That is, it is formed not only on the surface of a part of the crystalline substrate 11 without the p-type semiconductor layer 13p, but also on the lift-off layer LF. Furthermore, an intrinsic semiconductor layer 12n may be formed between the crystalline substrate 11 and the n-type semiconductor layer 13n.

In addition, in the fourth step, before forming the intrinsic semiconductor layer 12 and the n-type semiconductor layer 13n, there may be a step of cleaning the surface of the crystalline substrate 11 exposed in the third step. Moreover, the purpose of performing the cleaning step is to remove defects or impurities generated on the surface of the crystal substrate 11 in the third step, and for example, to perform treatment with hydrofluoric acid.

In addition, it is preferable that the crystalline substrate 11 has a texture structure TX, and each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the main surface 11SB side of the crystalline substrate 11 includes a texture reflecting the texture structure TX. Structure [Second Texture Structure].

If the semiconductor layer 13 includes such a texture structure, the etching solution easily penetrates into the semiconductor layer 13 due to the unevenness. Therefore, these layers 13 are easily removed, that is, they are easily patterned.

Furthermore, in FIG. 1D, in the non-formation region NA, a part of the main surface 11SB of the crystalline substrate 11 is exposed, but it is not limited thereto, and the intrinsic semiconductor layer 12p may remain on a part of the main surface 11SB. . In short, the p-type semiconductor layer 13p may be removed from a part of the main surface 11SB of the crystal substrate 11 so that the (disappearing) region without the layer 13p may be a non-formation region NA.

In this way, the following steps are reduced: an intrinsic semiconductor layer 12n is formed before the n-type semiconductor layer 13n is deposited and formed on the remaining second lift-off layer LF2 and the non-formation region NA.

In the third step, an opening portion may be formed in the second lift-off layer LF2, and an etching solution [second etching solution] may be attached to the first lift-off layer LF1 through the opening, and the first lift-off layer may be lifted off. The layer LF1 is removed. Furthermore, in the third step, the first lift-off layer LF1 may be removed as described above, and the etching solution may also be attached to the p-type semiconductor layer 13p, and the p-type semiconductor layer 13p may be removed. Further, as a method of forming the opening, for example, a method using a photoresist having an opening by a photolithography method; using a laser or the like to make the forming portion of the opening disappear, or making the opening The formation of the part is cracked.

In this way, since the etching solution reliably adheres to the second lift-off layer LF2 through the opening portion, and further adheres to the first lift-off layer LF1, the entire lift-off layer LF is efficiently removed. In addition, by removing the lift-off layer LF, the etching solution is surely attached to the p-type semiconductor layer 13p covered by the layer LF, and the p-type semiconductor layer 13p is removed. That is, the dissolution residues of the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p are suppressed.

Furthermore, it is preferable that the concentration of the etchant contained in the etching solution [the first etching solution] used in the fifth step is higher than that of the etchant contained in the etching solution [the second etching solution] used in the third step. High concentration.

In this way, a part of the lift-off layer LF is left in the third step, and the lift-off layer is removed in the fifth step, so that the required patterning can be easily performed.

The present invention is not limited to the above-mentioned embodiments, and various changes can be made within the scope shown in the claims. That is, an embodiment obtained by a combination of technical means appropriately changed within the range indicated in the claims is also included in the technical scope of the present invention.

For example, the semiconductor layer used in the first step is a p-type semiconductor layer, but it is not limited to this, and may be an n-type semiconductor layer. The conductivity type of the crystal substrate is not particularly limited, and may be either a p-type or an n-type.
[Example]

Hereinafter, the present invention will be specifically described by examples, but the present invention is not limited to these examples. The examples and comparative examples were prepared as follows (see Table 1).

[Crystalline substrate]
First, as a crystalline substrate, a single-crystal silicon substrate having a thickness of 200 μm was used. Then, anisotropic etching is performed on both sides of the single crystal silicon substrate. Thereby, a pyramid-shaped texture structure is formed on the crystal substrate.

[Intrinsic semiconductor layer]
The crystalline substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer (film thickness: 8 nm) made of silicon was formed on the main surfaces on both sides of the crystalline substrate. In addition, the film formation conditions are set to a substrate temperature of 150 ° C., a pressure of 120 Pa, a SiH ₄ / H ₂ flow ratio of 3/10, and a power density of 0.011 W / cm ² .

[p-type semiconductor layer (first conductive type semiconductor layer)]
A crystalline substrate having an intrinsic semiconductor layer formed on both main surfaces is introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon-based thin film (film thickness 10 nm) is formed on the intrinsic semiconductor layer on the main surface on the back side [Step 1] ]. In addition, the film formation conditions are set to a substrate temperature of 150 ° C., a pressure of 60 Pa, a SiH ₄ / B ₂ H ₆ flow ratio of 1/3, and a power density of 0.01 W / cm ² . The B ₂ H ₆ gas flow rate is a flow rate of a diluting gas until B ₂ H _{6 is} diluted to 5000 ppm with H ₂ .

[Lift off the floor]
Furthermore, using a CVD apparatus, a first lift-off layer and a second lift-off layer having a main component of silicon oxide (SiOx) were sequentially formed on a p-type hydrogenated amorphous silicon-based thin film.

Furthermore, the film formation conditions of the first lift-off layer are set to a substrate temperature of 180 ° C., a pressure of 50 Pa, a SiH ₄ / CO ₂ flow ratio of 1/7, and a power density of 0.3 W. / cm ² . The film formation conditions of the second lift-off layer were the same as those of the first lift-off layer, except that the SiH ₄ / CO ₂ flow rate ratio was set to 1/5. Moreover, in order to make both lift-off layers into a specific film thickness, the film-forming time is adjusted separately.

The composition of SiOx, which is the main component of the first and second liftoff layers, was analyzed by photoelectron spectroscopy. As a result, it was confirmed that the value of x is larger than that of the second liftoff layer.

[Pattern pattern of lift-off layer and first conductive semiconductor layer]
A photosensitive resist film is formed on the main surfaces of both sides of the crystal substrate on which the p-type semiconductor layer is formed. Using the photolithography method, the second lift-off layer, the first lift-off layer, and the p-type semiconductor layer are removed from a part of the main surface of the back surface side of the crystalline substrate to generate a non-formed region where the p-type semiconductor layer disappears. , At least the p-type semiconductor layer, the first lift-off layer, and the second lift-off layer remain on the remaining portion of the main surface on the back side [third step].

Furthermore, at this time, the crystalline substrate on which the various layers were formed was immersed in hydrated nitric acid containing 1% by weight of hydrogen fluoride as an etchant to remove the first lift-off layer and the second lift-off layer. Thereafter, the p-type semiconductor layer exposed by the removal of the first lift-off layer and the second lift-off layer and the intrinsic semiconductor layer directly below it are removed. That is, in the non-formation region, the rear-surface-side main surface of the crystal substrate is exposed.

Furthermore, in Example 4, the immersion time was set to a shorter time than that of other examples using hydrated nitric acid containing 5% by weight of hydrogen fluoride.

[n-type semiconductor layer (second conductive type semiconductor layer)]
After the third step, the crystalline substrate after cleaning the main surface exposed on the back side by 2% by weight of hydrofluoric acid was introduced into the CVD apparatus, and the main surface on the back side had the same topography as described above and a semiconductor layer (film 8 nm thick), and an n-type hydrogenated amorphous silicon-based thin film (film thickness 10 nm) was formed on this layer [4th step]. In addition, the film formation conditions are that the substrate temperature is 150 ° C., the pressure is 60 Pa, the SiH ₄ / PH ₃ / H ₂ flow ratio is 1/2, and the power density is 0.01 W / cm ² . The PH ₃ gas flow rate is a flow rate of a diluent gas until the pH _{3 is} diluted to 5000 ppm with H ₂ .

[Removal of lift-off layer and second conductive semiconductor layer]
The crystalline substrate on which the n-type semiconductor layer was formed was immersed in hydrofluoric acid containing 3% by weight of hydrogen fluoride as an etchant to collectively remove the lift-off layer, the n-type semiconductor layer, and between the lift-off layer and the n-type semiconductor layer Intrinsic semiconductor layer [step 5].

[Electrode layer, low reflection layer]
A magnetron sputtering device was used to form a film (film thickness: 100 nm) as a base of a transparent electrode layer on a conductive semiconductor layer of a crystalline substrate. As a low-reflection layer, a silicon nitride layer is formed on the light-receiving surface side of the crystal substrate. As a transparent conductive oxide, indium oxide (ITO) containing 10% by weight of tin oxide was used as a target, and a mixed gas of argon and oxygen was introduced into the chamber of the device, and the pressure in the chamber was set to 0.6 Pa. pressure.

It should be noted that the mixing ratio of argon and oxygen is set to a condition where the resistivity is the lowest (so-called bottom). Further, a film was formed using a DC power source at a power density of 0.4 W / cm ² .

Next, a photolithography method is used to etch only a film made of a transparent conductive oxide on the p-type semiconductor layer and the n-type semiconductor layer to form a transparent electrode layer. The transparent electrode layer completed by the etching prevents conduction between a film made of a transparent conductive oxide on the p-type semiconductor layer and a film made of a transparent conductive oxide on the n-type semiconductor layer.

Furthermore, screen printing was performed on the transparent electrode layer without diluting a silver paste (Dotite FA-333 manufactured by Fujikura Kasei), and a heating treatment was performed in a 150 ° C oven for 60 minutes. Thereby, a metal electrode layer is formed.

Next, an evaluation method of a back-contact solar cell will be described. Refer to Table 1 for the evaluation results.

[Evaluation of film thickness and etchability]
The thickness or etched state of the lift-off layer is measured using an optical microscope (BX51, manufactured by Olympus Optical Industries) and a SEM (Scanning Electron Microscope, scanning electron microscope) (field emission scanning electron microscope S4800, manufactured by Hitachi High-tech Corporation). Evaluation. After the third step, it is set to ｢○｣ when it can be etched in accordance with the patterned removal area of the design. It is set to ｢×｣ when the lift-off layer is excessively etched and adversely affects the characteristics of the solar cell. . In the fifth step, ｢○｣ is set when the lift-off layer has been removed, and ｢×｣ is set when the lift-off layer remains. In Comparative Example 2, the lift-off layer was removed in the third step, and the evaluation after the fifth step cannot be achieved, so it is set to-.

[Evaluation of refractive index]
The refractive index of a thin film formed on a glass substrate under the same conditions was determined by measurement using a spectroscopic ellipsometry (trade name M2000, manufactured by JA Woollam). The refractive index at a wavelength of 550 nm is selected from the fitting results.

[Assessment of conversion efficiency]
The solar simulator was used to irradiate AM (air mass) 1.5 reference sunlight at a light amount of 100 mW / cm ^{2 to} measure the conversion efficiency (Eff (%)) of the solar cell. The conversion efficiency of Example 1 was set to 1.00, and the relative values are shown in Table 1.

[Table 1]

In this example and comparative example, the etching rate of the first lift-off layer with respect to 3% by weight of hydrofluoric acid is 6.5 nm / second, and the etching rate of the second lift-off layer with respect to 3% by weight of hydrofluoric acid is 0.3 nm / second.

The pattern accuracy and solar cell characteristics of Examples 1 to 4 were all good. In Example 2 where the film thickness of the first lift-off layer is thicker, the time required to remove the lift-off layer in the fifth step is short, and the productivity is excellent.

In addition, for Examples 1 to 3 using hydrated nitric acid containing 1% by weight of hydrogen fluoride in the third step, the pattern accuracy after the third step was observed with an optical microscope. As a result, the pattern accuracy of any one was good. . In Example 3, the pattern thickness of the first lift-off layer is the thinnest, and the pattern accuracy of the first lift-off layer is thinner than that of the second lift-off layer.

From the viewpoint of uniformity in the battery, the pattern accuracy of Example 4 is slightly lower than that of Example 1, but it does not adversely affect the characteristics of the solar cell.

In summary, the results obtained by the examples are better than those of the comparative examples by removing the laminated layers and improving the solar cell characteristics. It is considered that the reason is that either the third step or the fifth step is patterned and etched uniformly and accurately, so that the first conductive type semiconductor layer and the second conductive type semiconductor layer can be aligned or connected to the electrode. The layer's electrical contact (suppression of the increase in series resistance) is good.

In particular, when the lift-off layer is formed of only a high-refractive index layer (Comparative Example 1), there is a residue of the lift-off layer in the fifth step. In the case where a layer is formed (Comparative Example 2), most of the lift-off layer is removed by using hydrated nitric acid in the third step, so that sufficient solar cell characteristics cannot be obtained.

10‧‧‧ solar battery

11‧‧‧ crystal substrate

11S‧‧‧Main face

11SB‧‧‧Main face

11SU‧‧‧Main face

12‧‧‧ intrinsic semiconductor layer

12n‧‧‧ intrinsic semiconductor layer

12p‧‧‧ intrinsic semiconductor layer

12U‧‧‧ intrinsic semiconductor layer

13‧‧‧Conductive semiconductor layer

13p‧‧‧p-type semiconductor layer [first conductive type semiconductor layer / second conductive type semiconductor layer]

13n‧‧‧n-type semiconductor layer [second conductive type semiconductor layer / first conductive type semiconductor layer]

14‧‧‧Low reflection layer

15‧‧‧ electrode layer

15n‧‧‧electrode layer

15p‧‧‧electrode layer

17‧‧‧ transparent electrode layer

17n‧‧‧Transparent electrode layer

17p‧‧‧Transparent electrode layer

18‧‧‧ metal electrode layer

18n‧‧‧metal electrode layer

18p‧‧‧metal electrode layer

25‧‧‧Isolation trough

LF‧‧‧ Lift off layer

LF1‧‧‧The first lift off layer

LF2‧‧‧The first lift off layer

LF2s‧‧‧Surface

NA‧‧‧Unformed area

SE‧‧‧side

TX‧‧‧Texture Structure

FIG. 1A is a sectional view showing a method of manufacturing a solar cell.

FIG. 1B is a sectional view showing a method of manufacturing a solar cell.

FIG. 1C is a sectional view showing a method for manufacturing a solar cell.

FIG. 1D is a sectional view showing a method of manufacturing a solar cell.

FIG. 1E is a sectional view showing a method of manufacturing a solar cell.

FIG. 1F is a sectional view showing a method of manufacturing a solar cell.

FIG. 1G is a sectional view showing a method of manufacturing a solar cell.

Fig. 2 is a sectional view showing a solar cell.

Fig. 3 is a plan view showing an electrode layer of a solar cell.

Claims (8)

A method for manufacturing a solar cell including a crystalline substrate, including: In a first step, a first conductive semiconductor layer is formed on a main surface side of one of the crystal substrates; The second step is to sequentially deposit and form a first lift-off layer and a second lift-off layer containing a silicon-based thin film material for the first conductive semiconductor layer; The third step is a part of the one main surface, removing the second lift-off layer, the first lift-off layer, and the first conductive semiconductor layer, thereby generating non-formation of the first conductive semiconductor layer. Region, on the other hand, the first conductive semiconductor layer, the first lift-off layer, and the second lift-off layer remain on the remaining portion of the one main surface; A fourth step is to deposit and form a second conductive type semiconductor layer on the remaining second lift-off layer and the non-formation region; and A fifth step is to use the first etching solution to remove the first lift-off layer and the second lift-off layer, and also remove the second conductive semiconductor layer deposited on the second lift-off layer; and The etching rate of the first conductive semiconductor layer, the first lift-off layer, and the second lift-off layer with respect to the first etching solution satisfies the following relationship: Etching speed of the first conductive type semiconductor layer <etching speed of the second lift-off layer <etching speed of the first lift-off layer ... [Relational Formula 1]. For example, the method for manufacturing a solar cell according to claim 1, wherein the first lift-off layer and the second lift-off layer are layers containing silicon oxide as a main component, and the refractive index measured using a wavelength of 550 nm satisfies the following relationship: Refractive index of the second lift-off layer> Refractive index of the first lift-off layer ... [Relationship Formula 2]. For example, the method for manufacturing a solar cell according to claim 1, wherein the first lift-off layer and the second lift-off layer are films containing silicon oxide as the main component, and the value of x when the main component is expressed as SiOx satisfies the following relationship formula: X of the first lift-off layer> x of the second lift-off layer ... [Relationship 3]. The method for manufacturing a solar cell according to any one of claims 1 to 3, wherein The crystal substrate has a first texture structure, Each of the first conductive type semiconductor layer and the second conductive type semiconductor layer formed on the one main surface side of the crystal substrate includes a second texture structure reflecting the first texture structure. The method for manufacturing a solar cell according to any one of claims 1 to 4, wherein in the non-formation region, a part of the one main surface of the crystal substrate is exposed. The method for manufacturing a solar cell according to any one of claims 1 to 5, wherein in the third step, an opening is formed in the second lift-off layer, and a second etching solution is attached to the first through the opening. 1 lift off layer, and remove the first lift off layer. The method for manufacturing a solar cell according to claim 6, wherein in the third step, the first lift-off layer is removed, and the second etching solution is also adhered to the first conductive semiconductor layer, and the first conductive layer is removed. Conductive semiconductor layer. The method for manufacturing a solar cell according to claim 6 or 7, wherein the concentration of the etchant contained in the first etching solution is higher than the concentration of the etchant contained in the second etching solution.