TW201926405A - 用於內連線的釕金屬特徵部填補 - Google Patents

用於內連線的釕金屬特徵部填補 Download PDF

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TW201926405A
TW201926405A TW107134901A TW107134901A TW201926405A TW 201926405 A TW201926405 A TW 201926405A TW 107134901 A TW107134901 A TW 107134901A TW 107134901 A TW107134901 A TW 107134901A TW 201926405 A TW201926405 A TW 201926405A
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ruthenium
metal
features
ruthenium metal
item
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TW107134901A
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TWI827553B (zh
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尤凱鴻
可拉斯 喬伊
志方 劉
大衛 Ｌ 歐麥拉
大衛 羅森塔爾
井下田真信
科瑞 瓦伊達
赫里特 Ｊ 盧森克
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日商東京威力科創股份有限公司
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/16—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal carbonyl compounds
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]

Abstract

本發明係提供一種用於基板之特徵部中無空隙釕(Ru)金屬填補的方法。本方法包含提供包含複數特徵部之一基板，於該等特徵部中沉積一釕金屬層，移除該等特徵部之開口周圍之場區的該釕金屬層，以及於該等特徵部中沉積額外的釕金屬，其中該額外釕金屬係以高於沉積在該場區上的速率而沉積在該特徵部中。根據一實施例，該額外釕金屬係沉積直至該等特徵部完全充滿釕金屬為止。

Description

用於內連線的釕金屬特徵部填補
〔相關申請案的交互參照〕本申請案係基於2017年10月4日所提出之美國臨時專利申請案第62/568,218號並主張其優先權，上述之完整內容乃併入以供參照。
本發明係關於使用低電阻係數之釕(Ru)金屬對微電子裝置進行特徵部(例如介層孔與渠溝)之無空隙填補的方法。
積體電路含有各種半導體裝置與複數之導電金屬通道，其供應電源給半導體裝置且使這些半導體裝置可以共享及交換資訊。在積體電路之中，利用使金屬層彼此互相絕緣的金屬間或層間介電層而將金屬層互相堆疊在另一金屬層之上。
通常，各金屬層必須與至少一額外的金屬層形成電性接觸。藉由在用以使金屬層分離的層間介電質中蝕刻出特徵部（亦即介層孔），且利用金屬填補所產生的介層孔而產生內連線，進而達成此種電性接觸。金屬層通常佔據層間介電質中被蝕刻出的通道。「介層孔」一般代表形成於介電層之中的任何特徵部，例如孔洞、線路或其它類似特徵部，其提供通過介電層而到達介電層下方之導體層的電性連接。類似地，一般將連接兩個或更多之介層孔的金屬層稱為渠溝。
在用以製造積體電路的多層金屬化方案中使用銅（Cu）金屬，會因為Cu原子在介電材料(例如SiO2 )中的高遷移率而產生問題，且Cu原子可能在Si中產生電性缺陷。因此，一般以阻障材料包封Cu金屬層、填補Cu的渠溝、及填補Cu的介層孔，以防止Cu原子擴散到介電材料及Si之中。在沉積Cu晶種之前，通常先將阻障層沉積在渠溝與介層孔的側壁與底部之上，且阻障層包括較佳在Cu中不起反應且不融和的、對介電材料提供優良的接合且提供低電阻係數的材料。
裝置效能的提升通常伴隨著裝置面積的減小或裝置密度的提高。提高裝置密度需要用於形成內連線之介層孔的尺寸縮小，包括更高的深寬比(亦即深度對寬度之比例)。隨著介層孔的尺寸縮小且深寬比提高，愈來愈難在介層孔的側壁上形成具有足夠厚度的擴散阻障層，同時又提供足夠的容積給介層孔中的金屬層。此外，隨著介層孔與渠溝尺寸縮小且介層孔與渠溝中之層的厚度減小，層及層之接面的材料性質變得日益重要。具體而言，必須謹慎地將形成這些層的製程整合到對製程順序的所有步驟均維持優良控制的製造製程順序中。
關於在基板之日益微型化的特徵部中使用Cu金屬的問題，需要使用其他低電阻係數的金屬來取代Cu。便需要對於此等日益微型化之特徵部之無空隙金屬填補的新方法。
本發明提供了一種以釕金屬填補基板中之特徵部的方法。本方法包含提供一含有複數特徵部之基板，於該等特徵部中沉積一釕金屬層，移除該等特徵部之開口周圍之場區的該釕金屬層，以及於該等特徵部中沉積額外的釕金屬，其中該額外釕金屬係以高於沉積在該場區上的速率而沉積在該特徵部中。根據一實施例，該額外釕金屬係沉積直至該等特徵部完全充滿釕金屬為止。
根據另一實施例，本方法包括提供含有複數特徵部的基板，於該等特徵部中沉積一釕金屬層，其中沉積釕金屬層的步驟會在特徵部充滿釕金屬層之前夾止特徵部之開口，藉此於特徵部中形成空隙。本方法步驟更包含移除引起夾止的多餘釕金屬，其中該移除步驟係移除特徵部之開口周圍之場區的釕金屬層，以及於特徵部中沉積額外的釕金屬，其中該額外釕金屬係以高於沉積在該場區上的速率而沉積在特徵部中。根據一實施例，該額外釕金屬係沉積直至該等特徵部完全充滿釕金屬為止。
在若干實施例中描述了用於微電子裝置中以具有低電阻率之釕金屬而無空隙填補特徵部的方法。此處已顯示出釕金屬具有短的有效電子平均自由路徑，是滿足國際半導體技術路線圖（ITRS）電阻要求的優秀候選者而作為Cu金屬在最小特徵尺寸為約10nm（5nm節點）的替代品。由於釕金屬的許多材料和電性，特徵尺寸的向下縮放比Cu金屬的影響更小。
根據一實施例，本方法係提供以釕金屬填充基板中的特徵部或基板上之膜中的特徵部。本方法包含提供含有特徵部之基板，於特徵部中沉積一釕金屬層，移除特徵部之開口周圍之場區的釕金屬層，以及於特徵部中沉積額外的釕金屬，其中該額外釕金屬係以高於沉積在該場區上的速率而沉積在特徵部中。
根據另一實施例，本方法包括提供含有特徵部的基板，於特徵部中沉積一釕金屬層，其中沉積釕金屬層的步驟會在特徵部充滿釕金屬層之前夾止特徵部之開口，藉此於特徵部中形成空隙。本方法步驟更包含移除引起夾止的多餘釕金屬，其中該移除步驟係移除特徵部之開口周圍之場區的釕金屬層，以及於特徵部中沉積額外的釕金屬，其中該額外釕金屬係以高於沉積在該場區上的速率而沉積在特徵部中。
本發明的實施例可以應用於在半導體裝置中發現之不同實際形狀的各種凹陷特徵部，包括具有垂直側壁的方形特徵部、具有凸形側壁的弓形特徵部、及具有相對於從特徵部頂部延伸到特徵部底部的方向之倒置式輪廓(retrograde profile)區域之側壁的特徵部。這些特徵部可以例如包括渠溝或介層孔。特徵部直徑可小於30nm、小於20nm、小於10nm或小於5nm。特徵部直徑可以介於20nm～30nm之間、10nm～20nm之間、5nm～10nm之間、或者3nm～5nm之間。特徵部的深度可例如大於20nm、大於50nm、大於100nm或大於200nm。例如，這些特徵部可以具有深寬比介於2：1～20：1之間、2：1～10：1之間、或2：1～5：1之間（AR，深度：寬度）。在一範例中，基板（例如Si）包括介電層，且該特徵部形成於介電層中。
圖1A～1D為示意性的剖面圖，說明根據本發明之一實施例中之特徵部的釕金屬填補。如圖1A所示，基板10包含膜102中的特徵部104，其中特徵部104包括側壁108，其具有相對於從特徵部104的頂部延伸到膜100上方之特徵部104的底部之方向的倒置型輪廓的區域。基板10還包括靠近特徵部104的開口的場區106。根據一實施例，膜100和102可以包含相同的材料。例如，該材料可選自由下列各者組成之群組：矽、鍺、矽鍺、介電材料、金屬和含金屬材料。介電材料可選自由下列各者組成之群組：SiO2 、SiON、SiN、高k材料、低k材料和超低k材料。根據另一實施例，膜100和102可包含不同的材料。不同的材料可選自由下列各者組成之群組：矽、鍺、矽鍺、介電材料、金屬和含金屬材料。介電材料可選自由下列各者組成之群組：SiO2 、SiON、SiN、高k材料、低k材料和超低k材料。
圖1B顯示具有實質均勻厚度的共形釕金屬層110沉積在基板10上，並包括沉積於場區106及特徵部104中。共形釕金屬層110在特徵部104被釕金屬填充之前夾止特徵部開口，從而阻止釕金屬進一步沉積在特徵部104中，並在特徵部104內部形成空隙（鍵孔）112。釕金屬層110由純釕金屬或含有少量雜質（例如碳和氧）的實質純釕金屬組成。釕金屬層110可以透過原子層沉積（ALD）、化學氣相沉積（CVD）、電鍍或濺射來沉積。在一實例中，可以使用Ru3 （CO）12 和CO載氣在約200℃的基板溫度下透過CVD來沉積釕金屬層。然而，CVD可以使用其他釕金屬前驅物來沉積釕金屬層110。
儘管圖1B中未示出，在釕金屬沉積之前，可以透過ALD或CVD在基板10上、包括在特徵部104中沉積一成核層。根據一實施方案，成核層可能係選自由下列成分所組成之族群：Mo、 MoN、 Ta、 TaN、 TaAlN、 W、 WN、 Ti、 TiN 以及 TiAlN。成核層的一個作用是在特徵部104中提供良好的成核表面以及黏附表面，以確保釕金屬層以短暫之孕育時間進行保型沉積。與使用Cu金屬填充物不同，在特徵部中介電材料和釕金屬之間不需要良好的擴散阻障層。因此，在釕金屬填充的情況下，成核層可以非常薄且可以是不連續或不完整的，其並具有空隙而在特徵部中使介電材料暴露出來。與Cu金屬特徵部填充相比，此會使特徵部釕金屬填充的量增加。在一些範例中，成核層的厚度可以是20Å或更薄、15Å或更薄、10Å或更薄、或5Å或更薄。在一實例中，可以使用原子層沉積法（ALD）沉積TaN成核層，其中在基板溫度約為350℃時，交替暴露第三丁基亞胺基-三-乙基甲基胺基-鉭（TBTEMT，Ta（NCMe3 ）（NEtMe）3 ）和氨（NH3 ）。
圖1C顯示從特徵部104之開口周圍的場區106移除釕金屬層110並移除導致特徵部開口夾止的釕金屬層110之後的基板10。根據一實施例，去除釕金屬層110可包括將基板10暴露於一電漿激發乾式蝕刻製程。電漿激發乾式蝕刻製程可包括電漿激發之蝕刻氣體與釕金屬層110之間的化學反應、藉由非反應性氣體物理去除釕金屬層110、或其組合。在一範例中，電漿激發乾式蝕刻製程包括將基板10暴露於含有含氧氣體及任選之含鹵氣體的電漿激發蝕刻氣體。在另一範例中，該移除步驟可以包括使用電漿激發的氬氣進行釕金屬層110的濺射去除或重新分佈。根據另一實施例，釕金屬層110的去除可包括化學機械拋光（CMP）製程。根據另一實施例，去除釕金屬層110可包括對釕金屬層110進行熱處理以使特徵部104中的釕金屬層110回流。根據又一實施例，去除釕金屬層110可以包括電漿激發乾式蝕刻製程與熱處理的組合。用於電漿激發乾式蝕刻製程的示例性處理條件包括約5mTorr～約760mTorr之間的氣壓、基板溫度在約40℃至約370℃之間。可以使用包含頂部電極板及支撐基板的底部電極板之電容耦合電漿（CCP）處理系統。在一個示例中，可以將約100W～約1500W之間的射頻（RF）功率施加到頂部電極板。 RF功率也可以施加到底部電極板以增加釕金屬去除。
根據一實施例，電漿激發蝕刻氣體可包含含氧氣體和任選之含鹵素氣體，以增強對釕金屬的移除。含氧氣體可包括O2 、 H2 O、CO、CO2 及其組合。含鹵氣體可以例如包括Cl2 、BCl3 、CF4 及其組合。在一個示例中，電漿激發蝕刻氣體可包括O2 和Cl2 。電漿激發蝕刻氣體可以進一步包括Ar氣。在另一個例子中，電漿激發蝕刻氣體可以由O2 氣體和任選的Ar氣體組成。在一些實施例中，電漿激發蝕刻氣體中的一種或多種氣體可以循環。
圖1D顯示在特徵部104中沉積額外的釕金屬114之後的基板10，其導致特徵部104之無空隙釕金屬填補。本發明人已經發現額外的釕金屬114係以高於沉積在薄膜102之場區106上的速率而沉積在特徵部104的釕金屬層110上，從而能夠以釕金屬完全填充特徵部104，並在額外的釕金屬114充滿特徵部104之前防止特徵部開口的夾止。 釕金屬層110和額外之釕金屬114一起以釕金屬完全填充特徵部104，而在場區106上存在過量的釕金屬。根據一些實施例，如果需要的話，釕金屬沉積和釕金屬去除的步驟可以重複至少一次以提供特徵部104的無空隙釕金屬填補。
根據本發明的一實施例，在釕金屬填充之後，可以對基板10進行熱處理，以使釕金屬中的雜質最小化並增加釕金屬晶粒尺寸。如此會導致釕金屬的電阻降低。根據另一實施例，在從特徵部104之開口周圍的場區106去除釕金屬層110之後，可以對基板進行熱處理，以使釕金屬中的雜質最小化並提供特徵部104中相對於場區106上之釕金屬沉積選擇性的改善。熱處理可以在200℃至600℃之間、300℃至400℃之間、500℃至600℃之間、400°C至450°C之間、或在450°C至500°C之間的基板溫度下進行。且熱處理可以在氬氣、氫氣或氬氣和氫氣兩者的存在下於低於大氣壓下進行。在一個實例中，熱處理可在成形氣體存在下在低於大氣壓下進行。成形氣體是氫氣與氮氣的混合物。在另一範例中，熱處理可以在高真空條件下進行，而不將氣體流入用於熱處理的處理室。
圖2A-2C顯示根據本發明之一實施例中，特徵部之釕金屬填充的SEM剖面圖像。圖2A顯示沉積在基板上的共形釕金屬層202，該基板包含在膜200中蝕刻之特徵部。這些特徵部具有約19nm的開口直徑，約40nm的底部直徑和約83nm的高度。可以使用Ru3 （CO）12 和CO載氣在約200℃的基板溫度下透過CVD來沉積共形釕金屬層202。圖2A中的共形釕金屬層202層在特徵部被釕金屬填充之前夾住特徵部開口，藉此在特徵部內部形成空隙212。圖2B顯示從特徵部之開口周圍的場區206移除共形釕金屬層202、並去除導致特徵部開口夾止之釕金屬層202的一部分之後的基板。使用電漿激發乾式蝕刻製程進行釕金屬去除，該製程包括將基板暴露於含有O2 氣體、Cl2 氣體和Ar氣體的電漿激發蝕刻氣體。圖2C顯示在特徵部中沉積額外的釕金屬214之後的基板，其導致特徵部的無空隙釕金屬填充。額外的釕金屬214係以比沉積在場區206上更高的速率沉積在特徵部中，從而使特徵部能夠完全填充以釕金屬並防止特徵部開口在特徵部充滿釕金屬之前被夾止。
在各種實施例中已經揭露以低電阻釕金屬進行微電子裝置之特徵部（例如介層孔和渠溝）無空隙填充的方法。本發明之實施例的前述描述係出於說明和描述的目的呈現。其並非旨在窮舉或將本發明限制於所揭露之精確形式。本說明書和以下申請專利範圍包括僅用於描述目的的術語，不應解釋為限制。熟習本相關領域技藝者可理解在上述教式下，許多修改和變化是可能的。熟習本領域技藝者將認得圖中所示的各種元件之各種等同組合和替換。因此，本發明的範圍旨在不受該詳細描述的限制，而是受所附申請專利範圍的限制。
10‧‧‧基板
100‧‧‧膜
102‧‧‧膜
104‧‧‧特徵部
106‧‧‧場區
108‧‧‧側壁
110‧‧‧共形釕金屬層
112‧‧‧空隙
114‧‧‧額外的釕金屬
200‧‧‧膜
202‧‧‧共形釕金屬層
206‧‧‧場區
214‧‧‧額外的釕金屬
藉著參考下列詳細說明並結合附圖來思考，可對本發明有更完整的了解，且其許多優點更顯清楚且更易瞭解，在附圖中：
圖1A～1D為示意性的剖面圖，說明根據本發明之一實施例中之特徵部的釕金屬填補；
圖2A～2C顯示掃瞄式電子顯微鏡（SEM）之剖面影像圖，說明根據本發明之一實施例中之特徵部的釕金屬填補。

Claims (20)

  1. 一種釕(Ru)金屬填補的方法，其步驟包含： 提供一基板，於該基板內包含複數特徵部； 於該等特徵部中沉積一釕金屬層， 移除該等特徵部之開口周圍之場區的該釕金屬層；以及 於該等特徵部中沉積額外的釕金屬，其中該額外釕金屬係以高於沉積在該場區上的速率而沉積在該等特徵部中。
  2. 根據申請專利範圍第1項之釕(Ru)金屬填補的方法，其中該額外釕金屬係沉積直至該等特徵部完全充滿釕金屬為止。
  3. 根據申請專利範圍第1項之釕(Ru)金屬填補的方法，其中該等特徵部具有一側壁及一底部，該側壁包含一倒置式輪廓區域，其相對於從該等特徵部之頂部延伸至該等特徵部之該底部的方向。
  4. 根據申請專利範圍第1項之釕(Ru)金屬填補的方法，其中該移除步驟包含將該基板暴露至一電漿激發乾式蝕刻製程。
  5. 根據申請專利範圍第4項之釕(Ru)金屬填補的方法，其中該電漿激發乾式蝕刻製程包含將該基板暴露至一電漿激發蝕刻氣體，該電漿激發蝕刻氣體包含含氧氣體以及任選之含鹵氣體。
  6. 根據申請專利範圍第1項之釕(Ru)金屬填補的方法，其步驟更包含： 於沉積該釕金屬層之前，先於該等特徵部中形成一成核層，其中該成核層係選自由下列成分所組成之族群：Mo、 MoN、 Ta、 TaN、 TaAlN、 W、 WN、 Ti、 TiN 以及 TiAlN。
  7. 根據申請專利範圍第1項之釕(Ru)金屬填補的方法，其中該釕金屬層以及該額外釕金屬係藉由原子層沉積法（ALD）或化學蒸氣沉積法（CVD）來沉積。
  8. 根據申請專利範圍第7項之釕(Ru)金屬填補的方法，其中該釕金屬層係藉由CVD並利用Ru3 (CO)12 以及CO載氣來進行保形沉積。
  9. 根據申請專利範圍第1項之釕(Ru)金屬填補的方法，其步驟更包含熱處理該基板，以將該特徵部中之該釕金屬層回流。
  10. 根據申請專利範圍第9項之釕(Ru)金屬填補的方法，其中該熱處理係於基板溫度介於200℃至600℃之間執行。
  11. 一種釕(Ru)金屬填補的方法，其步驟包含： 提供一基板，於該基板內包含複數特徵部； 於該等特徵部中沉積一釕金屬層，其中沉積該釕金屬層的步驟會在該等特徵部充滿該釕金屬層之前夾止該等特徵部之開口，藉此於該等特徵部中形成空隙； 移除引起該夾止的多餘釕金屬，其中該移除步驟係移除該等特徵部之開口周圍之場區的該釕金屬層；以及 於該等特徵部中沉積額外的釕金屬，其中該額外釕金屬係以高於沉積在該場區上的速率而沉積在該等特徵部中。
  12. 根據申請專利範圍第11項之釕(Ru)金屬填補的方法，其中該額外釕金屬係沉積直至該等特徵部完全充滿釕金屬為止。
  13. 根據申請專利範圍第11項之釕(Ru)金屬填補的方法，其中該等特徵部具有一側壁及一底部，該側壁包含一倒置式輪廓區域，其相對於從該等特徵部之頂部延伸至該等特徵部之該底部的方向。
  14. 根據申請專利範圍第11項之釕(Ru)金屬填補的方法，其中該移除步驟包含將該基板暴露至一電漿激發乾式蝕刻製程。
  15. 根據申請專利範圍第14項之釕(Ru)金屬填補的方法，其中該電漿激發乾式蝕刻製程包含將該基板暴露至一電漿激發蝕刻氣體，該電漿激發蝕刻氣體包含含氧氣體以及任選之含鹵氣體。
  16. 根據申請專利範圍第11項之釕(Ru)金屬填補的方法，其步驟更包含： 於沉積該釕金屬層之前，先於該等特徵部中形成一成核層，其中該成核層係選自由下列成分所組成之族群：Mo、 MoN、 Ta、 TaN、 TaAlN、 W、 WN、 Ti、 TiN 以及 TiAlN。
  17. 根據申請專利範圍第11項之釕(Ru)金屬填補的方法，其中該釕金屬層以及該額外釕金屬係藉由原子層沉積法（ALD）或化學蒸氣沉積法（CVD）來沉積。
  18. 根據申請專利範圍第17項之釕(Ru)金屬填補的方法，其中該釕金屬層係藉由CVD並利用Ru3 (CO)12 以及CO載氣來進行保形沉積。
  19. 根據申請專利範圍第11項之釕(Ru)金屬填補的方法，其步驟更包含熱處理該基板，以將該特徵部中之該釕金屬層回流。
  20. 根據申請專利範圍第19項之釕(Ru)金屬填補的方法，其中該熱處理係於基板溫度介於200℃至600℃之間執行。
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