TW201919148A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TW201919148A TW201919148A TW107124270A TW107124270A TW201919148A TW 201919148 A TW201919148 A TW 201919148A TW 107124270 A TW107124270 A TW 107124270A TW 107124270 A TW107124270 A TW 107124270A TW 201919148 A TW201919148 A TW 201919148A
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- layer
- sacrificial
- semiconductor device
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- manufacturing
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- 238000000034 method Methods 0.000 title claims abstract description 121
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
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Classifications
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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Abstract
一種半導體裝置之製造方法包括提供一基底,其具有:一導電柱體;一介電層,位於導電柱體上;以及複數個犧牲塊體,位於介電層上,上述犧牲塊體於上視角度中圍繞導電柱體。沉積一犧牲層以覆蓋上述犧牲塊體,犧牲層具有一凹口位於導電柱體正上方。沉積一硬式罩幕層於犧牲層上。自凹口底部去除一部分的硬式罩幕層。以硬式罩幕層作為蝕刻罩幕來蝕刻凹口的底部,藉以露出導電柱體的上表面。形成一導電材料於凹口內,導電材料實體接觸於導電柱體的上表面。
Description
本實施例係關於一種半導體技術,且特別是關於一種半導體裝置及其製造方法。
半導體積體電路(IC)工業已經經歷了快速增長。而IC材料和設計方面的技術進展也已經產生了多個IC世代。每一世代IC都比前一世代IC具有更小和更複雜的電路。在IC演進的過程中,功能密度(即,每晶片面積的內連裝置的數量)普遍增大,而幾何尺寸(即,可以使用製造製程產生的最小部件(或線))卻減小。這種按比例縮小製程通常因生產效率提高及相關成本降低而帶來了益處。上述按比例縮小製程也已增加處理和製造IC的複雜度,而因應這些進展,IC製造及加工需要類似的演進。
舉例來說,相變化記憶體係以一電流通路經過加熱元件而快速加熱及焠火相變化材料進而轉成非晶體或晶體狀態下進行操作,且通常希望將加熱元件盡可能製作的越小。緊密的加熱元件(例如由氮化鈦(TiN)構成的介層連接窗與相變化材料實體連接)因其較小的尺寸而有助於降低相變化記憶體的形成因子,且因其較高的加熱效率也增加了相變化記憶體的速度。然而,當半導體進展至更小尺寸,不限於相變化記 憶體,用於圖案化介層連接窗的傳統光阻方法會受限於解析度及光阻成分,其可能遭受光阻殘渣及不佳的關鍵圖形尺寸均一性(critical dimension uniformity,CDU)等問題。因此,儘管現有介層連接窗的製作方法能夠滿足其使用目的,但尚未能夠達到全面性的滿足。
一種半導體裝置之製造方法,包括:提供一基底,其具有一導電柱體、位於導電柱體上的一介電層以及位於介電層上的複數個犧牲塊體,犧牲塊體於上視角度中圍繞導電柱體;沉積一犧牲層,以覆蓋犧牲塊體,犧牲層具有一凹口位於導電柱體正上方;沉積一硬式罩幕層於犧牲層上;自凹口的底部去除一部分的硬式罩幕層;以硬式罩幕層作為蝕刻罩幕來蝕刻凹口的底部而露出導電柱體的上表面;以及形成一導電材料於凹口內,導電材料與導電柱體的上表面實體連接。
一種半導體裝置之製造方法,包括:提供一半導體基底,其具有一下電極;形成一化學機械研磨停止層於半導體基底上;形成一第一犧牲層於化學機械研磨停止層上;圖案化第一犧牲層,以形成複數個犧牲塊體,其於上視角度中圍繞下電極;形成一第二犧牲層於犧牲塊體上,其中第二犧牲層具有一凹口位於下電極的正上方;自凹口的底部去除一部分的第二犧牲層,以露出位於凹口的底部的化學機械研磨停止層;經由凹口的底部蝕刻化學機械研磨停止層,以形成一介層洞於化學機械研磨停止層內;以及於介層洞內填入一導電材料,其中導電材料與下電極實體連接。
一種半導體裝置,包括:一基底;一下電極,位於基底內;一介電層,位於介電層上;一導電介層連接窗,穿過介電層,導電介層連接窗與下電極實體連接且具有一寬高比小於1.0;一硫族化合物材料層,位於導電介層連接窗上;以及一上電極,位於硫族化合物材料層上。
100‧‧‧半導體裝置
102‧‧‧基底
104a‧‧‧相變化隨機存取記憶(PCRAM)區
104b‧‧‧周邊區
106‧‧‧PCRAM單元
108a‧‧‧導電柱體/下電極
108b‧‧‧導電柱體
110‧‧‧第一介電層
116‧‧‧(下)介層連接窗/加熱元件
120‧‧‧第二介電層
124‧‧‧相變化條
128‧‧‧上電極
132a、132b‧‧‧介層連接窗
136a、136b‧‧‧金屬線
200‧‧‧方法
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230‧‧‧操作步驟
300‧‧‧(半導體)裝置
302‧‧‧基底
304a‧‧‧第一區/PCRAM區
304b‧‧‧第二區/周邊區
308a、308b‧‧‧(下)電極/導電柱體
310‧‧‧介電層/CMP停止層
320‧‧‧第一犧牲層
320a‧‧‧犧牲塊體
330‧‧‧第二犧牲層
336‧‧‧介電凸塊
340‧‧‧凹口
350‧‧‧硬式罩幕層
354‧‧‧介層洞
356‧‧‧導電材料層
360‧‧‧底層介層連接窗
370‧‧‧相變化材料層
370a‧‧‧相變化條
374‧‧‧電極層
374a‧‧‧上電極
380‧‧‧第二介電層
382a、382b‧‧‧介層連接窗
384a、384b‧‧‧金屬線
390‧‧‧PCRAM單元
h1、h2、h3、h4、Thm‧‧‧厚度
H‧‧‧高
w1、w4‧‧‧寬度
w2‧‧‧距離
W‧‧‧寬
第1圖係繪示出根據一些實施例之具有相變化隨機存取記憶(phase-change random access memory,PCRAM)單元的半導體裝置的剖面示意圖。
第2A及2B圖係繪示出根據各種不同型態之具有相變化隨機存取記憶(PCRAM)單元的半導體裝置製造方法流程圖。
第3、4、5A、5B、5C、5D、6、7、8、9、10、11、12、13、14及15圖係繪示出根據一些實施例之以第2A及2B圖的方法形成具有相變化隨機存取記憶(PCRAM)單元的半導體裝置的剖面示意圖。
以下的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化本揭露內容。當然,這些僅為範例說明並非用以限定本發明。舉例來說,若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方,即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例,亦包含了尚可將附加的 特徵部件形成於上述第一特徵部件與上述第二特徵部件之間,而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外,本揭露內容在各個不同範例中會重複標號及/或文字。重複是為了達到簡化及明確目的,而非自行指定所探討的各個不同實施例及/或配置之間的關係。
再者,在空間上的相關用語,例如”下方”、”之下”、”下”、”上方”、”上”等等在此處係用以容易表達出本說明書中所繪示的圖式中元件或特徵部件與另外的元件或特徵部件的關係。這些空間上的相關用語除了涵蓋圖式所繪示的方位外,還涵蓋裝置於使用或操作中的不同方位。此裝置可具有不同方位(旋轉90度或其他方位)且此處所使用的空間上的相關符號同樣有相應的解釋。更進一步,當一數字或數字範圍的敘述加入了”約”、”近似於”等用語,該用語除非特別指出,否則是指數值包含所述數值的+/-10%。舉例來說,”約5nm”的用語包含大小範圍為4.5nm至5.5nm。
本揭露係有關於半導體裝置中的介層連接窗(via)結構及其製造方法。具體來說,本揭露係有關於提供底層介層連接窗(bottom via)作為相變化記憶單元中的加熱元件的方法及結構。相變化記憶體,如熟習的相變化隨機存取記憶體(PCRAM),其為一種非揮發記憶體且其中,相變化材料(在一些實施例中為硫族化合物(cjalcogenide)半導體)係用於儲存態。相變化材料中功能區的狀態係於晶體與非晶體之間切換。舉例來說,透過電流通過加熱元件,其產生熱。在晶體狀態中,相變化材料具有低電阻率,而在非晶體狀態中,其具有 高電阻率。在某溫度範圍中相變化材料於晶體與非晶體兩狀態中皆為穩定,且可透過熱激發而在兩狀態之間來回切換。相變化材料於非晶體與晶體狀態中電阻率比通常大於1000,且功能區的狀態用於表示儲存資料。舉例來說,在熱激發之後,若功能區為晶體狀態,則儲存資料為低邏輯電位(logic level)(例如,低),但若功能區為非晶體狀態,則儲存資料為高邏輯電位(例如,高)。PCRAM具備數個操作及工程上的優勢,包括高速、低功耗、非揮發、高密度及低成本。舉例來說,PCRAM裝置為非揮發性且可快速寫入(例如少於50奈秒內)。PCRAM單元可具有高密度且相容於CMOS邏輯,且通常比其他種類的記憶單元製造成本低。
第1圖係繪示出根據一些實施例之具有PCRAM單元的半導體裝置100的剖面示意圖。半導體裝置100包括一基底102(局部繪示於第1圖)。基底102可為由半導體材料(例如矽、矽鍺、砷化鍺及其相似物)所形成的半導體基底,且可為一塊材基底或絕緣層覆半導體(semiconductor-on-insulator)基底。半導體裝置100包括PCRAM區104a(其中形成有一或多個PCRAM單元)以及一周邊區104b(其可為邏輯電路區,包括但不限於PCRAM單元的控制電路)。
基底102包括一或多個導電柱體108a及108b。導電柱體108a及108b可由鎢(W)、鋁(Al)、銅(Cu)、AlCu及/或其他適合的導電材料所形成。導電柱體108a及108b的製作可包括單鑲嵌製程或雙鑲嵌製程。又一實施例中,導電柱體108a及108b由多晶矽及/或其他適合材料所形成。在一些實施 例中,導電柱體108a及108b為形成於內層介電(inter-layer dielectric,ILD)層內的接觸插塞,用以接入位於基底100下層內的電晶體(未繪示)的源極/汲極區及/或閘極電極。在PCRAM區104a內,導電柱體108a也稱作PCRAM單元106的下電極108a。
在PCRAM區104a內,介層連接窗(via)116與下電極108a電性連接,且被第一介電層110所圍繞。在一些實施例中,第一介電層110由碳化矽(SiC)、氮化矽(Si3N4)及/或其他適合材料所形成。在一些實施例中,介層連接窗116由氮化鈦(TiN)、鎢(W)、氮化鉭(TaN)及/或其他適合材料所形成。當介層連接窗116疊置於相變化條124下方時,介層連接窗116也稱作PCRAM單元106的下介層連接窗116。介層連接窗116也可稱作PCRAM單元106的加熱元件116,當電流流經介層連接窗116而產生熱,將會導致相變化條124的狀態改變。相變化條124與下介層連接窗116電性連接。相變化條124包括相變化材料,例如硫族化合物材料及/或化學計量(stoichiometric)材料。在一些實施例中,相變化條124包括但不限於鍺(Ge)、碲(Te)及銻(Sb)。在一範例中,相變化條124包括GeSbTe合金、AgInSbTe合金或氧化鉿化合物。
在PCRAM區104a內,上電極128疊置於相變化條124並與其電性連接。在一些實施例中,上電極128由TiN、TaN及/或其他適合材料所形成。相變化條124及上電極128可被第二介電層120所圍繞。第二介電層120可為內層介電(ILD)層或金屬層間介電(inter-metal dielectric,IMD)層。在一些實施例中,第一及第二介電層110及120包括不同材料組成。在一 些實施例中,第一及第二介電層110及120包括相同材料(例如,Si3N4),使第一及第二介電層110及120區域之間無邊界且彼此接觸。
在一些實施例中,相變化隨機存取記憶(PCRAM)單元106更包括被第二介電層120圍繞的介層連接窗132a及金屬線136a,其將上電極128電性連接至上層金屬層(未繪示)及/或其他金屬內連線。介層連接窗132a及金屬線136a可由Al、Cu、AlCu、W及/或其他適合導電材料所形成。介層連接窗132a及金屬線136a的製作可包括雙鑲嵌製程。相似地,在周邊區104b內,介層連接窗132b及金屬線136b穿過第一介電層110而電性連接至導電柱體108b。
在一PCRAM單元106內,當電流流經下介層連接窗116及相變化條124,因下介層連接窗116具有高電阻率而可在下介層連接窗116內產生充足的熱,使相變化條124改變狀態。下介層連接窗116的熱效率為影響PCRAM單元的寫入速度主要因素之一。具有低寬高(width-to-height)比的下介層連接窗結構的電阻率高於具有高寬高比的下介層連接窗結構。在一些實施例中,下介層連接窗116具有一寬高比(如第1圖所示的W/H),其小於1.0。在一些實施例中,下介層連接窗116具有一寬高比約在0.2至1.0的範圍。在一範例中,下介層連接窗116具有一寬高比約為0.4。在另一實施例中,下介層連接窗116具有一寬高比約在0.1至0.2的範圍。下介層連接窗116的高度可約在20nm至100nm的範圍,例如約為50nm。
第2A及2B圖係繪示出根據一些實施例之半導體裝 置之製造方法200的流程圖。方法200為一範例而並非侷限本揭露而超出保護範圍以外。額外的操作步驟可在進行方法200之前、期間或之後進行,且所述的某些操作步驟可於其他實施例方法中被取代、消除或重置。以下所述的方法200係配合相關的第3至15圖,其繪示出根據方法200的實施例於半導體裝置300不同製造步驟期間的剖面示意圖。半導體裝置300在諸多方面可實質上相似於第1圖的半導體裝置100。
半導體裝置300可為積體電路(IC)製程期間所製造的中間裝置或是部分裝置,可包括靜態隨機存取記憶體(static random access memory,SRAM)及/或邏輯電路、被動部件(例如,電阻器、電容器及電感器)以及主動部件(例如,p型場效電晶體(pFETs)、n型場效電晶體(nFETs)、鰭式場效電晶體(FinFETs)、金屬氧化物半導體場效電晶體(MOSFETs)、互補式金屬氧化物半導體(CMOS)場效電晶體、雙極電晶體、高壓電晶體、高頻電晶體、其他記憶單元及其組合)。再者,可在各種不同實施例中,提供各種特徵部件包括電晶體、閘極堆疊、主動區、隔離結構及其他特徵部件以達到簡化及易於瞭解目的而無須限定實施例為任何形式的裝置、任何裝置數量、任何區域或任何結構或區域配置。
於操作步驟202中,方法200提供了一半導體裝置300的前體。為了便於說明,半導體裝置300的前體也稱作裝置300。裝置300可包括基底302及各種不同的特徵部件形成於其內或其上。在說明的實施例中基底302為矽基底。或者,基底302可包括其他元素半導體(例如,鍺)、化合物半導體(包 括:碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、合金半導體(包括:SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaAnIsP)、或其組合。在另一實施例中,基底302為半導體覆絕緣層(semiconductor on insulator,SOI)。
基底302包括第一區304a及第二區304b。第一區304a可稱作PCRAM區304a,其中形成有PCRAM單元,且第二區304b可稱作周邊區304b,其中形成有PCRAM單元的控制電路及其他邏輯電路。基底302也包括一或多個電極(或下電極)308a及308b分別位於第一區304a及第二區304b內。在全文說明中,電極308a及308b也稱作導電柱體308a及308b。在一些實施例中,導電柱體308a及308b為接觸插塞,用以接入位於基底302下層內的電晶體(未繪示)的源極/汲極區及/或閘極電極。基底102可更包括ILD層,其圍繞導電柱體308a及308b。導電柱體308a及308b的製作可包括單鑲嵌或雙鑲嵌製程,期間形成ILD層,接著形成開口以及填入金屬材料於開口內。之後進行化學機械研磨(chemical mechanical polish,CMP)製程,以去除多餘金屬材料而留下導電柱體308a及308b。導電柱體308a及308b可由Al、AlCu、W、或其他金屬材料所形成。在另一實施例中,導電柱體308a及308b由多晶矽所形成。由於製程上的原因,每一導電柱體308a及308b可具有漸細的剖面輪廓,其上部寬於各自的下部。
請再參照第3圖,於操作步驟204中,方法200(第2A圖)形成一介電層310於基底上。在後續的操作步驟中,介 電層310作為形成於其上方的其他材料層的CMP停止層。因此,介電層310也可稱作CMP停止層310。介電層310可包括一介電材料,例如SiC、Si3N4、氮氧化矽(SiON)、及/或氧化矽。在所示的實施例中,介電層310包括SiC。介電層310可形成為任何適當的厚度並由任何適合的製程形成,包括化學氣相沉積製程(chemical vapor deposition,CVD)、低壓化學氣相沉積(low-pressure CVD,LPCVD)、高密度電漿化學氣相沉積(high density plasma CVD,HDPCVD)、物理氣相沉積製程(physical vapor deposition,PVD)、原子層沉積(atomic layer deposition,ALD)、及/或其他適合的沉積製程。在所示的實施例中,介電層310的厚度約在20nm至100nm之間,例如50nm。
於操作步驟206中,方法200(第2A圖)形成一第一犧牲層320於介電層310上(第4圖)。第一犧牲層320可包括一介電材料,例如Si3N4、四乙基矽酸鹽氧化物(TEOS oxide)、氧化矽、SiON、氮碳化矽(SiCN)、氮氧碳化矽(SiCON)、其他介電材料、或其組合。選擇第一犧牲層320的成分,使第一犧牲層320對於介電層310具有若干的蝕刻選擇比。在一些實施例中,第一犧牲層320包括氮化矽。第一犧牲層320可形成為任何適當的厚度並由任何適合的製程形成,包括:CVD、LPCVD、HDPCVD、PVD、ALD、及/或其他適合的沉積製程。在所示的實施例中,第一犧牲層320的厚度約在20nm至80nm之間,例如50nm。
於操作步驟208中,方法200(第2A圖)圖案化第一犧牲層320,以形成多個犧牲塊體320a,其於PCRAM區304a 的上視角度來看,圍繞導電柱體308a(第5A及5B圖)。第5A圖係繪示出裝置300沿著第5B圖的A-A線的剖面示意圖,而第5B圖係繪示出裝置300的PCRAM區304a的上視平面示意圖。為了圖案化第一犧牲層320,操作步驟208可包括各個不同的製程,例如微影及蝕刻。微影製程可包括形成一光阻(未繪示)於第一犧牲層320上。一例示性光阻包括對於光線(例如,UV光、深紫外光(DUV)、及/或EUV)的敏感光敏材料。對裝置300進行微影曝光(將光阻選擇區域暴露於光線中)。曝光導致光阻曝光區域發生化學反應。於曝光之後,施加顯影劑至光阻。顯影劑在正型光阻顯影製程溶解或去除曝光區域或在負型光阻顯影製程溶解或去除未曝光區域。適合的正型顯影劑包括:TMAH(tetramethyl ammonium hydroxide)、KOH及NaOH。適合的負型顯影劑包括溶劑,例如乙酸正丁酯(n-butyl acetate)、乙醇、己烷、苯及甲苯。於顯影光阻之後,第一犧牲層320的露出區域可透過蝕刻製程去除,例如濕蝕刻、乾蝕刻、反應離子蝕刻(reactive ion etching,RIE)、灰化、及/或其他適合的蝕刻製程。選擇一蝕刻劑,其以第一犧牲層320的材料組成為標的物,同時不對介電層310蝕刻,而維持介電層310覆蓋導電柱體308a及308b。在所示的實施例中,去除周邊區304b的第一犧牲層320,同時留下PCRAM區304a的部分的第一犧牲層320而形成圖案化的第一犧牲層320,其由多個犧牲塊體320a組成。在進行蝕刻之後,去除光阻。
請再參照第5A及5B圖,犧牲塊體320a交錯於相鄰的導電柱體308a之間,使每一導電柱體308a被多個犧牲塊體 320a圍繞(或包圍)。多個犧牲塊體320a對於所圍繞的導電柱體308a為等距排列的。在所示的實施例中,每一導電柱體308a被四個犧牲塊體320a圍繞。在另一實施例中,每一導電柱體308a被三個犧牲塊體320a圍繞,如第5C圖所示。在不同的實施例中,每一導電柱體308a被適當數量的犧牲塊體320a圍繞,例如五個或五個以上。如一範例中,第5D圖係繪示出每一導電柱體308a被五個犧牲塊體320a圍繞的實施例。
在所示的實施例中,犧牲塊體320a具有圓柱外型。在其他實施例中,犧牲塊體320a可具有不同外型,例如上視為方型或其他多邊型。在所示的實施例中,犧牲塊體320a與對應的導電柱體308a在上視角度重疊。在一些實施例中,重疊區域可小於對應的導電柱體308a的上表面積的20%。又一些實施例中,重疊區域可小於對應的導電柱體308a的上表面積的5%。又另一實施例中,犧牲塊體320a的側壁自對應的導電柱體308a的邊緣偏移,使犧牲塊體320a與對應的導電柱體308a在上視角度並未重疊。
於操作步驟210中,方法200(第2A圖)形成一第二犧牲層330於裝置300上以覆蓋PCRAM區304a及周邊區304b(第6圖)。在所示的實施例中,第二犧牲層330為一毯覆層而位於犧牲塊體320a的上表面及側壁且位於露出的介電層310上表面上。用於第二犧牲層330的適合的介電材料包括Si3N4、TEOS氧化物、氧化矽、SiON、SiCN、SiCON、其他介電材料、或其組合。上述介電材料可利用適合的技術進行沉積,包括:CVD、LPCVD、HDP-CVD、PVD、或ALD。在許多方面,第二 犧牲層330可實質上相似於第一犧牲層320,且可於裝置300上進行相似的沉積製程以沉積第二犧牲層330。在所示的實施例中,第二犧牲層330包括與第一犧牲層320(例如,Si3N4)相同的材料組成,使第二犧牲層330與第一犧牲層320之間無邊界,且與犧牲塊體320a彼此接觸。又另一實施例中,第二犧牲層330與第一犧牲層320包括不同的材料組成。如在一範例中,第一犧牲層320包括Si3N4而第二犧牲層330可包括TEOS,或第一犧牲層320包括TEOS而第二犧牲層330可包括Si3N4。
請再參照第6圖,在沉積介電材料成為毯覆層時,第二犧牲層330形成介電凸塊336於犧牲塊體320a的位置上。在一些實施例中,介電凸塊336去有彎曲側壁。相鄰的介電凸塊336(由犧牲塊體320a所定義出)圍繞一對應的導電柱體308a,且底部彼此相連而於對應的側壁之間形成凹口340。凹口340具有漸細的剖面輪廓,其底部為最窄部而頂部為最寬部。在一些實施例中,凹口340的底部低於周邊區304b內的第二犧牲層330的上表面。在不同的實施例中,凹口340位於導電柱體308a正上方。在一範例中,凹口340位於導電柱體308a中心的正上方。為了簡化目的,犧牲塊體320a的厚度表示為h1;介電凸塊336頂部的第二犧牲層330厚度表示為h2;位於凹口340底部的第二犧牲層330的厚度表示為h3;導電柱體308a的上表面的寬度表示為w1;兩相鄰的介電凸塊336的頂部之間距離表示為w2;自側壁(此處第二犧牲層330的厚度(h4)為h2的一半(h4=h2/2))量測的凹口334的寬度表示為w4。在一些實施例中,h3/h1的比值約為0.2至1.0;h2/h1的比值約為1.5至3.0;w4/w1的比值約為 0.1至0.4;且w4/w2的比值約為0.05至0.4。在一範例中,h3/h1的比值約為0.5;h2/h1的比值約為2;w4/w1的比值約為0.3;且w4/w2的比值約為0.2。
於操作步驟212中,方法200(第2A圖)形成一硬式罩幕層350於裝置300上,以覆蓋PCRAM區304a及周邊區304b(第7圖)。在所示的實施例中,硬式罩幕層350沉積為一毯覆層,位於介電凸塊336上及位於凹口340的底部及側壁上。硬式罩幕層350可包括:TiN、TaN、W、Si3N4、SiC、氧化矽、SiON、SiCN、SiCON、其他適合材料、或其組合。選擇硬式罩幕層350的成分,使硬式罩幕層350對於第二犧牲層330具有若干的蝕刻選擇比。在所示的實施例中,硬式罩幕層350包括TiN。在一些實施例中,硬式罩幕層350由CVD製程沉積而成。由於CVD製程的填洞能力,凹口340上部比其下部更容易聚積沉積材料。再者,凹口340側壁的漸細剖面輪廓防止凹口340在其底部被覆蓋前,凹口340的上開口因CVD製程而封閉。可調整CVD製程的參數(例如,壓力、溫度及氣體黏度),使臣機材料的填洞行為維持為凹口340的底部的硬式罩幕層350薄於側壁上的硬式罩幕層350。在一些實施例中,CVD製程採用設定壓力小於0.8torr及溫度高於攝氏80度,使硬式罩幕層350的材料沉積並未封閉凹口340的底部而留下凹口340的底部的沉積層薄於側壁上的沉積層。位於介電凸塊336上及位於凹口340的底部及側壁上的各個不同部分的硬式罩幕層350具有不同厚度。當位於第二犧牲層330的平坦表面部分,硬式罩幕層350於PCRAM區304a及周邊區304b兩處具有實質不變的厚度,並表示為Thm, 如第7圖所示。硬式罩幕層350的厚度Thm約在20nm至100nm的範圍,例如60nm。
於操作步驟214中,方法200(第2A圖)蝕刻硬式罩幕層350,以露出凹口340的底部(第8圖)。由於硬式罩幕層350位於凹口340底部的部分薄於別處,因此底部相較於別處更易於蝕刻去除,因而造成位於凹口340底部的第二犧牲層330露出,而第二犧牲層330的其他部分仍被硬式罩幕層350所覆蓋。上述蝕刻製程可包括任何適合的蝕刻技術,例如濕蝕刻、乾蝕刻、RIE、灰化、及/或其他蝕刻方法。選擇的蝕刻劑以抵抗蝕刻第二犧牲層330。舉例來說,乾蝕刻製程以含氧氣體、含氟氣體(例如,CF4、SF6、CH2F2、CHF3、及/或C2F6)、含氯氣體(例如,Cl2、CHCl3、CCl4、及/或BCl3)、含溴氣體(例如,HBr及/或HBr3)、含碘氣體、其他適合氣體及/或電漿、及/或其組合來實施。舉例來說,濕蝕刻製程可包括蝕刻於稀釋氫氟酸(diluted hydrofluoric acid,DHF)、氫氧化鉀(potassium hydroxide,KOH)溶液、氨水(ammonia)、含氫氟酸(HF)、硝酸(HNO3)、及/或醋酸(CH3COOH)溶液、或其他適合的溼式蝕刻劑。在所示的實施例中,操作步驟212包括由時間控制的濕蝕刻製程以將硬式罩幕層350薄化並僅將凹口340的底部打開。
於操作步驟216中,方法200(第2A圖)以硬式罩幕層350作為蝕刻罩幕來蝕刻第二犧牲層330(第9圖)。凹口340在上述蝕刻製程中向下延伸並露出位於凹口340底部的介電層310。上述蝕刻製程可包括任何適合的蝕刻技術,例如濕 蝕刻、乾蝕刻、RIE、灰化、及/或其他蝕刻方法。選擇一蝕刻劑,其以第二犧牲層330的材料組成為標的物,同時不對硬式罩幕層350及介電層310蝕刻,而實質保留位於凹口340側壁上的硬式罩幕層350及位於凹口340底部的介電層310。介電層310維持覆蓋導電柱體308a及308b。
於操作步驟218中,方法200(第2B圖)以第二犧牲層330作為蝕刻罩幕來蝕刻介電層310(第10圖)。凹口340在上述蝕刻製程中進一步向下延伸並露出位於凹口340底部的導電柱體308a。於操作步驟218中導電柱體308a也作為蝕刻停止層。自凹口340底部去除介電層310可包括任何適合的蝕刻技術,例如濕蝕刻、乾蝕刻、RIE、灰化、及/或其他蝕刻方法。在一些實施例中,選擇一蝕刻劑,使介電層310與第二犧牲層330具有高蝕刻選擇比。舉例來說,介電層310與第二犧牲層330之間的蝕刻選擇比約為5:1或更高,例如5:1至20:1。凹口340底部被介電層310圍繞的部分形成介層洞354,其位於導電柱體308a正上方。介層洞354內於後續製程中填入導電材料,以形成PCRAM單元的加熱元件。根據以上所述,介層洞354的製作主要為自對準製程而無使用微影圖案化(除製作犧牲塊體320a以外),且可得到具有相對低的寬高比的介層洞。在一些實施例中,介層洞354的寬高比低於1.0。又一些實施例中,介層洞354的寬高比約在0.2至1.0的範圍。在一範例中,介層洞354的寬高比約為0.4。在另一實施例中,介層洞354的寬高比約在0.1至0.2的範圍。
於操作步驟220中,方法200(第2B圖)於介層洞 354內填入導電材料(第11圖)。填入介層洞354可包括沉積一導電材料層356於裝置300上,以覆蓋PCRAM區304a及周邊區304b。適合導電材料層356的導電材料包括:TiN、TaN、W、其他適合材料、或其組合。導電材料層356可利用任何適合的技術進行沉積,包括:電鍍、CVD、LPCVD、HDP-CVD、PVD、或ALD。在所示的實施例中,導電材料層356利用ALD製程進行沉積,好處在於ALD製程的填洞能力強,以填入具有高深寬比的凹口340的底部。在一些實施例中,導電材料層356與硬式罩幕層350包括不同的材料組成。在一範例中,導電材料層356可包括TiN,而硬式罩幕層350可包括SiC,或導電材料層356可包括TaN,而硬式罩幕層350可包括TiN。在所示的實施例中,導電材料層356包括與硬式罩幕層350相同的材料組成,例如TiN,使導電材料層356與硬式罩幕層350之間無邊界,且與硬式罩幕層350接觸。導電材料層356填入被介電層310圍繞的介層洞354而提高凹口340的底部。在一些實施例中,提高的凹口340底部高於犧牲塊體320a的上表面。在一些實施例中,提高的凹口340底部低於犧牲塊體320a的上表面,但高於犧牲塊體320a的下表面。
於操作步驟222中,方法200(第2B圖)進行一或多道化學機械研磨(CMP)製程,以研磨裝置300並露出介電層310(第12圖)。在上述CMP製程中介電層310作為CMP停止層。在進行上述CMP製程之後,去除了介電層310上方的材料層(例如,犧牲塊體320a、第二犧牲層330、硬式罩幕層350及導電材料層356)。在進行上述CMP製程之後,露出填入於介 層洞354內的導電材料,其也稱作底層介層連接窗360。底層介層連接窗360的寬高比低於1.0。又一些實施例中,底層介層連接窗360的寬高比約在0.2至1.0的範圍。在一範例中,底層介層連接窗360的寬高比約為0.4。在另一實施例中,底層介層連接窗360的寬高比約在0.1至0.2的範圍。底層介層連接窗360的高度可約在20nm至100nm的範圍,例如約為50nm。
於操作步驟224中,方法200(第2B圖)形成一相變化材料層370於裝置300上(第13圖)。相變化材料層370包括相變化材料,例如硫族化合物材料及/或化學計量材料。在一些實施例中,相變化材料層370包括鍺(Ge)、碲(Te)及銻(Sb)。在一範例中,相變化材料層370包括GeSbTe合金、AgInSbTe合金或氧化鉿化合物。相變化材料層370可利用任何適合的技術進行沉積,包括:電鍍、CVD、LPCVD、HDP-CVD、PVD、或ALD。
於操作步驟226中,方法200(第2B圖)形成一電極層374於相變化材料層370上(第13圖)。在一些實施例中,電極層374由TiN、TaN、W、及/或其他適合材料形成。電極層374可利用任何適合的技術進行沉積,包括:電鍍、CVD、LPCVD、HDP-CVD、PVD、或ALD。
於操作步驟228中,方法200(第2B圖)圖案化相變化材料層370及電極層374,以形成相變化條370a及上電極374a疊置於對應的底層介層連接窗360及導電柱體308a上(第14圖)。相變化材料層370及電極層374的圖案化可包括各個不同的製程,例如微影及蝕刻。微影製程可包括形成一光阻(未 繪示)於電極層374上;對光阻進行曝光成一圖案(其定義出一開口);進行後曝烤(post-exposure bake)製程;以及對光阻進行顯影以形成一罩幕部件。罩幕部件或其衍生物接著用於蝕刻相變化材料層370及電極層374。隨後去除罩幕部件(例如,圖案化的光阻)。上述蝕刻製程可包括使用不同蝕刻化學藥劑的多重蝕刻步驟,每一蝕刻化學藥劑以相變化材料層370及電極層374中的特定材料為標的物。上述蝕刻製程可包括一或多道乾蝕刻製程、濕蝕刻製程及其他適合的蝕刻技術。上述蝕刻製程自周邊區304b去除相變化材料層370及電極層374。
於操作步驟230中,方法200(第2B圖)進行進一步的加工,以完成PCRAM單元390的製作。舉例來說,如第15圖所示,方法200可形成一第二介電層380於裝置300上。第二介電層380可為ILD層或IMD層。在一些實施例中,介電層310及第二介電層380可包括相同材料(例如,Si3N4),使介電層310與第二介電層380之間無邊界且與第二介電層380接觸。在一些實施例中,介電層310及第二介電層380可包括不同的材料組成。舉例來說,介電層310包括SiC而第二介電層380包括SiC以外的材料,例如氧化矽、硼磷矽酸鹽玻璃(BPSG)、四乙基矽酸鹽氧化物(TEOS oxide)、未摻雜矽酸鹽玻璃、熔融石英玻璃(fused silica glass,FSG)、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、低介電常數介電材料、及/或其他適合的介電材料。第二介電層380可透過電漿輔助化學氣相沉積(plasma enhanced CVD,PECVD)製程、流動式化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)製程、或其他 適合的沉積技術進行沉積。方法200也形成介層連接窗382a及金屬線384a於PCRAM區304a內而電性連接上電極374a,以作為金屬內連接。介層連接窗382a及金屬線384a可由Al、Cu、AlCu、W、及/或其他適合導電材料形成。介層連接窗382a及金屬線384a的製作可包括雙鑲嵌製程。相似地,於周邊區304b內形成介層連接窗382b及金屬線384b並穿過介電層310而電性連接導電柱體308b。
儘管並未設限,然而一或多個實施例提供諸多益處於半導體裝置及其製造方法,包括相變化記憶單元。舉例來說,可形成具有非常低寬高比的介層連接窗作為高加熱效率的加熱元件,其提高相變化記憶單元的寫入速度。再者,所述的介層連接窗製造方法並未侷限於製造相變化記憶單元,且能夠輕易地整合於現行形成介層連接窗的半導體製程。
在一實施例中,一種半導體裝置之製造方法,包括:提供一基底,其具有一導電柱體、位於導電柱體上的一介電層以及位於介電層上的複數個犧牲塊體,犧牲塊體於上視角度中圍繞導電柱體;沉積一犧牲層,以覆蓋犧牲塊體,犧牲層具有一凹口位於導電柱體正上方;沉積一硬式罩幕層於犧牲層上;自凹口的底部去除一部分的硬式罩幕層;以硬式罩幕層作為蝕刻罩幕來蝕刻凹口的底部而露出導電柱體的上表面;以及形成一導電材料於凹口內,該導電材料與導電柱體的上表面實體連接。在一實施例中,犧牲塊體的每一者具有圓柱外型。在一實施例中,犧牲層包括與犧牲塊體相同的材料組成。在一實施例中,犧牲層與犧牲塊體包括不同的材料組成。在一實施例 中,犧牲塊體僅包括四個犧牲塊體。在一實施例中,沉積硬式罩幕層包括進行化學氣相沉積製程。在一實施例中,去除部分的硬式罩幕層包括進行濕蝕刻製程。在一實施例中,形成導電材料於凹口內包括進行原子層沉積製程。在一實施例中,位於凹口內的導電材料包括氮化鈦。在一實施例中,硬式罩幕層包括與位於凹口內的導電材料相同的材料組成。在一實施例中,上述方法更包括在形成導電材料於凹口內之後,進行化學機械研磨製程,以露出介電層的上表面。在一實施例中,在進行化學機械研磨製程之後,位於凹口內的導電材料具有一寬高比小於1.0。
在另一實施例中,一種半導體裝置之製造方法,包括:提供一半導體基底,其具有一下電極;形成一化學機械研磨停止層於半導體基底上;形成一第一犧牲層於化學機械研磨停止層上;圖案化第一犧牲層,以形成複數個犧牲塊體,其於上視角度中圍繞下電極;沉積一第二犧牲層於犧牲塊體上,其中第二犧牲層具有一凹口位於下電極的正上方;自凹口的底部去除一部分的第二犧牲層,以露出位於凹口的底部的化學機械研磨停止層;經由凹口的底部蝕刻化學機械研磨停止層,以形成一介層洞於化學機械研磨停止層內;以及於介層洞內填入一導電材料,其中導電材料與下電極實體連接。在一實施例中,自凹口的底部去除部分的第二犧牲層包括:形成一硬式罩幕層於第二犧牲層上;去除位於凹口的底部上方的一部分的硬式罩幕層,以露出部分的第二犧牲層;以及以硬式罩幕層作為蝕刻罩幕來蝕刻第二犧牲層。在一實施例中,形成硬式罩幕層 包括將硬式罩幕層沉積為位於凹口的底部的厚度小於位於凹口的側壁的厚度。在一實施例中,於介層洞內填入導電材料之後,上述方法更包括:進行一化學機械研磨製程,以去除第二犧牲層及犧牲塊體;形成一相變化材料層於化學機械研磨停止層上,其中相變化材料層與導電材料實體接觸;以及形成一上電極於相變化材料層上。在一實施例中,相變化材料層包括GeSbTe、AgInSbTe或氧化鉿。
又另一實施例中,一種半導體裝置,包括:一基底;一下電極,位於基底內;一介電層,位於介電層上;一導電介層連接窗,穿過介電層,導電介層連接窗與下電極實體連接且具有一寬高比小於1.0;一硫族化合物材料層,位於導電介層連接窗上;以及一上電極,位於硫族化合物材料層上。在一實施例中,導電介層連接窗的寬高比約在0.2至1.0的範圍。在一實施例中,介電層包括碳化矽且該導電介層連接窗包括氮化鈦。
以上概略說明了本發明數個實施例的特徵,使所屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎,以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神和保護範圍內,且可在不脫離本揭露之精神和範圍內,當可作更動、替代與潤飾。
Claims (20)
- 一種半導體裝置之製造方法,包括:提供一基底,其具有一導電柱體、位於該導電柱體上的一介電層以及位於該介電層上的複數個犧牲塊體,該等犧牲塊體於上視角度中圍繞該導電柱體;沉積一犧牲層,以覆蓋該等犧牲塊體,該犧牲層具有一凹口位於該導電柱體正上方;沉積一硬式罩幕層於該犧牲層上;自該凹口的底部去除一部分的該硬式罩幕層;以該硬式罩幕層作為蝕刻罩幕來蝕刻該凹口的該底部而露出該導電柱體的上表面;以及形成一導電材料於該凹口內,該導電材料與該導電柱體的該上表面實體連接。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該等犧牲塊體的每一者具有圓柱外型。
- 如申請專利範圍第2項所述之半導體裝置之製造方法,其中該犧牲層包括與該等犧牲塊體相同的材料組成。
- 如申請專利範圍第2項所述之半導體裝置之製造方法,其中該犧牲層與該等犧牲塊體包括不同的材料組成。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該等犧牲塊體僅包括四個犧牲塊體。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中沉積該硬式罩幕層包括進行化學氣相沉積製程。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中 去除該部分的該硬式罩幕層包括進行濕蝕刻製程。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中形成該導電材料於該凹口內包括進行原子層沉積製程。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中位於該凹口內的該導電材料包括氮化鈦。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該硬式罩幕層包括與位於該凹口內的該導電材料相同的材料組成。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,更包括:在形成該導電材料於該凹口內之後,進行化學機械研磨製程,以露出該介電層的上表面。
- 如申請專利範圍第11項所述之半導體裝置之製造方法,其中在進行該化學機械研磨製程之後,位於該凹口內的該導電材料具有一寬高比小於1.0。
- 一種半導體裝置之製造方法,包括:提供一半導體基底,其具有一下電極;形成一化學機械研磨停止層於該半導體基底上;形成一第一犧牲層於該化學機械研磨停止層上;圖案化該第一犧牲層,以形成複數個犧牲塊體,其於上視角度中圍繞該下電極;沉積一第二犧牲層於該等犧牲塊體上,其中該第二犧牲層具有一凹口位於該下電極的正上方;自該凹口的底部去除一部分的該第二犧牲層,以露出位於 該凹口的該底部的該化學機械研磨停止層;經由該凹口的該底部蝕刻該化學機械研磨停止層,以形成一介層洞於該化學機械研磨停止層內;以及於該介層洞內填入一導電材料,其中該導電材料與該下電極實體連接。
- 如申請專利範圍第13項所述之半導體裝置之製造方法,其中自該凹口的該底部去除該部分的該第二犧牲層包括:形成一硬式罩幕層於該第二犧牲層上;去除位於該凹口的該底部上方的一部分的該硬式罩幕層,以露出該部分的該第二犧牲層;以及以該硬式罩幕層作為蝕刻罩幕來蝕刻該第二犧牲層。
- 如申請專利範圍第14項所述之半導體裝置之製造方法,其中形成該硬式罩幕層包括將該硬式罩幕層沉積為位於該凹口的該底部的厚度小於位於該凹口的側壁的厚度。
- 如申請專利範圍第13項所述之半導體裝置之製造方法,其中於該介層洞內填入該導電材料之後,更包括:進行一化學機械研磨製程,以去除該第二犧牲層及該等犧牲塊體;形成一相變化材料層於該化學機械研磨停止層上,其中該相變化材料層與該導電材料實體接觸;以及形成一上電極於該相變化材料層上。
- 如申請專利範圍第16項所述之半導體裝置之製造方法,其中該相變化材料層包括GeSbTe、AgInSbTe或氧化鉿。
- 一種半導體裝置,包括: 一基底;一下電極,位於該基底內;一介電層,位於該介電層上;一導電介層連接窗,穿過該介電層,該導電介層連接窗與該下電極實體連接且具有一寬高比小於1.0;一硫族化合物材料層,位於該導電介層連接窗上;以及一上電極,位於該硫族化合物材料層上。
- 如申請專利範圍第18項所述之半導體裝置,其中該導電介層連接窗的該寬高比約在0.2至1.0的範圍。
- 如申請專利範圍第18項所述之半導體裝置,其中該介電層包括碳化矽且該導電介層連接窗包括氮化鈦。
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