TW201906095A - 封裝及其形成方法 - Google Patents

封裝及其形成方法 Download PDF

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Publication number
TW201906095A
TW201906095A TW106143107A TW106143107A TW201906095A TW 201906095 A TW201906095 A TW 201906095A TW 106143107 A TW106143107 A TW 106143107A TW 106143107 A TW106143107 A TW 106143107A TW 201906095 A TW201906095 A TW 201906095A
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Taiwan
Prior art keywords
die
package
encapsulating material
thermally conductive
underfill
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TW106143107A
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TWI648826B (zh
Inventor
林俊成
鄭禮輝
蔡柏豪
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台灣積體電路製造股份有限公司
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Publication of TWI648826B publication Critical patent/TWI648826B/zh
Publication of TW201906095A publication Critical patent/TW201906095A/zh

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Abstract

一種方法包括：在載體之上形成釋放膜；藉由晶粒貼合膜將裝置貼合於所述釋放膜之上；將所述裝置包封於包封材料中；對所述包封材料執行平面化以暴露出所述裝置；自所述載體剝離所述裝置及所述包封材料；蝕刻所述晶粒貼合膜，以暴露出所述裝置的後表面；以及在所述裝置的所述後表面上施加導熱性材料。

Description

封裝中作為隔離膜的釋放膜
隨著半導體技術的演進，半導體晶片/晶粒正日漸變小。與此同時，需要在半導體晶粒中整合更多的功能。因此，半導體晶粒需要將越來越多的輸入/輸出（input/output，I/O）接墊包裝於更小的區域中，且輸入/輸出接墊的密度隨時間而急劇增加。因此，半導體晶粒的封裝變得更加困難，此對封裝的良率造成不利影響。
傳統封裝技術可劃分成兩個類別。在第一類別中，在鋸切晶圓上的晶粒之前封裝所述晶粒。此種封裝技術具有一些有利特徵，例如具有更大的產量及更低的成本。此外，需要更少的底部填充劑或模製化合物。然而，此種封裝技術亦具有缺點。由於晶粒的大小正日漸變小，因此相應封裝可僅為扇入型封裝（fan-in type package），在所述扇入型封裝中每一晶粒的輸入/輸出接墊被限制於位於相應晶粒的表面正上方的區。由於晶粒的面積有限，因此輸入/輸出接墊的數目因所述輸入/輸出接墊的節距（pitch）的限度而受限。若欲減小接墊的節距，則可能出現焊料橋（solder bridge）。另外，根據固定的球的大小要求，焊料球必須具有特定大小，此進而會限制可在晶粒的表面上包裝的焊料球的數目。
在封裝的另一類別中，是在封裝晶粒之前自晶圓鋸切出晶粒。此種封裝技術的有利特徵是可形成扇出型封裝（fan-out package），此意味著晶粒上的輸入/輸出接墊可被重佈線至較所述晶粒大的區域，且因此在晶粒的表面上所包裝的輸入/輸出接墊的數目可增大。此種封裝技術的另一有利特徵是可封裝「已知合格晶粒（known-good-die）」並捨棄缺陷晶粒，且因此不會在缺陷晶粒上浪費成本及精力。
以下揭露內容提供諸多不同的實施例或實例以用於實作本發明的不同特徵。以下闡述組件及配置形式的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡明及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可使用例如「在...之下」、「在...下方」、「下部」、「上覆」、「上部」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。除了圖中所繪示的定向之外，所述空間相對性用語旨在涵蓋裝置在使用或操作時的不同定向。設備可被另外定向（旋轉90度或為其他定向），且本文所使用的空間相對性描述語可同樣相應地作出解釋。
根據各種示例性實施例，提供一種積體扇出型（Integrated Fan-Out，InFO）封裝及其形成方法。根據一些實施例說明形成所述積體扇出型封裝的中間階段。對一些實施例的一些變形進行論述。在各視圖中及說明性實施例通篇中，相同的參考編號用於標示相同的元件。
圖1至圖20A示出根據一些實施例的形成封裝中的中間階段的剖視圖。圖1至圖20A所示的步驟亦於圖22所示的製程流程400中進行示意性地說明。
參考圖1，提供載體20，且在載體20上塗佈釋放膜22。相應步驟被示為圖22所示製程流程中的步驟402。載體20是由透明材料形成，且可為玻璃載體、陶瓷載體、有機載體等。載體20可具有圓的俯視形狀，且可具有矽晶圓的大小。舉例而言，載體20可具有8英吋的直徑、12英吋的直徑等。釋放膜22在實體上接觸載體20的頂表面。釋放膜22可由光-熱轉換（Light To Heat Conversion，LTHC）塗佈材料形成。可藉由塗佈將釋放膜22施加至載體20上。根據本揭露的一些實施例，光-熱轉換塗佈材料能夠在光/輻射（例如雷射）的熱量之下進行分解，且因此可使載體20自形成於載體上的結構釋放。根據本揭露的一些實施例，光-熱轉換塗佈材料22包含碳黑（carbon black）（碳顆粒（carbon particle））、溶劑、矽填料、及/或環氧樹脂。所述環氧樹脂可包括聚醯亞胺或另一聚合物（例如壓克力（Acrylic））。聚醯亞胺若包含於光-熱轉換塗佈材料中，則與用於微影（photolithography）的典型聚醯亞胺不同，此乃因所述聚醯亞胺可不再具有光敏性，且可不會藉由曝光（photo exposure）及顯影而被移除。根據本揭露的一些示例性實施例，光-熱轉換塗佈材料22的厚度可介於約1微米與約2微米之間的範圍內。應理解，本揭露的整個說明中所列舉的值為實例，且可變為不同的值。光-熱轉換塗佈材料22可以可流動形式塗佈，且接著例如在紫外（ultra-violet，UV）光下被固化。光-熱轉換塗佈材料22為均質材料，且整個光-熱轉換塗佈材料22具有相同的組成。
根據一些實施例，如圖1所示，在光-熱轉換塗佈材料22上形成聚合物緩衝層（polymer buffer layer）23。根據一些實施例，聚合物緩衝層23是由聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）、或另一可適用的聚合物形成。根據替代實施例，不形成聚合物緩衝層23。因此，聚合物緩衝層23使用虛線示出以指示可形成或可不形成聚合物緩衝層23。
圖2至圖4示出金屬柱32的形成。相應步驟被示為圖22所示製程流程中的步驟404。在本說明通篇中，金屬柱體32作為另一選擇被稱為穿孔32，乃因金屬柱體32穿透隨後分配的包封材料。
參考圖2，例如藉由物理氣相沈積（Physical Vapor Deposition，PVD）來形成金屬晶種層（metal seed layer）24。根據本揭露的一些實施例，不形成聚合物緩衝層23，且因此金屬晶種層24在實體上接觸光-熱轉換塗佈材料22。根據本揭露的其他實施例，形成聚合物緩衝層23，且金屬晶種層24位於聚合物緩衝層23之上且接觸聚合物緩衝層23。根據本揭露的一些實施例，金屬晶種層24包括鈦層及位於所述鈦層之上的銅層。根據本揭露的替代實施例，金屬晶種層24包括與光-熱轉換塗佈材料22或聚合物緩衝層23接觸的銅層。
亦如圖2所示，在金屬晶種層24之上形成光阻26。接著使用微影罩幕（photo lithography mask）（圖中未示出）對光阻26執行曝光（light-exposure）。在隨後的顯影之後，在光阻26中形成開口28。經由開口28而暴露出金屬晶種層24的一些部分。
接下來，如圖3所示，藉由在開口28中鍍敷金屬材料而形成金屬柱32。金屬柱32作為另一選擇被稱為穿孔或模塑通孔（through-molding vias），乃因金屬柱32將穿透最終封裝中的隨後形成的包封材料（其可為模製化合物）。所鍍敷金屬材料可為銅或銅合金。金屬柱32的頂表面低於光阻26的頂表面，以使得金屬柱32的形狀由開口28來限定。金屬柱32可具有實質上垂直且筆直的邊緣。作為另一選擇，金屬柱32可在剖視圖中具有沙鍾（sand timer）形狀，其中金屬柱32的中間部分窄於相應的頂部部分及底部部分。
在後續步驟中，移除光阻26，且因此暴露出金屬晶種層24的下伏部分。接著在蝕刻步驟中（例如，在非等向性蝕刻（anisotropic etching）步驟或等向性蝕刻（isotropic etching）步驟中）移除金屬晶種層24的被暴露部分。剩餘晶種層24的邊緣因此可與金屬柱32的相應上覆部分共端或實質上共端。所得金屬柱32示於圖4中。在本說明通篇中，將金屬晶種層24的剩餘部分視作金屬柱32的部分。金屬柱32的俯視形狀包括但不限於圓形形狀、矩形形狀、六邊形形狀、八邊形形狀等。在金屬柱32形成之後，暴露出聚合物緩衝層23或光-熱轉換塗佈材料22。
圖5示出裝置36的植放/貼合。裝置36可為裝置晶粒（device die），且因此在下文中被稱為裝置晶粒36，然而裝置36亦可為封裝。相應步驟被示為圖22所示製程流程中的步驟406。藉由晶粒貼合膜（Die-Attach Film，DAF）38將裝置晶粒36貼合至聚合物緩衝層23或光-熱轉換塗佈材料22，晶粒貼合膜38為在將裝置晶粒36植放於光-熱轉換塗佈材料22上之前，預先貼合於裝置晶粒36上的黏著劑膜。裝置晶粒36可包括後表面（面朝下的表面）在實體上接觸晶粒貼合膜38的半導體基底39。裝置晶粒36可包括位於半導體基底39的前表面（面朝上的表面）處的積體電路裝置（例如主動裝置（包括例如電晶體（圖中未示出）））。根據本揭露的一些實施例，裝置晶粒36為邏輯晶粒，所述邏輯晶粒可為中央處理單元（Central Processing Unit，CPU）晶粒、圖形處理單元（Graphic Processing Unit，GPU）晶粒、行動應用晶粒、微控制單元（Micro Control Unit，MCU）晶粒、輸入輸出（IO）晶粒、基帶（BaseBand，BB）晶粒、或應用處理器（Application processor，AP）晶粒。由於載體20為晶圓級，因此儘管示出一個裝置晶粒36，然而在晶粒植放步驟中在光-熱轉換塗佈材料22之上植放多個相同的裝置晶粒36，且所述裝置晶粒可被部署成包括多個列及多個行的陣列。
根據一些示例性實施例，預形成金屬支柱42（例如銅支柱）來作為裝置晶粒36的部分，且將金屬支柱42電性耦合至裝置晶粒36中的積體電路裝置，例如電晶體（圖中未示出）。根據本揭露的一些實施例，介電材料（例如聚合物）填充相鄰金屬支柱42之間的間隙以形成頂部介電層44。頂部介電層44亦可包括覆蓋並保護金屬支柱42的一部分。根據本揭露的一些實施例，介電層44可由聚苯並噁唑或聚醯亞胺形成。
在植放裝置晶粒36時，施加力以推壓裝置晶粒36抵靠載體20，且所述力由箭頭表示。由於晶粒貼合膜38為軟的，因此與裝置晶粒36共端的最初的晶粒貼合膜38受到擠壓，且晶粒貼合膜38的一些部分38A被推出至位於裝置晶粒36正下方的區之外。此外，部分38A可具有較晶粒貼合膜38的部分38B的頂表面高的一些部分。部分38A可接觸裝置晶粒36的側壁，且裝置晶粒36的接觸部分可為半導體基底39（例如矽基底）。
接下來，如圖6所示，將裝置晶粒36及金屬柱32包封於包封材料48中。相應步驟被示為圖22所示製程流程中的步驟408。包封材料48填充相鄰穿孔32之間的間隙及穿孔32與裝置晶粒36之間的間隙。包封材料48可包括模製化合物、模製底部填充劑、環氧樹脂、及/或樹脂。包封材料48的頂表面高於金屬支柱42的頂端。模製化合物可包含基材（base material）及位於所述基材中的填料顆粒（圖中未示出），所述基材可為聚合物、樹脂、環氧樹脂等。填料顆粒可為SiO2 、Al2 O3 、二氧化矽等介電顆粒，且可具有球形形狀。此外，球形填料顆粒可具有相同或不同的直徑。
在隨後的步驟中，如圖7所示，執行平面化步驟（例如化學機械研磨（Chemical Mechanical Polish，CMP）步驟或機械磨削（mechanical grinding）步驟）以使包封材料48及介電層44薄化，直至完全暴露出穿孔32及金屬支柱42。相應步驟亦被示為圖22所示的製程流程中的步驟408。由於所述平面化製程，穿孔32的頂端與金屬支柱42的頂表面實質上齊平（共面），且與包封材料48的頂表面實質上共面。
圖8至圖12示出前側重佈線結構的形成。圖8及圖9示出第一層重佈線（Redistribution Line，RDL）及相應介電層的形成。參考圖8，形成介電層50。相應步驟被示為圖22所示製程流程中的步驟410。根據本揭露的一些實施例，介電層50是由例如聚苯並噁唑、聚醯亞胺等聚合物形成。所述形成方法包括塗佈可流動形式的介電層50，並接著對介電層50進行固化。根據本揭露的替代實施例，介電層50是由例如氮化矽、氧化矽等無機介電材料形成。所述形成方法可包括化學氣相沈積（Chemical Vapor Deposition，CVD）、原子層沈積（Atomic Layer Deposition，ALD）、電漿增強型化學氣相沈積（Plasma-Enhanced Chemical Vapor Deposition，PECVD）、或其他可適用的沈積方法。接著例如藉由微影製程來形成開口52。根據其中介電層50是由例如聚苯並噁唑或聚醯亞胺等感光性材料形成的一些實施例中，所述形成開口52涉及使用微影罩幕（圖中未示出）來對介電層50進行曝光、以及對介電層50進行顯影。經由開口52而暴露出穿孔32及金屬支柱42。
接下來，參考圖9，在介電層50之上形成重佈線54。相應步驟被示為圖22所示製程流程中的步驟412。重佈線54包括形成於介電層50中以連接至金屬支柱42及穿孔32的介層窗54A、以及位於介電層50之上的金屬跡線（金屬線）54B。根據本揭露的一些實施例，在鍍敷製程中形成重佈線54（包括54A及54B），所述鍍敷製程包括沈積金屬晶種層（圖中未示出）、在所述金屬晶種層之上形成光阻（圖中未示出）並將所述光阻圖案化、及在所述金屬晶種層之上鍍敷例如銅及/或鋁等金屬材料。金屬晶種層及所鍍敷金屬材料可由相同材料或不同材料形成。接著移除經圖案化的光阻，然後對金屬晶種層的先前被所述經圖案化的光阻覆蓋的部分進行蝕刻。圖21示出重佈線54中的一者及介電層50的放大圖。如圖21所示，重佈線54的位於介層窗54A正上方的部分的頂表面可凹陷得低於重佈線54的位於介電層50正上方的部分。其他重佈線54以及重佈線58及64（圖12）可具有相似的輪廓。
參考圖10，根據本揭露的一些實施例，在圖9所示結構之上形成介電層60，然後在介電層60中形成開口。因此經由所述開口而暴露出重佈線54的一些部分。可使用選自用於形成介電層50的相同的候選材料的材料來形成介電層60，所述候選材料可包括聚苯並噁唑、聚醯亞胺、苯並環丁烯、或其他有機或無機材料。接著形成重佈線58。相應步驟被示為圖22所示製程流程中的步驟414。重佈線58亦包括延伸至介電層60中的開口中以接觸重佈線54的介層窗部分、以及位於介電層60正上方的金屬線部分。所述形成重佈線58可相同於所述形成重佈線54，所述形成包括形成晶種層、形成經圖案化的罩幕、對重佈線58進行鍍敷、以及接著移除經圖案化的罩幕及晶種層的所不期望的部分。
圖11示出在介電層60及重佈線58之上形成介電層62及重佈線64。相應步驟被示為圖22所示製程流程中的步驟416。介電層62可由選自用於形成介電層50及60的同一組候選材料的材料形成。重佈線64亦可由金屬或金屬合金形成，所述金屬或金屬合金包括鋁、銅、鎢、或其合金。應理解，儘管在所示示例性實施例中，形成有三層重佈線（54、58、及64），然而所述封裝可具有任何數目的重佈線層，例如一個層、兩個層、或多於三個層。
圖12示出根據一些示例性實施例的介電層66、球下金屬（Under-Bump Metallurgy，UBM）68、及電性連接件70的形成。介電層66可由選自用於形成介電層50、60、及62的同一組候選材料的材料形成。舉例而言，可使用聚苯並噁唑、聚醯亞胺、或苯並環丁烯來形成介電層66。在介電層66中形成開口以暴露出下伏金屬接墊，所述下伏金屬接墊在所述說明性示例性實施例中作為重佈線64的部分。根據本揭露的某一實施例，將球下金屬68形成為延伸至介電層66中的開口中以接觸重佈線64中的金屬接墊。球下金屬68可由鎳、銅、鈦、或其多層形成。根據一些示例性實施例，球下金屬68包括鈦層及位於所述鈦層之上的銅層。
接著形成電性連接件70。相應步驟被示為圖22所示製程流程中的步驟418。所述形成電性連接件70可包括在球下金屬68的被暴露部分上植放焊料球，且接著對所述焊料球進行回焊，並且因此電性連接件70為焊料區。根據本揭露的替代實施例，所述形成電性連接件70包括執行鍍敷步驟以在球下金屬68之上形成焊料層，且接著對所述焊料層進行回焊。電性連接件70亦可包括亦可藉由鍍敷來形成的非焊料金屬支柱、或金屬支柱及位於所述非焊料金屬支柱之上的焊料頂蓋。在本說明通篇中，將包括釋放膜22的結構與上覆結構組合起來稱作封裝100，封裝100是包括多個裝置晶粒36的複合晶圓（且在下文中亦被稱作複合晶圓100）。
接下來，參考圖13，將複合晶圓100植放於貼合至框架76的膠帶74上。根據本揭露的一些實施例，電性連接件70接觸膠帶74。接下來，在光-熱轉換塗佈材料22上投射光77（由箭頭表示），且光77穿透透明載體20。根據本揭露的一些示例性實施例，光77為雷射束，所述雷射束掃描過整個光-熱轉換塗佈材料22。
作為曝光（例如雷射掃描）的結果，可自光-熱轉換塗佈材料22剝除載體20，且因此自載體20剝去（拆下）複合晶圓100。相應步驟被示為圖22所示製程流程中的步驟420。在曝光期間，光-熱轉換塗佈材料22的至少頂部部分因應於藉由曝光所引入的熱量而被分解，因而使得載體20能夠與下伏結構分離。接著例如藉由電漿清潔步驟來移除光-熱轉換塗佈材料22的殘餘物。所得複合晶圓100示於圖14中。
根據其中形成有聚合物緩衝層23的本揭露的一些實施例，如圖14所示，在複合晶圓100的頂部處暴露出聚合物緩衝層23。根據其中不形成聚合物緩衝層23的本揭露的替代實施例，暴露出穿孔32、包封材料48及晶粒貼合膜38，且對應的結構示於圖15中。若形成聚合物緩衝層23，則進行蝕刻，亦產生如圖15所示的結構。相應步驟被示為圖22所示製程流程中的步驟422。
根據本揭露的一些實施例，對作為如圖3所示金屬晶種層24的部分的鈦層24A（圖15）進行蝕刻。由於鈦具有較銅高的電阻率（electrical resistivity），因此藉由移除鈦層，暴露出具有較鈦層低的電阻率的穿孔32的銅部分。因此，可建立至穿孔32的電阻較低的連接。根據本揭露的一些實施例，藉由使用氟化氫（hydrogen fluoride，HF）溶液、磷酸、或氟化氫與磷酸的混合物的濕式蝕刻來對鈦層執行蝕刻。亦可利用乾式蝕刻來執行所述蝕刻。
此外，在蝕刻步驟中蝕刻晶粒貼合膜38。相應步驟被示為圖22所示製程流程中的步驟424。根據本揭露的一些實施例，藉由乾式蝕刻來執行所述蝕刻。蝕刻氣體可包括氧氣（O2 ）、CF4 、及可能的一些其他氣體（例如氮氣（N2 ））。所述蝕刻由如圖15所示箭頭72表示。所得結構示於圖16A至圖16C中。根據一些示例性實施例，在進行蝕刻時，蝕刻氣體中的氧氣可具有介於約50標準毫升/分鐘（sccm）與約1,500標準毫升/分鐘之間的範圍內的流速，蝕刻氣體中的CF4 可具有介於約50標準毫升/分鐘與約1,500標準毫升/分鐘之間的範圍內的流速，且蝕刻氣體中的氮氣可具有介於約50標準毫升/分鐘與約2,000標準毫升/分鐘之間的範圍內的流速。
蝕刻氣體可對晶粒貼合膜38及包封材料48兩者產生蝕刻。晶粒貼合膜38亦可被完全移除（如圖16A至圖16C所示）或被局部地移除（如圖20C所示）。可藉由調整例如氧氣及CF4 的流速等蝕刻條件來調整作為晶粒貼合膜38的蝕刻率對包封材料48的蝕刻率的比率的蝕刻選擇性，以使得可產生各種效果。舉例而言，晶粒貼合膜38的蝕刻率可高於、等於、或低於包封材料48的蝕刻率。由於對包封材料48的蝕刻，包封材料48的頂表面凹陷得低於穿孔32的頂表面。另一方面，蝕刻氣體不會侵蝕穿孔32，且因此穿孔32突出至包封材料48上方。根據本揭露的一些實施例，突出高度HP1（圖16A）介於約2微米與約50微米之間的範圍內。
根據替代實施例，藉由雷射掃描來達成對晶粒貼合膜38的移除，且因此晶粒貼合膜38及包封材料48的頂表面部分被移除。由於穿孔32及裝置晶粒36的基底39的高導熱率，穿孔32及裝置晶粒36的基底39儘管亦經受雷射掃描，然而不會凹陷。
在圖16A中，穿孔32的高度被表示為H1，包封材料48的高度被表示為H2，且裝置晶粒36的高度被表示為H3。高度H1因穿孔32的突出而大於高度H2及H3。端視包封材料48凹陷的程度而定，裝置晶粒36的高度H3可大於、等於、或小於包封材料48的高度H2。由於存在部分38A（圖15），形成凹槽73，如圖16A所示。應理解，凹槽73為當自裝置晶粒36的頂部觀察時環繞裝置晶粒36的凹槽環的部分。凹槽73可延伸至低於裝置晶粒36的頂表面。此外，裝置晶粒36的側壁可被暴露至凹槽73。根據本揭露的一些實施例，凹槽73的深度D1可介於約1微米與約100微米之間的範圍內。
圖16B示出根據一些實施例的複合晶圓100。除了不形成如圖16A所示的凹槽73以外，該些實施例相似於圖16A所示的實施例。
圖16C示出根據一些實施例的複合晶圓100。除了穿孔32具有與包封材料48的頂表面及裝置晶粒36的頂表面共面的頂表面且不形成如圖16A所示的凹槽73以外，該些實施例相似於如圖16A所示的實施例。
根據本揭露的一些實施例，如圖17所示，施加導熱膏78來覆蓋裝置晶粒36。相應步驟被示為圖22所示製程流程中的步驟426。根據本揭露的替代實施例，不施加導熱膏78，如圖20B所示。導熱膏78可包含混合有金屬顆粒（例如銅顆粒）的聚合物。導熱膏78亦可為焊料膏。因此，導熱膏78亦可為導電的。導熱膏78可藉由印刷或另一可適用的方法來施加，並接著被固化成固體狀態。可對或可不對導熱膏78進行熱處理（在其固化期間），以移除其中的聚合物及/或溶劑，使得在凝固的導熱膏78中留有金屬顆粒及少量的黏著劑。根據一些示例性實施例，導熱膏78的大部分（例如大於80重量百分比）可為金屬顆粒。所述熱處理可包括介於約160℃與約200℃之間的範圍內的處理溫度，且所述熱處理可持續約30分鐘與約2小時之間。導熱膏78可具有高於約1瓦/克耳文*米（W/k*m）、高於約5瓦/克耳文*米、高於約20瓦/克耳文*米、高於約50瓦/克耳文*米、或甚至更高的導熱率。
導熱膏78可具有較裝置晶粒36的俯視面積大的俯視面積，且可完全覆蓋或局部地覆蓋裝置晶粒36。此外，凹槽73（圖16）亦可由導熱膏78來填充。因此，凹槽73中的導熱膏78可完全環繞裝置晶粒36，且凹槽73中的導熱膏78的部分與裝置晶粒36之間的垂直介面可形成完整的環。導熱膏78的頂表面與包封材料48的頂表面齊平或高於包封材料48的頂表面，此意味著裝置晶粒36與導熱膏78的組合高度H4等於或大於包封材料48的厚度高度H2。
如圖18所示，複合晶圓100包括多個封裝100’（示意性地示出），所述多個封裝100’彼此相同且封裝100’中的每一者包括穿孔32及一個裝置晶粒36。圖18亦示出將封裝200結合至封裝100’，因而形成多個相同的疊層封裝（Package-on-Package，PoP）結構/封裝。藉由焊料區80來執行所述結合，焊料區80將穿孔32接合至上覆封裝200中的金屬接墊206。焊料區80可接觸穿孔32的突出部分的頂表面及側壁，且因此會減小接觸電阻。根據本揭露的一些實施例，封裝200包括封裝基底204及裝置晶粒202，裝置晶粒202可為例如靜態隨機存取記憶體（Static Random Access Memory，SRAM）晶粒、動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）晶粒等記憶體晶粒。亦將底部填充劑208設置至封裝200與下伏封裝100’之間的間隙中，並進行固化。
根據本揭露的一些實施例，導熱膏78的頂表面低於封裝200的頂表面。因此，導熱膏78藉由底部填充劑208的一部分在垂直方向上與封裝200間隔開。根據替代實施例，亦如圖18所示，導熱膏78足夠厚，且導熱膏78的頂表面接觸封裝200的底表面。虛線78’示意性地示出導熱膏78的接觸封裝200的所延伸邊緣。在隨後論述的圖20A、圖20C、圖20D、及圖20E所示的封裝中，邊緣78’亦被示出。
根據本揭露的替代實施例，並非將封裝200結合至穿孔32，而是形成背側重佈線結構（圖中未示出）。背側重佈線結構將包括介電層及位於所述介電層中的重佈線，且封裝200結合於背側重佈線結構中的背側重佈線之上。為了形成背側重佈線結構，可在複合晶圓100之下植放載體而非膠帶以作為形成背側重佈線結構時的支撐件。因此，在形成背側重佈線結構期間藉由黏著劑膜（圖中未示出）將電性連接件70黏著至載體。
接下來，參考圖19，執行單體化（晶粒鋸切）製程以將複合晶圓100及上覆封裝200分割成彼此相同的單獨的封裝300。所得結構示於圖19中。單體化可在膠帶74上執行。所述單體化可使用刀片來執行，或可使用雷射來執行以進行預開槽，使得形成溝槽，並接著使用刀片來切穿所述溝槽。
圖20A示出藉由焊料區70將單體化的封裝300結合至封裝組件86。根據本揭露的一些實施例，封裝組件86為封裝基底，所述封裝基底可為無芯基底或具有芯體的基底。根據本揭露的其他實施例，封裝組件86為印刷電路板或封裝。焊料區70可結合至封裝組件86中的結合接墊88。
在封裝300中，導熱膏78具有良好的導熱率，且因此會將在裝置晶粒36中產生的熱量高效地傳導至底部填充劑208中。底部填充劑208亦可被選擇成具有相對高的導熱率（但低於導熱膏78的導熱率），且因此可在水平方向上將熱量傳導至封裝300之外。導熱膏78亦可環繞並接觸裝置晶粒36的側壁，因此進一步改善熱傳導。
如圖16A及圖16B所示，可形成或可不形成圖16A及圖16B中的凹槽73。因此，在圖20A中，導熱膏78的部分78A可能存在或可能不存在，且對應的區可被包封材料48或導熱膏78的部分佔據。
圖20B示出根據本揭露一些實施例的封裝300的剖視圖。除了導熱膏不形成於裝置晶粒36正上方以外，根據該些實施例的封裝300相似於圖20A所示的封裝300。因此，裝置晶粒36的頂表面在實體上接觸底部填充劑208。由於具有低導熱率值的聚合物緩衝層23及晶粒貼合膜38（圖14）已被移除且將不再充當散熱的障壁，因此裝置晶粒36與底部填充劑208之間的導熱率相較於包括聚合物緩衝層23及晶粒貼合膜38的封裝得到提高。
圖20C示出根據本揭露一些實施例的封裝300的剖視圖。除了晶粒貼合膜38的至少底部部分留存且可形成或可不形成凹槽以外，根據該些實施例的封裝300相似於圖20A所示的封裝300。根據本揭露的一些實施例，藉由以下方式來形成此種結構：將晶粒貼合膜38的蝕刻率控制至接近於包封材料48的蝕刻率，且一旦暴露出裝置晶粒36便停止蝕刻製程。根據一些實施例，在裝置晶粒36之上形成導熱膏78。根據替代實施例，不在裝置晶粒36之上形成導熱膏78。因此，導熱膏78使用虛線示出以指示可形成或可不形成導熱膏78。
圖20D示出根據本揭露一些實施例的封裝300的剖視圖。除了穿孔32不突出至高於包封材料48的頂表面及裝置晶粒36的頂表面以外，根據該些實施例的封裝300相似於圖20A所示的封裝300。因此，穿孔32的頂表面、包封材料48的頂表面、及裝置晶粒36的頂表面彼此共面。根據該些實施例，可形成或可不形成凹槽73（圖16A）。凹槽73當形成時，將被導熱膏佔據。
圖20E示出根據本揭露一些實施例的封裝300的剖視圖。除了導熱膏78小於裝置晶粒36以外，根據該些實施例的封裝300相似於圖20A所示的封裝300。因此，裝置晶粒36的頂表面具有與導熱膏78接觸的部分（例如，中心部分）及與底部填充劑208接觸的部分。導熱膏78的寬度W1小於裝置晶粒36的寬度W2。根據該些實施例，可形成或可不形成凹槽73（如圖16A所示）。凹槽73當形成時，將被底部填充劑208佔據。
圖20F示出根據本揭露一些實施例的封裝300的剖視圖。除了導熱膏78具有與包封材料48的頂表面共面或較包封材料48的頂表面低的頂表面以外，根據該些實施例的封裝300相似於圖20A所示的封裝300。舉例而言，使用實線所示的導熱膏78的頂表面與包封材料48的頂表面共面。虛線81示出根據一些實施例的導熱膏78的頂表面，且導熱膏78的頂表面低於包封材料48的頂表面。所述實施例是在圖16A所示的步驟中對裝置晶粒36的基底39進行較快蝕刻的結果。在圖20F中，裝置晶粒36與導熱膏78的總高度H4等於或小於包封材料48的高度H3。
根據本揭露一些實施例的封裝是利用最後重佈線製程（RDL-last process）來形成，在最後重佈線製程中形成晶粒貼合膜38及可能的聚合物緩衝層23並接著對晶粒貼合膜38及可能的聚合物緩衝層23進行蝕刻。另一方面，最先重佈線製程（RDL-first process）作為用於避免形成晶粒貼合膜及聚合物緩衝層的方式為不佳的。原因在於，在最先重佈線製程中，同時對裝置晶粒的矽基底39與穿孔進行平面化，且發現了自穿孔進行研磨的銅會污染矽基底，因而造成裝置晶粒的洩漏。
在以上所示的示例性實施例中，根據本揭露的一些實施例對一些示例性製程及特徵作出論述。亦可包括其他特徵及製程。舉例而言，可包括測試結構以有助於對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）裝置進行驗證測試。測試結構可包括例如在重佈線層中或在基底上形成的測試接墊，所述測試接墊使得能夠對三維封裝或三維積體電路進行測試、使用探針及/或探針卡等。可對中間結構以及最終結構執行驗證測試。另外，可結合包括對已知合格晶粒進行中間驗證的測試方法來使用本文所揭露的結構及方法，以增加良率並降低成本。
本揭露的實施例具有一些有利特徵。藉由移除封裝中的聚合物緩衝層及晶體貼合膜，聚合物緩衝層及晶粒貼合膜不再阻礙散熱，且因此所得封裝的散熱得到改善。
根據本揭露的一些實施例，一種方法包括：在載體之上形成釋放膜；藉由晶粒貼合膜將裝置貼合於所述釋放膜之上；將所述裝置包封於包封材料中；對所述包封材料執行平面化以暴露出所述裝置；自所述載體剝離所述裝置及所述包封材料；以及蝕刻所述晶粒貼合膜，以暴露出所述裝置的後表面。在實施例中，所述方法更包括在所述裝置的所述後表面上施加導熱膏；以及分配底部填充劑以接觸所述導熱膏。在實施例中，在蝕刻所述晶粒貼合膜之後，形成延伸至所述包封材料內的凹槽，且所述導熱膏被填充至所述凹槽中。在實施例中，所述方法更包括分配底部填充劑，其中所述底部填充劑接觸所述裝置的所述後表面。在實施例中，在蝕刻所述晶粒貼合膜之後，形成延伸至所述包封材料內的凹槽，且所述底部填充劑被填充至所述凹槽中。在實施例中，所述方法更包括在所述載體之上形成金屬柱，其中所述金屬柱被包封於所述包封材料中，其中在蝕刻所述晶粒貼合膜時，所述包封材料的一部分被蝕刻，且所述穿孔突出出所述包封材料外。在實施例中，在蝕刻所述晶粒貼合膜之後，所述晶粒貼合膜被完全移除。在實施例中，在蝕刻所述晶粒貼合膜之後，與所述裝置的所述後表面接觸的所述晶粒貼合膜的第一部分被移除，而與所述裝置的側壁接觸的所述晶粒貼合膜的第二部分則留存。
根據本揭露的一些實施例，一種方法包括：在載體上塗佈釋放層；在所述釋放層之上形成金屬柱；藉由晶粒貼合膜將裝置晶粒貼合於所述釋放層之上；將所述裝置晶粒及所述金屬柱包封於包封材料中；在所述釋放層上投射光，以分解所述釋放層的一部分；自所述包封材料、所述裝置晶粒、及所述金屬柱剝除所述載體；蝕刻所述晶粒貼合膜，以顯露出所述裝置晶粒的後表面；將封裝結合至所述金屬柱；以及分配底部填充劑，其中所述底部填充劑的一部分設置於所述裝置晶粒與所述封裝之間。在實施例中，所述方法更包括在所述裝置晶粒的所述後表面上施加導熱膏；以及對所述導熱膏進行固化，其中所述底部填充劑接觸所述導熱膏。在實施例中，所述底部填充劑接觸所述裝置晶粒的所述後表面。在實施例中，當蝕刻所述晶粒貼合膜時，所述包封材料亦被蝕刻而使所述金屬柱突出出所述包封材料外。在實施例中，所述蝕刻所述晶粒貼合膜使得形成延伸至所述包封材料中的凹槽。在實施例中，所述底部填充劑被填充至所述凹槽中。
根據本揭露的一些實施例，一種封裝包括：包封材料；穿孔，穿透所述包封材料，其中所述穿孔包括突出至高於所述包封材料的頂表面的部分；裝置，包封於所述包封材料中，其中所述裝置包括具有後表面的半導體基底；封裝組件，位於所述穿孔之上且結合至所述穿孔；以及底部填充劑，位於所述包封材料與所述封裝組件之間，其中所述底部填充劑接觸所述包封材料。在實施例中，所述底部填充劑更接觸所述裝置中所述半導體基底的所述後表面。在實施例中，所述底部填充劑更包括延伸至所述包封材料中的一部分，其中所述底部填充劑的所述一部分接觸所述裝置中所述半導體基底的側壁。在實施例中，所述封裝更包括導熱膏，所述導熱膏位於所述裝置中所述半導體基底的所述後表面之上且接觸所述半導體基底的所述後表面，所述底部填充劑的一部分與所述導熱膏交疊。在實施例中，所述導熱膏更包括延伸至所述包封材料中的一部分，其中所述導熱膏的所述一部分接觸所述裝置中所述半導體基底的側壁。在實施例中，所述封裝更包括焊料區，所述焊料區將所述穿孔結合至所述封裝組件，其中所述焊料區接觸所述穿孔的側壁。
根據本揭露的一些實施例，一種方法包括：自上覆於晶粒貼合膜、包封材料、及穿透所述包封材料的穿孔之上的區移除層，其中晶粒貼合膜被顯露出，且所述晶粒貼合膜將裝置與所述層接合；蝕刻所述晶粒貼合膜，以至少局部地移除所述晶粒貼合膜，其中在蝕刻所述晶粒貼合膜之後，所述裝置的表面被暴露出；在所述裝置的所述表面上施加膏；對所述膏進行固化；將封裝組件結合至所述穿孔，其中所述膏與所述封裝組件間隔開一間隙；以及將底部填充劑填充至所述間隙中。在實施例中，所述移除所述層包括移除聚合物緩衝層。在實施例中，所述移除所述層包括蝕刻光-熱轉換塗佈材料。在實施例中，在蝕刻所述晶粒貼合膜之後，形成延伸至所述包封材料內的凹槽，且所述膏被填充至所述凹槽中。在實施例中，在蝕刻所述晶粒貼合膜之後，所述晶粒貼合膜的延伸至所述包封材料中的剩餘部分留下，且所述膏具有位於所述晶粒貼合膜的剩餘部分之上且接觸所述晶粒貼合膜的剩餘部分的一部分。在實施例中，在蝕刻所述晶粒貼合膜時，蝕刻所述包封材料以使得所述穿孔的一部分突出出所述包封材料外。
根據本揭露的一些實施例，一種封裝包括：包封材料；裝置晶粒，包封於所述包封材料中，其中所述裝置晶粒包括具有後表面的半導體基底；導熱膏，位於所述裝置晶粒之上且接觸所述裝置晶粒；封裝組件，位於所述包封材料及所述裝置晶粒之上；以及底部填充劑，分離所述導熱膏與所述封裝組件且接觸所述導熱膏及所述封裝組件。在實施例中，所述底部填充劑接觸所述包封材料。
根據本揭露的一些實施例，一種封裝包括：包封材料；裝置晶粒，包封於所述包封材料中，其中所述裝置晶粒包括半導體基底；以及填充材料，所述填充材料包括：第一部分，延伸至所述包封材料中以接觸所述裝置晶粒的側壁；以及第二部分，位於所述裝置晶粒中所述半導體基底的頂表面之上且接觸所述半導體基底的頂表面。在實施例中，所述填充材料包括導熱膏，且所述封裝更包括底部填充劑，所述底部填充劑的一部分位於所述導熱膏之上且接觸所述導熱膏。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應理解，其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，且他們可在不背離本揭露的精神及範圍條件下對其作出各種改變、代替、及變更。
20‧‧‧載體/透明載體
22‧‧‧釋放膜/光-熱轉換塗佈材料
23‧‧‧聚合物緩衝層
24‧‧‧金屬晶種層/剩餘晶種層
24A‧‧‧鈦層
26‧‧‧光阻
28、52‧‧‧開口
32‧‧‧金屬柱/穿孔
36‧‧‧裝置/裝置晶粒
38‧‧‧晶粒貼合膜
38A、38B、78A‧‧‧部分
39‧‧‧半導體基底/基底/矽基底
42‧‧‧金屬支柱
44‧‧‧頂部介電層/介電層
48‧‧‧包封材料
50、60、62、66‧‧‧介電層
54、58、64‧‧‧重佈線
54A‧‧‧介層窗
54B‧‧‧金屬跡線/金屬線
68‧‧‧球下金屬
70‧‧‧電性連接件
72‧‧‧箭頭
73‧‧‧凹槽
74‧‧‧膠帶
76‧‧‧框架
77‧‧‧光
78‧‧‧導熱膏
78’‧‧‧虛線/邊緣
80‧‧‧焊料區
81‧‧‧虛線
86‧‧‧封裝組件
88‧‧‧結合接墊
100‧‧‧封裝/複合晶圓
100’‧‧‧封裝/下伏封裝
200‧‧‧封裝/上覆封裝
202‧‧‧裝置晶粒
204‧‧‧封裝基底
206‧‧‧金屬接墊
208‧‧‧底部填充劑
300‧‧‧封裝
400‧‧‧製程流程
402、404、406、408、410、412、414、416、418、420、422、424、426‧‧‧步驟
D1‧‧‧深度
H1‧‧‧穿孔的高度/高度
H2‧‧‧包封材料的高度/高度
H3‧‧‧裝置晶粒的高度/高度
H4‧‧‧組合高度
HP1‧‧‧突出高度
W1、W2‧‧‧寬度
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1至圖20A示出根據一些實施例的形成封裝中的中間階段的剖視圖。 圖20B至圖20F示出根據某些實施例的一些封裝的剖視圖。 圖21示出根據一些實施例的重佈線的一部分的放大圖。 圖22示出根據一些實施例的形成封裝的製程流程。

Claims (20)

  1. 一種方法，包括： 在載體之上形成釋放膜； 藉由晶粒貼合膜將裝置貼合於所述釋放膜之上； 將所述裝置包封於包封材料中； 對所述包封材料執行平面化以暴露出所述裝置； 形成重佈線，以電性耦合至所述裝置； 在形成所述重佈線之後，自所述載體剝離所述裝置及所述包封材料； 移除所述晶粒貼合膜，以暴露出所述裝置的後表面；以及 在所述裝置的所述後表面上施加導熱性材料。
  2. 如申請專利範圍第1項所述的方法，更包括： 分配底部填充劑以接觸所述導熱性材料。
  3. 如申請專利範圍第1項所述的方法，其中在所述晶粒貼合膜被移除之後，形成延伸至所述包封材料內的凹槽，且所述導熱性材料被填充至所述凹槽中。
  4. 如申請專利範圍第1項所述的方法，其中所述導熱性材料具有高於約1瓦/克耳文*米的導熱率。
  5. 如申請專利範圍第1項所述的方法，其中所述導熱性材料選自由焊料、銀、銅膏、及其組合組成的群組。
  6. 如申請專利範圍第1項所述的方法，更包括： 在所述載體之上形成金屬柱，其中所述金屬柱被包封於所述包封材料中，其中在移除所述晶粒貼合膜時，所述包封材料的一部分被移除，且所述金屬柱突出出所述包封材料外。
  7. 如申請專利範圍第1項所述的方法，其中在移除所述晶粒貼合膜之後，所述晶粒貼合膜被完全移除。
  8. 如申請專利範圍第1項所述的方法，其中在移除所述晶粒貼合膜之後，與所述裝置的所述後表面接觸的所述晶粒貼合膜的第一部分被移除，而與所述裝置的側壁接觸的所述晶粒貼合膜的第二部分則留存。
  9. 一種方法，包括： 在載體上塗佈釋放層； 在所述釋放層之上形成金屬柱； 藉由晶粒貼合膜將裝置晶粒貼合於所述釋放層之上； 將所述裝置晶粒及所述金屬柱包封於包封材料中； 在所述釋放層上投射光，以分解所述釋放層的一部分； 自所述包封材料、所述裝置晶粒、及所述金屬柱剝除所述載體； 蝕刻所述晶粒貼合膜，以顯露出所述裝置晶粒的後表面； 在所述裝置晶粒的所述後表面上施加導熱性材料； 將封裝結合至所述金屬柱；以及 分配底部填充劑，其中所述底部填充劑的一部分設置於所述裝置晶粒與所述封裝之間。
  10. 如申請專利範圍第9項所述的方法，更包括： 固化所述導熱性材料，其中所述底部填充劑接觸所述導熱性材料。
  11. 如申請專利範圍第9項所述的方法，其中所述底部填充劑接觸所述裝置晶粒的所述後表面。
  12. 如申請專利範圍第9項所述的方法，其中當蝕刻所述晶粒貼合膜時，所述包封材料亦被蝕刻而使所述金屬柱突出出所述包封材料外。
  13. 如申請專利範圍第9項所述的方法，其中所述蝕刻所述晶粒貼合膜使得形成延伸至所述包封材料中的凹槽。
  14. 如申請專利範圍第13項所述的方法，其中所述底部填充劑被填充至所述凹槽中。
  15. 一種封裝，包括： 包封材料； 穿孔，穿透所述包封材料； 裝置，包封於所述包封材料中，其中所述裝置包括具有後表面的半導體基底； 封裝組件，位於所述穿孔之上且結合至所述穿孔； 導熱性材料，位於所述裝置中所述半導體基底的所述後表面之上且接觸所述半導體基底的所述後表面；以及 底部填充劑，位於所述包封材料與所述封裝組件之間，其中所述底部填充劑接觸所述包封材料。
  16. 如申請專利範圍第15項所述的封裝，其中所述底部填充劑更接觸所述裝置中所述半導體基底的所述後表面。
  17. 如申請專利範圍第16項所述的封裝，其中所述底部填充劑更包括延伸至所述包封材料中的一部分，其中所述底部填充劑的所述一部分接觸所述裝置中所述半導體基底的側壁。
  18. 如申請專利範圍第15項所述的封裝，其中所述穿孔包括突出至較所述包封材料的頂表面高的一部分。
  19. 如申請專利範圍第15項所述的封裝，其中所述導熱性材料更包括延伸至所述包封材料中的一部分，其中所述導熱性材料的所述一部分接觸所述裝置中所述半導體基底的側壁。
  20. 如申請專利範圍第15項所述的封裝，更包括焊料區，所述焊料區將所述穿孔結合至所述封裝組件，其中所述焊料區接觸所述穿孔的側壁。
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US10763132B2 (en) 2020-09-01
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