TW201818476A - 用於半導體裝置的延伸區域 - Google Patents

用於半導體裝置的延伸區域 Download PDF

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TW201818476A
TW201818476A TW106126833A TW106126833A TW201818476A TW 201818476 A TW201818476 A TW 201818476A TW 106126833 A TW106126833 A TW 106126833A TW 106126833 A TW106126833 A TW 106126833A TW 201818476 A TW201818476 A TW 201818476A
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channel
region
extension
gate
semiconductor device
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TW106126833A
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TWI739879B (zh
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坎達巴拉 泰伯利
傑佛瑞 史密斯
尼哈爾 莫漢蒂
安東 德維利耶
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日商東京威力科創股份有限公司
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Abstract

一種具有通道及耦合至該通道之源極-汲極之半導體裝置的形成方法。此方法包含蝕刻一通道區域俾使該通道區域的一端在圍繞該通道區域的一閘極結構內形成一凹陷部。形成一延伸區域與該通道區域接觸並至少部分填滿該凹陷部。該延伸區域的一延伸材料所具有的一組成係不同於該通道區域之一通道材料的一組成俾以在該通道區域中產生一應變。一源極-汲極區域係與該延伸區域接觸並與該閘極結構相鄰。

Description

用於半導體裝置的延伸區域
交互參考之相關申請案：本申請案係基於2016年8月10日申請之美國專利臨時申請案US 62/373,164並主張其為優先權母案，將其所有內容包容包含於此作為參考。 本發明係大致上關於半導體裝置之改善。更具體而言，本發明係關於半導體裝置如積體電路之製造方法以及積體電路用之電晶體與電晶體元件的改善。
半導體裝置的製造(尤其是微觀的層面)涉及重覆地進行以在基板上形成期望之半導體裝置的各種製造程序如薄膜形成沉積、蝕刻遮罩產生、圖案化、材料蝕刻與移除、以及摻雜處理。習知的微製造皆在一平面中產生電晶體並在此類平面之上形成導線/金屬化，因此被特徵化為二維(2D)電路或 2D製造。微縮的努力大幅增加了2D電路中每單位面積中的電晶體數目，但當微縮進入個位數奈米半導體裝置製造節點時，微縮努力遇到了更大的挑戰。半導體裝置的製造商表達了對三維(3D)半導體裝置的期望，在三維(3D)半導體裝置中電晶體係彼此上下堆疊。
業界持續需要高效能之半導體裝置的微縮以及其對應的製造程序。
根據本發明的一實施例，提供一種具有通道及耦合至該通道之源極-汲極之半導體裝置的形成方法。此方法包含蝕刻一通道區域俾使該通道區域的一端在圍繞該通道區域的一閘極結構內形成一凹陷部。形成一延伸區域與該通道區域接觸並至少部分填滿該凹陷部。該延伸區域的一延伸材料所具有的一組成係不同於該通道區域之一通道材料的一組成俾以在該通道區域中產生一應變。一源極-汲極區域係與該延伸區域接觸並與該閘極結構相鄰。
另一態樣包含一種半導體裝置，此半導體裝置具有一閘極結構及一通道，該閘極結構包含一閘極間隙壁且該通道延伸通過該閘極結構俾使該通道的一端陷入該閘極間隙壁中的一凹陷部內。一延伸區域係與該凹陷部內之該通道的該端接觸，該延伸區域係由一延伸材料所形成且該延伸材料的一組成係不同於該通道的一通道材料的一組成俾以在該通道中提供一應變。一源極-汲極接觸件係與該延伸區域接觸並與該閘極結構相鄰。
在更另一態樣中，一種半導體裝置包含一p型橫向奈米線，該p型橫向奈米線係藉由通過一閘極間隙壁中之一第一開口的一第一連接結構而耦合至一p型源極-汲極區域。一n型橫向奈米線係以和該p型橫向奈米線垂直堆疊的關係而設置，且係藉由通過該閘極間隙壁中之一第二開口的一第二連接結構而耦合至一n型源極-汲極區域。一電極結構包含接觸該p型源極-汲極區域的一p型電極以及接觸該n型源極-汲極區域的一n型電極，該n型電極係藉由介電材料而與該p型電極電絕緣。該第一連接結構與該第二連接結構中的至少一者在該閘極間隙壁中的一對應開口內包含一延伸摻雜區域。又，根據本發明的一實施例，提供一種半導體裝置。該半導體裝置包含複數奈米線及一閘極間隙壁，該奈米線包含一凹陷部，且該閘極間隙壁纏繞該複數奈米線，該複數奈米線包含對該複數奈米線中之該凹陷部提供接取的一通道，其中該凹陷部及該通道包含矽鍺的延伸摻雜。該凹陷部的一深度係小於該閘極間隙壁的一寬度。
上面對實施例的大略說明及下面對實施例的詳細闡述僅為本發明的例示性而非限制性態樣。
下面參考附圖的說明意在說明本發明的各種實施例而非代表僅有的實施例(複數實施例)。在某些情況中，說明包含用以提供對本發明實施例(複數實施例)之瞭解的特定細節。然而，熟知此項技藝者當明白，本發明之實施例(複數實施例)可在缺乏此些特定細節的情況下實施。在某些情況中，習知的結構與元件可能會以方塊圖的形式顯示以免模糊本發明的概念。
說明書中提及「一實施例」係指，與一實施例關連的一特定特徵、結構、或特性係包含於本發明的至少一實施例中。是以，在說明書各處所述之「在一實施例中」並不一定指相同的一實施例。又，在一或多個實施例中可以任何適合的方式組合特定的特徵、結構、或特性。又，本發明的實施例意在涵蓋其所有修改及變化。
必須注意，除非另外明白指出，否則在說明書及申請專利範圍中所用的單數詞「一」及「該」包含複數。即，除非明白另外指出，否則文中所用的「一」、「該」等詞具有「一或多」的意義。此外，文中可用之應瞭解「上」、「側」、「高度」、「寬度」、「較高」、「較低」、「內部」、「在內」等詞僅在說明參考點但不必要將本發明的實施例限制至任何特定的位向或配置。又，「第一」、「第二」、「第三」等詞僅識別文中所揭露之複數部分、元件、步驟、操作、功能、及/或參考點中的一者，因此類似地不必將本發明的實施例限制至任何特定的位向或配置。
又，「大約」、「近似」、「次要」、及類似的詞大致上指一些範圍，此些範圍包含在某些實施例中之一界限20%、10%、或可能5%內的識別數值以及其間的任何數值。
文中所用之「基板」或「目標基板」等詞大致上指根據本發明所處理的物體。基板可包含一裝置的任何材料部分或結構，尤其是一半導體或其他電子裝置，且可例如是一基礎基板結構如一半導體晶圓、光罩、或一基礎基板結構上方或上的一膜層如一薄膜。是以，基板不限於任何特定的基礎結構、下方層或上方層、圖案化或未圖案化的，而是應被認為是包含任何此類膜層或基礎結構以及此些膜層及/或基礎結構的任何組合。本文可指涉特定類型的基板，但其作為例示目的。
文中的技術包含用以產生具有閘極及源極-汲極(S/D)區域之半導體裝置之延伸區域的整合與硬體方法。圖1為根據文中實施例之形成具有延伸區域之半導體裝置之一例示性製造程序的流程圖。此程序始於一中間裝置結構，此中間裝置結構包含在形成S/D區域之前其中具有通道區域的閘極結構。方法100始於S101，使通道區域的一端陷入閘極結構中以形成一凹陷部。凹陷部較佳地深到足以提供用以形成閘極結構中之一延伸區域的空間但淺得足以避免閘極結構材料(如取代閘極材料)暴露至源極-汲極區域的製程、且類似地避免源極-汲極區域材料及/或延伸區域材料暴露至閘極製程(如取代閘極之移除)。凹陷部可藉由移除通道材料而形成，下面將參考特定實例更進一步討論。
一旦在裝置的閘極結構中形成了凹陷部，如S103所示延伸區域係至少部分地形成在凹陷部內。在一實例中，延伸區域可藉由自步驟S101所形成之凹陷部中所暴露之通道材料的末端磊晶成長所形成。就此點而言，凹陷部可提供一「導引」結構如磊晶成長用的一通道以確保最終的延伸區域與凹陷部的形狀(或者，例如是已移除之通道材料的形狀)相匹配。延伸區域所具有之材料組成係不同於通道材料的材料組成以在通道區域內造成應變而增進半導體裝置的效能。例如，在通道區域為矽(Si)時延伸區域可為矽鍺(SiGe)，反之亦然，即SiGe通道配Si延伸區域。延伸材料可富化及/或摻雜以影響半導體裝置的操作特性。例如，當延伸材料為SiGe時，半導體裝置可被暴露至富化程序以增加鍺的相對量。可在延伸區域中提供添加物如半導體摻質或其他材料如碳或其他中性性種以影響裝置特性。此類材料可藉由磊晶成長、擴散、或其他半導體程序原位添加。在一實施例中，可使用材料如B2 O3 、Ga、ZnO、TiO以將接觸金屬的功函數偏向源極與汲極。
一旦在通道的一端處形成延伸區域後，如步驟S105中所見，在裝置與閘極結構相鄰的S/D區域內形成經摻雜的S/D接觸件。因此延伸區域座落於通道之末端與 S/D接觸件之間，故延伸區域將通道連接至通過閘極結構之一部分如閘極間隙壁的S/D接觸件。在S/D接觸件材料(及延伸材料)中可使用各種摻質材料。例如，針對p通道裝置可以硼摻雜S/D接觸件或針對n通道裝置可以磷摻雜S/D接觸件。此些摻質可在形成S-D 接觸件時原位提供及/或藉由後續的製程如離子植入提供。可選擇性地執行尖峰式退火製程以將摻質自S/D接觸件擴散至延伸區域中及/或更進一步客製化存在於已形成之延伸區域內之摻質的擴散輪廓。退火製程亦可將摻質擴散至原始的通道材料中。
一旦形成S/D接觸件後，可進行傳統製程如打開取代閘極、移除通道材料、針對通道的閘極金屬化、S/D金屬化等，下面將更進一步討論。
文中用以提供延伸區域的技術可與下列者相關：利用環繞式閘極製程的裝置製造，將奈米線或奈米薄片納入奈米線場效電晶體(FET)及/或堆疊互補FET裝置中。環繞式閘極(GAA)為一FET裝置，其中一金屬閘極實體圍繞一矽或矽/鍺奈米線。GAA為三閘極製程的更進一步延伸，在三閘極中閘極圍繞一矽或矽/鍺鰭；在鰭式FET中閘極圍繞四側中的三側上，但在GAA FET裝置中閘極圍繞一特定通道的所有側(不論該特定通道具有矩形或圓形的橫剖面)。GAA FET裝置的一類型為奈米線FET。
在奈米線FET裝置中，電流係藉由S/D接觸件供給通過奈米線或奈米薄片通道，S/D接觸件中的摻雜半導體材料(如SiGe或Si)係藉由連接至裝置之上層內連線及/或金屬化層的金屬S/D電極而帶電。以磊晶成長的摻雜半導體材料例如可額外地提供應變機制以增加通過FET的驅動電流。本發明之發明人體認到，可在奈米線或奈米薄片半導體裝置中形成S/D磊晶延伸部以滿足例如裝置效能或設計規格。根據本發明，此類延伸部可增加奈米線通道之末端處的應變以例如增進驅動電流。
圖2為根據本發明實施例之具有複數延伸區域之多通道 FET裝置的橫剖面圖。裝置 200包含一閘極結構及耦合至閘極結構的複數源極-汲極區域而形成一奈米線FET裝置。在所示的實施例中，閘極結構包含複數奈米線110，奈米線110具有裝置200(即多通道裝置)之電流通道的功能。閘極結構亦包含填充金屬160、功函數材料(WFM) 170、及圍繞奈米線110的高介電常數介電材料180、及覆蓋此些材料的閘極蓋層125。在圖1的實施例中，閘極間隙壁120亦被認為是閘極結構的一部分且圍繞奈米線110的相對末端區域。
裝置200的複數S/D區域包含形成在閘極結構之任一側上並與閘極間隙壁120相鄰的S/D接觸件112a與112b。S/D接觸件112a與112b係被在S/D區域中形成S/D電極(亦稱為S/D條)的S/D金屬130所圍繞。在圖1中，S/D接觸件112a與112b係彼此連接或合併且金屬130為S/D接觸件112a與112b兩者提供一單一S/D電極。或者或此外，在某些實施例中，S/D區域112a與112b可分離以對每一奈米線110提供分離的接觸件，下面將參考圖5討論。蝕刻停止層(ESL)140與淺溝槽隔離(STI)氧化物覆層150亦顯示於裝置200中。
結構200亦包含多個奈米線延伸區域111a、111b，奈米線延伸區域111a、111b係源於複數奈米線110之末端處閘極間隙壁120中的刻痕(或凹陷部)內。是以，在圖2的實施例中，延伸區域111a與111b經由閘極間隙壁120中的開口將奈米線110連接至S/D接觸件112a與112b。延伸區域111a與111b可受到摻雜及/或可在奈米線110的末端處提供較大的應變以改善裝置效能。延伸區域111a與111b係由一延伸材料所形成，此延伸材料所具有的組成係不同於S/D接觸件之材料的組成。
圖3為製造具有圖2之結構200之特定裝置用之一例示性程序的流程圖。圖4A-4J例示圖3之程序中各種階段處的結構。如先前技術中所已知的，奈米線或奈米薄片可自交替半導體材料如Si與SiGe的「鰭」 結構所形成。矽奈米線的形成可經由等向性蝕刻鰭中的SiGe 及形成閘極間隙壁材料而達成，閘極間隙壁材料於閘極結構之任一端上之矽線的末端處終止。類似地，SiGe 奈米線可藉著相對於SiGe選擇性地蝕刻鰭中的Si而加以形成。文中的技術可應用至Si與SiGe奈米線或奈米薄片以及其他類似的半導體結構。為了便於解釋文中的實施例，圖3與4A-4J中的說明係針對製造矽奈米線的程序。是以，圖3與4A-4J揭露製造半導體裝置之矽奈米線用之延伸區域的整合及硬體方法。
圖3之方法300可始於一半導體結構如圖4A 中所示的例示性結構400A。結構400A顯示在裝置程序中之一中間階段處的閘極結構。結構400A包含一鰭結構的複數Si奈米線410與SiGe區域415、以及多晶矽材料417。SiGe 415與多晶矽417為犧牲層，在製程中後續會受到移除以釋放奈米線410。SiGe 區域415具有大約20%的鍺(Ge)，但可使用其他的化學計量。在結構400A中，包含複數奈米線410的鰭結構係受到襯墊層418如SiO的保護，多晶矽係受到蓋層425的保護。結構400A可被稱為「取代閘極」。
結構400A亦包含纏繞取代閘極之相對側上之奈米線410之末端區域的複數閘極間隙壁420。閘極間隙壁420能使閘極區域與最終裝置的S/D區域電絕緣。亦顯示ESL(蝕刻停止層)440與STI(矽槽溝絕緣)氧化物450。
在圖4B中例示結構400A之橫剖面的三維(3D)示圖。在圖4B中，可更明顯地看出複數Si/SiGe鰭延伸通過由多晶矽417所構成的取代閘極且奈米線410延伸通過閘極間隙壁420。
回到圖3，在程序的步驟S301中，將複數Si 奈米線410選擇性地蝕刻至閘極間隙壁420中以形成複數凹陷部。步驟S301的一例示性結果係例示於圖4C中。如所見，複數凹陷部410a與410b在具有厚度或寬度WG 的閘極間隙壁 420內具有深度Dr ，厚度或寬度WG 例如通常為30-100埃。並非移除奈米線410的材料而完全穿過閘極間隙壁420的寬度WG 。凹陷部的深度Dr 的範圍可自數埃至少於閘極間隙壁420之厚度或寬度WG 的任何深度。深度Dr 應足以在閘極間隙壁420內提供欲形成延伸區域用的區域，但應受限制以避免通過閘極間隙壁420的凹陷部410a與410b穿通(punch through)。完全的材料移除(即移除超過閘極間隙壁420的寬度)可使鰭中的複數SiGe區域415暴露至S/D區域的下游製程(如蝕刻)且類似地可使S/D材料暴露至閘極製程，這是非所欲的。是以，在某些實施例中，應設定目標的凹陷部深度Dr 以確保在考慮基板之下游製程步驟的製程控制限制及製造變異時不會發生穿通。
在某些實施例中，控制凹陷部深度Dr 俾使某些SiGe可自陷入之線的末端成長，且經由矽的凹陷蝕刻而在閘極間隙壁內產生通道有助於維持始於線之末端的一致性線形磊晶成長。在某些實施例中，最大深度可為低介電常數閘極間隙壁厚度的函數且與閘極間隙壁的厚度成正比。應注意，凹陷部並未貫穿整個低介電常數間隙壁。在某些實例中，取決於技術，低介電常數間隙壁的厚度可介於40A至80A之間而凹陷部的深度可介於10A至20A之間或大約低介電常數間隙壁之厚度的20-25%。
可經由原子層蝕刻(ALE)、類ALE、或經由選擇性的汽相蝕刻來控制複數凹陷部410a與410b的特定深度Dr 。三種製程對矽與矽鍺皆有優異的選擇比，在SiGe對Si的相反選擇比案例中亦同。 又，選擇比可與閘極間隙壁材料(如具有低介電常數值的材料)相關。在本發明的某些實例中，例如在具有SiGe線或Ge線的PMOS及具有Si線的NMOS中，針對低介電常數閘極間隙壁，可能期望Si與SiGe之間有此類選擇比。可使用其他方法來形成複數凹陷部410a 與410b。在一實例中，可利用例如TOKYO ELECTRON LTD.所製造的CERTAS設備經由等向汽向蝕刻製程來完成凹陷蝕刻。CERTAS設備蝕刻在矽線與閘極間隙壁材料之間例如可達到超過100：1的選擇比。或者，可經由原子層蝕刻(ALE)或類原子層蝕刻(類ALE)來執行凹陷蝕刻以用埃數量級的尺寸來選擇性地陷入矽線。
在圖3的步驟S303中，在凹陷部中的暴露矽奈米線410上進行SiGe的磊晶成長以產生複數延伸區域411a與411b(之後共同被稱為延伸區域411)。在一實施例中， 參考圖4D，延伸摻雜411可如通常的S/D 磊晶成長自陷入的奈米線410開始並延伸至S/D區域。然而，可使延伸區域 411的成長局限於凹陷部內。
由於在S301中所形成的複數凹陷部410a與410b並未暴露任何SiGe 415或閘極結構的多晶矽417(閘極間隙壁420內)，因此SiGe在延伸區域中的磊晶成長僅始於奈米線410的末端而不會始於閘極結構材料如SiGe 415。基於p線(即p通道)或n線(即n通道)的裝置可成長磊晶SiGe或磊晶Si。在圖3與4A-4J的實例中，延伸區域 411為SiGe磊晶。這提供了與Si奈米線410的晶格不匹配，而在奈米線通道中產生了能影響裝置特性的應變。
在某些實施例中，延伸區域411可摻雜摻質材料。取決於欲製造之裝置的類型可使用各種摻質材料。摻雜可在延伸區域 411的磊晶成長期間原位進行，或由成長延伸區域之後的後續程序進行。在圖3與4A-4J的例示性製程中，自Si 奈米線410的末端磊晶成長並原位摻雜硼SiGe：B 而摻雜SiGe 延伸區域411。SiGe：B的組成範圍可自20%的Ge(與鰭中之SiGe 415的Ge含量一致)至100%的Ge。 在某些實施例中，可較佳地使用範圍落在20%至50% Ge的延伸部作為起點，然後更進一步地使其富含Ge而得到更高的Ge%甚至於純 (100%)Ge。在某些實施例中，當Ge% ＜50%時可觀察到相對較少的磊晶成長缺陷。Ge% by 相對Ge%較高的磊晶成長可藉由緩衝層/漸進層來達到，緩衝層/漸進層之增加係用以克服Si與Ge之間的晶格不匹配。
在圖3的步驟S305中，移除任何閘極間隙壁420外(或凹陷部 410外)的磊晶成長。步驟S305之一例示性結果係例示於圖4E中。可蝕刻磊晶SiGe：B材料俾使材料大致上留在奈米線410之末端與閘極間隙壁420之外緣之間的區域中。是以，如在圖4E中所見，摻雜延伸區域411x被保留在凹陷部 410內。可利用例如TOKYO ELECTRON LTD.所製造的CERTAS設備經由汽化蝕刻製程或經由直下異向性蝕刻來完成SiGe：B的蝕刻，汽向蝕刻在Si與SiGe(相對於閘極間隙壁材料 420)之間的選擇比可超過100：1，在直下異向性蝕刻中閘極蓋層425與閘極間隙壁 420定義了可被蝕刻移除及可留下的延伸區域 411材料部分。
一旦移除多餘的磊晶成長(如閘極間隙壁420外的部分)後，在圖3的步驟S307中可富化留在凹陷部 410a與410b內的材料。如在圖4F中所見，摻雜延伸區域 411x變成經富化的摻雜延伸區域411xr。在所述的實例中，摻雜延伸區域 411x的SiGe：B富含鍺俾使摻雜延伸區域 411xr之SiGe：B提供之Ge量係高於磊晶成長之SiGe：B的Ge量。在一實例中，磊晶成長的SiGe：B包含20-70% Ge但富化的SiGe：B提供Ge含量的某個程度的百分比提昇。在某些實例中，磊晶SiGe的範圍可介於Si(80%)Ge(20%)上至Si(50%)Ge(50%)。
步驟S307的富化程序可以例如是電漿緻密化程序，電漿緻密化程序可藉由TOKYO ELECTRON LTD.所製造的SPA表面波電設備來執行。對於SiGe 的案例，SPA程序移除Si並在奈米線410的界面處留下更富鍺的材料。可使用其他的富化程序。延伸區域 411中更富含鍺不僅僅可在自延伸區域重新成長之奈米線410與S/D接觸件之間的界面處提供較高的摻雜濃度，亦可提供額外的應變讓較佳的驅動電流例如自S/D接觸件流經奈米線410。由於奈米線410並非通過閘極間隙壁420完全凹陷，因此在移除取代閘極420內之材料之前任何SPA處理皆不會影響取代閘極420內的Si 或SiGe。
一旦在奈米線410的末端處形成延伸區域411後， 可完成摻雜半導體材料的磊晶成長以形成複數S/D接觸件。因此延伸區域 411係位於奈米線410之末端與S/D接觸件412之間。在所討論的實施例中，在步驟309中，複數S/D接觸件412係自經富化之延伸區域 411xr磊晶成長歐成，經富化的延伸區域 411xr有效地成為複數S/D接觸件之摻雜延伸區域。此些S/D接觸件所具有的鍺含量可與經富化之延伸區域 411xr 的鍺含量一致。是以，S/D接觸件的SiGe：B 可為20% 至70%的Ge。
在形成複數S/D接觸件412之後，可選擇性地執行尖峰退火程序。可執行S/D尖峰退火程序以將來自S/D接觸件412的硼摻質驅趕至延伸區域 411xr中以及矽線410的末端中。步驟S309之的例示性結果係例示於圖4G中。
一旦完成S/D接觸件412後，可進行傳統的奈米線或奈米薄片程序。尤其，在尖峰退火之後，可如S311所示移除閘極蓋層與多晶矽。可藉由選擇性的蝕刻程序打開取代閘極上方的閘極蓋層425並經由濕式程序或經由汽相蝕刻程序異性向移除多晶矽417。結果係顯示於圖4H中。Si/SiGe 鰭(即複數Si 奈米線410與SiGe區域415)係受到形成取代閘極模組之前沉積在鰭上部上之選擇性的襯墊層418的保護而不被此多晶矽移除蝕刻程序影響。在複數S/D接觸件412中經摻雜的SiGe係藉著以選擇性材料如可流動式的氧化物(此處未顯示)而受到保護而不被蝕刻，可流動式的氧化物在移除閘極蓋層之前可被向下研磨至與閘極蓋層425等高。
在圖3的步驟S313中，釋放複數Si 奈米線410以提供圖4I的結構。更具體而言，在已自取代閘極420內移除多晶矽417後，可移除保護取代閘極內之Si/SiGe鰭(即複數Si 奈米線410與SiGe 415)的襯墊層418。複數S/D接觸件415之經摻雜的SiGe材料再次因埋在非選擇性的薄膜如可流動式的SiO內而受到保護。SiGe區域415可經由汽相蝕刻移除，汽相蝕刻可為純等向的且對於欲被釋放的Si 奈米線410能達到超過100：1的選擇比。此類選擇性蝕刻程序可由例如TOKYO ELECTRON LTD.所製造的CERTAS系統來施行。一旦自取代閘極420內部移除SiGe後，如圖4I中所見，實質上留在閘極間隙壁420內的為在閘極的每一端上受到閘極間隙壁420支撐的複數奈米線410，閘極間隙壁420在閘極模組產生程序的早期中纏繞奈米線410。
在步驟S315中，沉積高介電常數材料、功函數材料、及填充金屬材料圍繞奈米線410與閘極間隙壁420內部，形成所謂的環繞式閘極(GAA)，在GAA中摻雜延伸411維持在閘極間隙壁420之終端處之奈米線410的末端處。步驟S315的一例示性結果係例示於圖4J中。在圖4J中，閘極間隙壁420中的高介電常數材料480、功函數金屬470、及填充金屬460可為凹陷的且可受到介電蓋層425的覆蓋。接著可進行自對準接觸件(SAC)蝕刻以自S/D區域移除SiO (此圖中未顯示SiO)接著以金屬填充S/D條而形成金屬S/D電極。一例示性的結果係例示於先前已討論的圖2中。
延伸區域可用於非圖2之多通道奈米線FET裝置的GAA裝置中。GAA或奈米線FET之眾多優點中的一優點為，裝置可被製造為互補的並使n-FET與p-FET(n型FET材料與p型FET材料)的線彼此上下堆疊以提供邏輯裝置的大幅面積縮減。本發明之發明人體認到，延伸摻雜可被用來補償相對於多通道 FET裝置如圖2中所示之裝置的較小源極/汲極接觸尺寸，其中S/D磊晶能成長並在上線與下線之間實體接觸。對於互補FET的應用而言，上線與下線係獨立地對應至nFET或pFET且在S/D條區域內係藉由介電薄膜所分離並可經由一共同的閘極或經由一經修改的堆疊PMOS/NMOS 閘極而連通。在互補FET裝置製造程序中鰭深寬比的特定尺寸需求下，因為需要獨立地隔絕每一通道，故互補裝置之S/D接觸件的尺寸會小於傳統多通道裝置之S/D接觸件的尺寸。本發明之發明人體認到，延伸區域可改善裝置效能而補償此類較小的S/D接觸件面積。
圖5為根據本發明實施例之具有延伸區域之堆疊奈米線互補FET裝置的橫剖面圖。互補裝置500包含一奈米線n-FET裝置作為上裝置及設置於其下之一奈米線p-FET裝置作為下裝置。如所見，裝置500包含一閘極結構及複數S/D區域以形成一互補奈米線FET裝置。在所示的實施例中，閘極結構 包含奈米線210與210’、圍繞奈米線210、210’的填充金屬260、功函數材料(WFM)270、高介電常數介電材料280、以及覆蓋此些材料的閘極蓋層225。閘極間隙壁 220亦被視為是閘極結構的一部分且纏繞奈米線210與210’的相對區域。蝕刻停止層(ESL)240與淺溝槽隔離(STI)氧化物蓋層250亦顯示於裝置500中。
裝置500的複數S/D區域包含形成在閘極結構之任一側上並與閘極間隙壁220相鄰的S/D接觸件212a與212b。S/D接觸件212a與212b每一者係受到在S/D區域中分別形成S/D電極235與230之S/D金屬的圍繞。NFET線210係耦合至上S/D金屬235(亦被稱為上金屬電極)而pFET線210’係耦合至下S/D金屬230(亦被稱為下金屬電極)。上金屬與下金屬係彼此上下堆疊且藉由介電層233所分離俾使nFET與pFET 為獨立的裝置。即，在圖5中，S/D接觸件212a與212b係分離以對奈米線210、210’每一者提供分離的接觸件，這可導致比圖2之多通道裝置更小的電極接觸面積。
奈米線延伸區域211a、211b源於奈米線210之末端處之閘極間隙壁220中的刻痕(或凹陷部)內。是以，在圖5的實施例中，延伸區域211a與211b經由閘極間隙壁220的對應開口而將奈米線210與210’連接至 S/D接觸件212a與212b。延伸區域211a與211b可在 奈米線210、210’的末端處提供較大的應變以提供較佳的裝置效能而補償較小的電極接觸面積。例如，如上面針對圖3與4A-4J所討論的延伸區域可富含及/或摻雜摻雜材料以達成奈米線通道區域上的應變。富化與摻雜材料大致上取決於裝置的導電性。
在上面的說明中，文中所述之不同步驟的討論順序僅是為了清楚明白的目的。大致上，此些步驟可以任何適合的順序施行。此外，雖然不同特徵、技術、配置中的每一者可在本發明的不同處討論，但本發明欲使每一概念能彼此獨立執行或彼此結合執行。因此，本發明可以許多不同的方式體現與看待。
雖然已說明了某些實施例，但此些實施例僅以例示方式呈現，其意不在限制本發明的範疇。的確，文中所述之新穎的方法、設備、及系統可以各種其他的形式體現；又，可在不脫離本發明之精神的情況下對文中所述之方法、設備、及系統進行各種省略、取代、及變化。隨附的申請專利範圍及其等效物意在涵蓋落在本發明之範疇與精神內的此類形式或修改。例如，可針對雲端計算架構此技術，藉此在由網路所鏈結的複數設備之間分享單一功能及合作處理單一功能。
100‧‧‧方法
110‧‧‧奈米線
111a‧‧‧延伸區域
111b‧‧‧延伸區域
112a‧‧‧S/D接觸件
112b‧‧‧S/D接觸件
120‧‧‧閘極間隙壁
125‧‧‧閘極蓋層
130‧‧‧S/D金屬
140‧‧‧蝕刻停止層
150‧‧‧淺溝槽隔離氧化物覆層
160‧‧‧填充金屬
170‧‧‧功函數材料
180‧‧‧高介電常數介電材料
200‧‧‧裝置
210‧‧‧奈米線
210’‧‧‧奈米線
211a‧‧‧延伸區域
211b‧‧‧延伸區域
212a‧‧‧S/D接觸件
212b‧‧‧S/D接觸件
220‧‧‧閘極間隙壁
225‧‧‧閘極蓋層
230‧‧‧S/D電極
233‧‧‧介電層
235‧‧‧S/D電極
240‧‧‧蝕刻停止層
250‧‧‧淺溝槽隔離氧化物蓋層
260‧‧‧填充金屬
270‧‧‧功函數材料
280‧‧‧高介電常數介電材料
300‧‧‧方法
400A‧‧‧結構
410‧‧‧奈米線
410a‧‧‧凹陷部
410b‧‧‧凹陷部
411‧‧‧延伸摻雜
411a‧‧‧延伸區域
411b‧‧‧延伸區域
411x‧‧‧摻雜延伸區域
411xr‧‧‧經富化的摻雜延伸區域
412‧‧‧S/D接觸件
415‧‧‧SiGe區域
417‧‧‧多晶矽材料
418‧‧‧襯墊層
420‧‧‧閘極間隙壁
425‧‧‧蓋層
440‧‧‧蝕刻停止層
450‧‧‧矽槽溝絕緣氧化物
460‧‧‧填充金屬
470‧‧‧功函數金屬
480‧‧‧高介電常數材料
500‧‧‧互補裝置
S101‧‧‧步驟
S301‧‧‧步驟
S303‧‧‧步驟
S305‧‧‧步驟
S307‧‧‧步驟
S309‧‧‧步驟
S311‧‧‧步驟
S313‧‧‧步驟
S315‧‧‧步驟
被包含於說明書中並構成說明書之一部分的附圖與文中說明例示一或多個實施例並加以解釋。附圖並非一定依比例繪製。附圖中所示的任何數值尺寸皆僅供例示用途且可能或可不必代表真實或較佳的數值或尺寸。在適合之處，某些或所有的特徵可能不被例示以助於根本特徵的說明。在圖示中：
圖1為根據本發明之某些態樣之形成延伸區域用之一製造程序的流程圖；
圖2為根據本發明之某些態樣之一半導體裝置的橫剖面圖；
圖3為根據本發明之某些態樣之延伸摻雜用之一製造程序的流程圖；
圖4A為根據本發明之某些態樣之用以製造圖1之裝置之一例示性起始結構的橫剖面圖；
圖4B為根據本發明之某些態樣之圖4A之例示性結構的三維圖；
圖4C為根據本發明之某些態樣之圖3之製造程序之完成第一步驟後之半導體的橫剖面圖；
圖4D為根據本發明之某些態樣之圖3之製造程序之完成第二步驟後之半導體的橫剖面圖；
圖4E為根據本發明之某些態樣之圖3之製造程序之完成第三步驟後之半導體的橫剖面圖；
圖4F為根據本發明之某些態樣之圖3之製造程序之完成第四步驟後之半導體的橫剖面圖；
圖4G為根據本發明之某些態樣之圖3之製造程序之完成第五步驟後之半導體的橫剖面圖；
圖4H為根據本發明之某些態樣之圖3之製造程序之完成第六步驟後之半導體的橫剖面圖；
圖4I為根據本發明之某些態樣之圖3之製造程序之完成第七步驟後之半導體的橫剖面圖；
圖4J為根據本發明之某些態樣之圖3之製造程序之完成第八步驟後之半導體的橫剖面圖；及
圖5為根據本發明之某些態樣之一第二半導體裝置的橫剖面圖。

Claims (20)

  1. 一種具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，此方法包含： 蝕刻一通道區域俾使該通道區域的一端在圍繞該通道區域的一閘極結構內形成一凹陷部； 形成一延伸區域與該通道區域接觸並至少部分填滿該凹陷部，其中該延伸區域的延伸材料所具有的組成係不同於該通道區域之通道材料的組成，俾以在該通道區域中產生一應變；及 形成一源極-汲極區域與該延伸區域接觸並與該閘極結構相鄰。
  2. 如申請專利範圍第1項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中該通道區域包含一奈米線且該閘極結構包含圍繞該奈米線之一端的一閘極間隙壁，該蝕刻步驟包含選擇性蝕刻該奈米線的該端以在該閘極間隙壁內形成該凹陷部。
  3. 如申請專利範圍第2項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中選擇性蝕刻該奈米線包含蝕刻該奈米線一深度，該深度係小於該閘極間隙壁的一厚度。
  4. 如申請專利範圍第1項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中形成該延伸區域包含自該奈米線的材料磊晶成長該延伸材料。
  5. 如申請專利範圍第4項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中形成該延伸區域包含對該延伸材料進行摻雜。
  6. 如申請專利範圍第5項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中對該延伸材料進行摻雜包含在磊晶成長該延伸材料期間進行原位摻雜。
  7. 如申請專利範圍第5項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中對該延伸材料進行摻雜包含退火以使摻質自源極-汲極接觸件擴散至該延伸區域中。
  8. 如申請專利範圍第4項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中形成該延伸區域包含： 磊晶成長該延伸材料俾使該延伸材料包含超出該閘極結構之一表面之該凹陷部外部的額外延伸材料；及 移除該額外延伸材料俾使該延伸材料填充該凹陷部並與該閘極結構的該表面實質上齊平。
  9. 如申請專利範圍第1項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中形成該延伸區域包含富化該延伸材料。
  10. 如申請專利範圍第9項之具有通道及耦合至通道之源極-汲極之半導體裝置的形成方法，其中形成該源極-汲極區域包含自該經富化的延伸材料磊晶成長源極-汲極材料。
  11. 一種半導體裝置，包含： 一閘極結構，包含一閘極間隙壁； 一通道，延伸通過該閘極結構俾使該通道的一端陷入該閘極間隙壁中的一凹陷部內； 一延伸區域，係與該凹陷部內之該通道的該端接觸，該延伸區域係由一延伸材料所形成，且該延伸材料的組成係不同於該通道之通道材料的組成，俾以在該通道中提供一應變；及 一源極-汲極接觸件，係與該延伸區域接觸並與該閘極結構相鄰。
  12. 如申請專利範圍第11項之半導體裝置，其中該通道包含一奈米線，且該奈米線的一端凹陷的一深度係小於該閘極間隙壁的一厚度。
  13. 如申請專利範圍第12項之半導體裝置，其中該閘極間隙壁具有30-100埃之間的厚度。
  14. 如申請專利範圍第13項之半導體裝置，其中該奈米線包含矽。
  15. 如申請專利範圍第13項之半導體裝置，其中該延伸區域包含SiGe。
  16. 如申請專利範圍第15項之半導體裝置，其中該延伸區域係經Ge富化。
  17. 如申請專利範圍第16項之半導體裝置，其中該延伸區域包含經富化的SiGe，其包含 20%至70%的鍺含量範圍。
  18. 一種半導體裝置，包含： 一p型橫向奈米線，藉由通過一閘極間隙壁中之一第一開口的一第一連接結構而耦合至一p型源極-汲極區域； 一n型橫向奈米線，係以和該p型橫向奈米線垂直堆疊的關係而設置，且係藉由通過該閘極間隙壁中之一第二開口的一第二連接結構而耦合至一n型源極-汲極區域；及 一電極結構，包含接觸該p型源極-汲極區域的一p型電極以及接觸該n型源極-汲極區域的一n型電極，該n型電極係藉由介電材料而與該p型電極電絕緣，其中該第一連接結構與該第二連接結構中的至少一者在該閘極間隙壁中的一對應開口內包含一延伸摻雜區域。
  19. 如申請專利範圍第18項之半導體裝置，其中該至少一連接結構包含經富化的SiGe。
  20. 如申請專利範圍第18項之半導體裝置，其中該經富化之SiGe包含20%至70%的鍺含量範圍。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI832259B (zh) * 2021-07-09 2024-02-11 台灣積體電路製造股份有限公司 奈米結構電晶體裝置及半導體裝置之形成方法

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653289B1 (en) 2016-09-19 2017-05-16 International Business Machines Corporation Fabrication of nano-sheet transistors with different threshold voltages
US10833193B2 (en) 2016-09-30 2020-11-10 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device, method of manufacturing the same and electronic device including the device
CN106298778A (zh) 2016-09-30 2017-01-04 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
US11056592B2 (en) 2017-06-30 2021-07-06 Intel Corporation Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer
CN109904074B (zh) * 2017-12-11 2022-04-08 中芯国际集成电路制造(北京)有限公司 全包围栅场效应晶体管及其制造方法
US10439049B2 (en) * 2017-12-19 2019-10-08 International Business Machines Corporation Nanosheet device with close source drain proximity
US10896956B2 (en) * 2017-12-22 2021-01-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Field effect transistor with reduced contact resistance
US10304833B1 (en) * 2018-02-19 2019-05-28 Globalfoundries Inc. Method of forming complementary nano-sheet/wire transistor devices with same depth contacts
CN111699550B (zh) * 2018-03-19 2023-05-09 东京毅力科创株式会社 三维器件及其形成方法
US11062959B2 (en) * 2018-03-19 2021-07-13 International Business Machines Corporation Inner spacer and junction formation for integrating extended-gate and standard-gate nanosheet transistors
US10593673B2 (en) 2018-05-15 2020-03-17 International Business Machines Corporation Nanosheet with single epitaxial stack forming off-set dual material channels for gate-all-around CMOS
US10483166B1 (en) 2018-06-26 2019-11-19 International Business Machines Corporation Vertically stacked transistors
US10388569B1 (en) 2018-06-26 2019-08-20 International Business Machines Corporation Formation of stacked nanosheet semiconductor devices
US10615256B2 (en) 2018-06-27 2020-04-07 International Business Machines Corporation Nanosheet transistor gate structure having reduced parasitic capacitance
CN110729189B (zh) * 2018-07-17 2023-06-30 中芯国际集成电路制造（天津）有限公司 半导体器件及其制造方法
US11588052B2 (en) * 2018-08-06 2023-02-21 Intel Corporation Sub-Fin isolation schemes for gate-all-around transistor devices
US10608083B2 (en) * 2018-08-31 2020-03-31 International Business Machines Corporation Non-planar field effect transistor devices with low-resistance metallic gate structures
US11450739B2 (en) 2018-09-14 2022-09-20 Intel Corporation Germanium-rich nanowire transistor with relaxed buffer layer
US11276691B2 (en) * 2018-09-18 2022-03-15 Intel Corporation Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths
US11398474B2 (en) 2018-09-18 2022-07-26 Intel Corporation Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions
KR102509307B1 (ko) 2018-09-19 2023-03-10 삼성전자주식회사 반도체 장치
US11355608B2 (en) * 2018-09-24 2022-06-07 Intel Corporation Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures
WO2020065732A1 (ja) 2018-09-25 2020-04-02 株式会社ソシオネクスト 半導体装置及びその製造方法
US11538806B2 (en) 2018-09-27 2022-12-27 Intel Corporation Gate-all-around integrated circuit structures having high mobility
US11527612B2 (en) * 2018-09-28 2022-12-13 Intel Corporation Gate-all-around integrated circuit structures having vertically discrete source or drain structures
US11469299B2 (en) 2018-09-28 2022-10-11 Intel Corporation Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers
US10741456B2 (en) 2018-10-10 2020-08-11 International Business Machines Corporation Vertically stacked nanosheet CMOS transistor
EP3660922A1 (en) 2018-11-27 2020-06-03 IMEC vzw A method of forming a stack of insulated cmos devices
EP3660891B1 (en) 2018-11-27 2023-06-07 IMEC vzw A method for forming a semiconductor device
FR3090998B1 (fr) 2018-12-21 2022-12-09 Commissariat Energie Atomique Architecture à transistors n et p superposes a structure de canal formee de nanofils
US11764263B2 (en) * 2019-01-04 2023-09-19 Intel Corporation Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches
US10991798B2 (en) * 2019-01-21 2021-04-27 International Business Machines Corporation Replacement sacrificial nanosheets having improved etch selectivity
US10832907B2 (en) 2019-02-15 2020-11-10 International Business Machines Corporation Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance
US11677026B2 (en) * 2019-03-04 2023-06-13 International Business Machines Corporation Transistor having wrap-around source/drain contacts
US10985279B2 (en) * 2019-03-13 2021-04-20 International Business Machines Corporation Source and drain epitaxy and isolation for gate structures
CN111755333B (zh) * 2019-03-27 2024-02-27 芯恩（青岛）集成电路有限公司 一种纳米片场效应晶体管及其制备方法
US11769836B2 (en) * 2019-05-07 2023-09-26 Intel Corporation Gate-all-around integrated circuit structures having nanowires with tight vertical spacing
KR20200132436A (ko) * 2019-05-17 2020-11-25 삼성전자주식회사 반도체 장치
KR20200136519A (ko) 2019-05-27 2020-12-08 삼성전자주식회사 반도체 장치
WO2020255801A1 (ja) * 2019-06-17 2020-12-24 株式会社ソシオネクスト 半導体記憶装置
WO2020255256A1 (ja) 2019-06-18 2020-12-24 株式会社ソシオネクスト 半導体装置
US10903365B2 (en) 2019-06-19 2021-01-26 International Business Machines Corporation Transistors with uniform source/drain epitaxy
US11942416B2 (en) * 2019-06-28 2024-03-26 Intel Corporation Sideways vias in isolation areas to contact interior layers in stacked devices
WO2020262248A1 (ja) 2019-06-28 2020-12-30 株式会社ソシオネクスト 半導体記憶装置
US11222964B2 (en) 2019-07-08 2022-01-11 Tokyo Electron Limited Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits
US10978573B2 (en) 2019-07-08 2021-04-13 International Business Machines Corporation Spacer-confined epitaxial growth
US11488947B2 (en) 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
US11315925B2 (en) * 2019-08-28 2022-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Uniform gate width for nanostructure devices
WO2021065590A1 (ja) * 2019-10-02 2021-04-08 株式会社ソシオネクスト 半導体集積回路装置および半導体集積回路装置の製造方法
US11735525B2 (en) 2019-10-21 2023-08-22 Tokyo Electron Limited Power delivery network for CFET with buried power rails
US11495540B2 (en) * 2019-10-22 2022-11-08 Tokyo Electron Limited Semiconductor apparatus having stacked devices and method of manufacture thereof
US11251080B2 (en) 2019-12-02 2022-02-15 Tokyo Electron Limited Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits
US11545497B2 (en) 2019-12-31 2023-01-03 Tokyo Electron Limited CFET SRAM bit cell with three stacked device decks
US11183561B2 (en) * 2020-01-07 2021-11-23 International Business Machines Corporation Nanosheet transistor with inner spacers
WO2021153169A1 (ja) * 2020-01-27 2021-08-05 株式会社ソシオネクスト 半導体記憶装置
US11581414B2 (en) * 2020-03-30 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around devices with optimized gate spacers and gate end dielectric
US11495661B2 (en) * 2020-04-07 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including gate barrier layer
EP3905338A1 (en) * 2020-04-27 2021-11-03 Imec VZW Strained semiconductor monocrystalline nanostructure
US11411180B2 (en) 2020-04-28 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Phase-change memory device and method
US20220005951A1 (en) * 2020-07-05 2022-01-06 International Business Machines Corporation Strained Semiconductor FET Devices with Epitaxial Quality Improvement
US11610977B2 (en) * 2020-07-28 2023-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming nano-sheet-based devices having inner spacer structures with different widths
US11665878B2 (en) 2020-09-30 2023-05-30 Tokyo Electron Limited CFET SRAM bit cell with two stacked device decks
US11380685B2 (en) * 2020-10-02 2022-07-05 Qualcomm Incorporated Semiconductor device with superlattice fin
US11489078B2 (en) * 2020-10-27 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Lightly-doped channel extensions
CN113013251A (zh) * 2021-02-26 2021-06-22 中之半导体科技(东莞)有限公司 一种具有栅极填充结构的mosfet管
US11723187B2 (en) 2021-03-16 2023-08-08 Tokyo Electron Limited Three-dimensional memory cell structure
US20230095007A1 (en) * 2021-09-24 2023-03-30 Intel Corporation Integrated circuit structures having metal-containing source or drain structures

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100392166B1 (ko) * 2000-03-17 2003-07-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법 및 반도체 장치
DE10240449B4 (de) * 2002-09-02 2009-06-10 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer dielektrischen Schicht mit geringem Leckstrom, wobei eine erhöhte kapazitive Kopplung erzeugt wird
US7566605B2 (en) * 2006-03-31 2009-07-28 Intel Corporation Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
US20080135949A1 (en) * 2006-12-08 2008-06-12 Agency For Science, Technology And Research Stacked silicon-germanium nanowire structure and method of forming the same
JP4310399B2 (ja) * 2006-12-08 2009-08-05 株式会社東芝 半導体装置及びその製造方法
TWI562313B (en) * 2010-09-06 2016-12-11 shu lu Chen Electrical switch using a recessed channel gated resistor structure and method for three dimensional integration of semiconductor device
US8753942B2 (en) * 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
CN104126222B (zh) * 2011-12-23 2017-06-13 英特尔公司 单轴应变纳米线结构
US8778768B1 (en) * 2013-03-12 2014-07-15 International Business Machines Corporation Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain
KR102083494B1 (ko) * 2013-10-02 2020-03-02 삼성전자 주식회사 나노와이어 트랜지스터를 포함하는 반도체 소자
US9570609B2 (en) * 2013-11-01 2017-02-14 Samsung Electronics Co., Ltd. Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same
US9590037B2 (en) * 2014-03-19 2017-03-07 International Business Machines Corporation p-FET with strained silicon-germanium channel
US9490340B2 (en) * 2014-06-18 2016-11-08 Globalfoundries Inc. Methods of forming nanowire devices with doped extension regions and the resulting devices
US9502518B2 (en) * 2014-06-23 2016-11-22 Stmicroelectronics, Inc. Multi-channel gate-all-around FET
US9647098B2 (en) * 2014-07-21 2017-05-09 Samsung Electronics Co., Ltd. Thermionically-overdriven tunnel FETs and methods of fabricating the same
US9362355B1 (en) * 2015-11-13 2016-06-07 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer
US9653289B1 (en) * 2016-09-19 2017-05-16 International Business Machines Corporation Fabrication of nano-sheet transistors with different threshold voltages
US9831254B1 (en) * 2016-09-22 2017-11-28 International Business Machines Corporation Multiple breakdown point low resistance anti-fuse structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI832259B (zh) * 2021-07-09 2024-02-11 台灣積體電路製造股份有限公司 奈米結構電晶體裝置及半導體裝置之形成方法

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