TW201816914A - Mounting method for electronic component and carrying jig applying the mounting method - Google Patents
Mounting method for electronic component and carrying jig applying the mounting method Download PDFInfo
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- TW201816914A TW201816914A TW105133869A TW105133869A TW201816914A TW 201816914 A TW201816914 A TW 201816914A TW 105133869 A TW105133869 A TW 105133869A TW 105133869 A TW105133869 A TW 105133869A TW 201816914 A TW201816914 A TW 201816914A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67772—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving removal of lid, door, cover
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
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Abstract
Description
本發明係有關一種電子構件之製法,尤指一種電子構件的置放製程及其應用之承載治具。 The present invention relates to a method for manufacturing an electronic component, and more particularly, to a process for placing an electronic component and a bearing fixture for application thereof.
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢,其主要係於同一電子產品上整合越來越多功能,但此同時亦要求電子產品體積輕薄,因此,為配合微小化發展的趨勢,業界遂藉由降低封裝基板之厚度,以達到電子產品多功能、小型化之目的。 With the vigorous development of the electronics industry, electronic products are gradually moving towards the trend of multifunctionality and high performance. They are mainly integrated on the same electronic product and become more and more multifunctional. In line with the trend of miniaturization, the industry has reduced the thickness of the packaging substrate to achieve the purpose of multi-function and miniaturization of electronic products.
然而,薄化後的封裝基板由於剛性較差且易受熱製程影響而變形,導致接置於該封裝基板上覆晶用之凸塊發生虛銲(non-wetting)的機率增加,故對於封裝基板於熱製程中之平整性及應力釋放的問題係藉由蓋件解決。 However, the thinned package substrate is deformed due to its poor rigidity and susceptible to the influence of the thermal process, which leads to an increase in the probability of non-wetting of bumps connected to the chip on the package substrate. The problems of flatness and stress relief in the thermal process are solved by the cover.
如第1圖所示,係為習知半導體封裝件4使用承載治具1於覆晶製程之剖面示意圖。首先,將一設有複數晶片41之封裝基板40設於一承載件10上,並將一蓋件11設於該承載件10上並壓蓋該封裝基板40,其中,該晶片41 係透過複數銲錫凸塊410覆晶接置於該封裝基板40上,接著,回銲(Reflow)該些銲錫凸塊410,其中,該封裝基板40雖於受熱後會產生形變,但藉由該蓋件11壓觸該封裝基板40,得以抑制該封裝基板40之外部變形。 As shown in FIG. 1, it is a schematic cross-sectional view of a conventional semiconductor package 4 using a carrier jig 1 in a flip-chip process. First, a package substrate 40 provided with a plurality of wafers 41 is provided on a carrier 10, and a cover member 11 is provided on the carrier 10 and presses the package substrate 40, wherein the wafer 41 is transmitted through a plurality of The solder bumps 410 are flip-chip placed on the package substrate 40, and then the solder bumps 410 are reflowed. The package substrate 40 is deformed after being heated, but is covered by the cover 11 Pressing against the packaging substrate 40 can suppress external deformation of the packaging substrate 40.
惟,習知覆晶製程中,藉由該蓋件11接觸該封裝基板40而限制該封裝基板40變形之方式,亦同時抑制該封裝基板40熱脹縮的空間,使該封裝基板40無法釋放其內部壓力,因而增加該封裝基板40的潛在變形量,以致於當該封裝基板40從該承載治具1中取出時,該封裝基板40的潛在變形量會使該封裝基板40發生翹曲之現象,造成該封裝基板40無法與該銲錫凸塊410有效接觸或接觸結合性不佳。 However, in the conventional flip-chip manufacturing process, the way in which the cover member 40 contacts the packaging substrate 40 to limit the deformation of the packaging substrate 40, and at the same time inhibit the thermal expansion and contraction of the packaging substrate 40, so that the packaging substrate 40 cannot be released. Due to its internal pressure, the amount of potential deformation of the package substrate 40 is increased, so that when the package substrate 40 is taken out from the carrying jig 1, the amount of potential deformation of the package substrate 40 may cause the package substrate 40 to warp. As a result, the package substrate 40 cannot be effectively contacted with the solder bump 410 or the contact bonding is poor.
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an urgent problem to be solved.
鑑於上述習知技術之種種缺失,本發明係提供一種應用於電子構件之承載治具,係包括:承載件,係用以承載基板,其中,該基板定義有至少一置放區;以及蓋件,係設於該承載件上,其中,該蓋件與該基板之間具有間隔,且該蓋件具有對應該置放區之至少一開口。 In view of the various shortcomings of the above-mentioned conventional technologies, the present invention provides a carrier fixture for electronic components, including: a carrier member for carrying a substrate, wherein the substrate defines at least one placement area; and a cover member Is arranged on the bearing member, wherein the cover member and the substrate have a space therebetween, and the cover member has at least one opening corresponding to the placement area.
本發明亦提供一種電子構件之置放製程,係包括:將一基板設於一承載件上,其中,該基板定義有至少一置放區;以及將一蓋件設於該承載件上,其中,該蓋件與該基板之間具有間隔,且該蓋件具有對應該置放區之至少一開 口。 The invention also provides a process for placing electronic components, comprising: placing a substrate on a carrier, wherein the substrate defines at least one placement area; and placing a cover on the carrier, wherein There is a space between the cover member and the substrate, and the cover member has at least one opening corresponding to the placement area.
前述之電子構件之置放製程及其應用之承載治具中,該基板具有複數該置放區,且該蓋件具有複數對應該置放區之開口。 In the aforementioned electronic component placement process and the application fixture therefor, the substrate has a plurality of the placement areas, and the cover has a plurality of openings corresponding to the placement areas.
前述之電子構件之置放製程及其應用之承載治具中,該置放區上係設置有電子元件。 In the aforementioned placement process of the electronic component and the application fixture thereof, the placement area is provided with electronic components.
前述之電子構件之置放製程及其應用之承載治具中,該電子元件係藉由複數導電元件設於該置放區上。例如,該間隔係大於該導電元件之高度。 In the aforementioned placement process of the electronic component and the application fixture thereof, the electronic component is provided on the placement area by a plurality of conductive components. For example, the interval is greater than the height of the conductive element.
前述之電子構件之置放製程及其應用之承載治具中,該蓋件復包含有用以接觸該基板的支撐部。例如,該基板復定義有對應該置放區周圍之切割道,該支撐部之位置係對應該切割道之位置,且該支撐部之寬度係小於或等於該切割道之寬度。 In the aforementioned placement process of the electronic component and the supporting fixture to which it is applied, the cover member further includes a support portion for contacting the substrate. For example, the substrate is defined with a cutting track corresponding to the surrounding of the placement area, the position of the supporting portion corresponds to the position of the cutting track, and the width of the supporting portion is less than or equal to the width of the cutting track.
前述之電子構件之置放製程及其應用之承載治具中,該蓋件與該基板間之間隔中復形成有緩衝層。 In the aforementioned placement process of the electronic component and the application fixture therefor, a buffer layer is formed in the space between the cover member and the substrate.
由上可知,本發明之電子構件之置放製程及其應用之承載治具,主要藉由當該基板設於該承載件上時,該蓋件與該基板之間具有間隔,以於進行回銲作業時,該間隔可作為該基板之熱脹縮空間,使該基板能釋放熱脹縮的壓力,故相較於習知技術,當該基板從本發明之承載治具中取出時,該基板不會發生翹曲之現象,因而能避免該基板與用以接置電子元件之導電元件之間發生接觸不良之問題。 It can be known from the above that the placing process of the electronic component of the present invention and the carrying fixture of the application mainly include that when the substrate is provided on the carrier, there is a space between the cover and the substrate to facilitate the return During the welding operation, the space can be used as the thermal expansion and contraction space of the substrate, so that the substrate can release the pressure of thermal expansion and contraction. Therefore, compared with the conventional technology, when the substrate is taken out of the carrying fixture of the present invention, the The substrate does not warp, so the problem of poor contact between the substrate and the conductive components used to connect electronic components can be avoided.
1,2‧‧‧承載治具 1,2‧‧‧bearing fixture
10,20‧‧‧承載件 10,20‧‧‧bearing parts
11,21‧‧‧蓋件 11,21‧‧‧ cover
210‧‧‧開口 210‧‧‧ opening
211‧‧‧支撐部 211‧‧‧ support
212‧‧‧接腳 212‧‧‧pin
3‧‧‧電子構件 3‧‧‧electronic components
30‧‧‧基板 30‧‧‧ substrate
300‧‧‧置放區 300‧‧‧ placement area
31‧‧‧電子元件 31‧‧‧Electronic components
310‧‧‧導電元件 310‧‧‧ conductive element
32‧‧‧緩衝層 32‧‧‧ buffer layer
4‧‧‧半導體封裝件 4‧‧‧ semiconductor package
40‧‧‧封裝基板 40‧‧‧ package substrate
41‧‧‧晶片 41‧‧‧Chip
410‧‧‧銲錫凸塊 410‧‧‧solder bump
t‧‧‧間隔 t‧‧‧ interval
h‧‧‧高度 h‧‧‧ height
d,r‧‧‧寬度 d, r‧‧‧width
S‧‧‧切割道 S‧‧‧ Cutting Road
第1圖係為習知半導體封裝件之覆晶製程的剖面示意圖;第2A及2B圖係為本發明之電子構件之置放製程之剖面示意圖;以及第3A及3B圖係為對應第2B圖的不同實施例之剖面示意圖。 Fig. 1 is a schematic cross-sectional view of a conventional flip-chip manufacturing process of a semiconductor package; Figs. 2A and 2B are cross-sectional schematic views of an electronic component placement process of the present invention; and Figs. 3A and 3B are corresponding to Fig. 2B. Schematic sectional views of different embodiments.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The limited conditions are not technically significant. Any modification of the structure, change of the proportional relationship, or adjustment of the size shall still fall within the scope of this invention without affecting the effects and goals that the invention can produce. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not intended to limit the scope of the present invention. Changes or adjustments in their relative relationships shall be considered to be the scope of the present invention without substantial changes in the technical content.
第2A圖係為本發明之應用於電子構件之承載治具2的剖面示意圖。 FIG. 2A is a schematic cross-sectional view of a load-bearing jig 2 applied to an electronic component according to the present invention.
如第2A圖所示,該承載治具2係包括一承載件20以及一蓋件21。 As shown in FIG. 2A, the supporting jig 2 includes a supporting member 20 and a cover member 21.
所述之承載件20係用以承載一基板30,且該基板30定義有複數置放區300。 The carrier 20 is used to carry a substrate 30, and the substrate 30 defines a plurality of placement areas 300.
所述之蓋件21係藉由至少一接腳212設於該承載件20上且具有分別對應該置放區300之複數開口210,並於該基板30設於該承載件20上時,該蓋件21與該基板30之間具有間隔t。 The cover 21 is provided on the carrier 20 through at least one pin 212 and has a plurality of openings 210 corresponding to the placement areas 300 respectively. When the substrate 30 is disposed on the carrier 20, the cover 21 There is a gap t between the cover member 21 and the substrate 30.
第2A至2B圖係為本發明之電子構件3之置放製程之剖面示意圖。 Figures 2A to 2B are schematic cross-sectional views of the placement process of the electronic component 3 of the present invention.
如第2A圖所示,以上述承載治具2為例,將一基板30設於該承載件20上,再將該蓋件21設於該承載件20上,且該蓋件21與該基板30之間具有間隔t。 As shown in FIG. 2A, taking the above-mentioned carrier jig 2 as an example, a substrate 30 is disposed on the carrier 20, and then the cover 21 is disposed on the carrier 20, and the cover 21 and the substrate There is an interval t between 30.
於本實施例中,該基板30具線路層(未圖示),其係例如為線路結構、無核心層之線路板或具有核心層之線路板。 In this embodiment, the substrate 30 has a circuit layer (not shown), which is, for example, a circuit structure, a circuit board without a core layer, or a circuit board with a core layer.
如第2B圖所示,對應該開口210將複數電子元件31設於該基板30之置放區300上,其中,該電子構件3係包括該基板30與該電子元件31。 As shown in FIG. 2B, a plurality of electronic components 31 are disposed on the placement area 300 of the substrate 30 corresponding to the opening 210. The electronic component 3 includes the substrate 30 and the electronic component 31.
於本實施例中,該電子元件31係為主動元件、被動元件或其二者組合等,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。具體地,該電子元件31係以複數如銲錫凸塊或銅柱之導電元件310覆晶結合該基板30之線路層上,且該間隔t係大於該導電元件310之高度h,再回銲該些導電元件310以將該電子元件31固 定於該基板30上。 In this embodiment, the electronic component 31 is an active component, a passive component, or a combination of the two, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. Specifically, the electronic component 31 is covered with a plurality of conductive elements 310 such as solder bumps or copper pillars on the circuit layer of the substrate 30, and the interval t is greater than the height h of the conductive element 310, and then the solder is re-soldered. The conductive components 310 are used to fix the electronic component 31 on the substrate 30.
然而,該電子元件31與該基板30之結合方式係依需求而定,並不限於上述覆晶方式,亦可為扇出方式、打線方式或其它方式。 However, the combination method of the electronic component 31 and the substrate 30 is determined according to requirements, and is not limited to the above-mentioned flip-chip method, and may also be a fan-out method, a wire bonding method, or other methods.
由於本發明中該蓋件21與該基板30之間具有間隔t,故當該基板30設於該承載件20上,,並進行熱製程(如回銲製程)時,該間隔t可作為該基板30之熱脹縮空間,使該基板30能釋放熱脹縮的壓力,故相較於習知技術,當該基板30從本發明之承載治具2中取出時,該基板30不會發生翹曲之現象,因而能避免該基板30與該導電元件310之間發生接觸不良之問題。 Since there is an interval t between the cover member 21 and the substrate 30 in the present invention, when the substrate 30 is disposed on the carrier 20 and a thermal process (such as a reflow process) is performed, the interval t can be used as the The thermal expansion and contraction space of the substrate 30 enables the substrate 30 to release the pressure of thermal expansion and contraction. Therefore, compared to the conventional technology, when the substrate 30 is taken out from the carrying jig 2 of the present invention, the substrate 30 does not occur. The warping phenomenon can avoid the problem of poor contact between the substrate 30 and the conductive element 310.
再者,如第3A圖所示,該蓋件21復具有用以接觸該基板30的支撐部211。具體地,該基板30對應該置放區300周圍設有切割道S,該支撐部211之位置係對應該切割道S之位置,且該支撐部211之寬度r係小於或等於該切割道S之寬度d,例如,該切割道S之寬度d係為0.2mm至0.3mm。 Furthermore, as shown in FIG. 3A, the cover member 21 further includes a support portion 211 for contacting the substrate 30. Specifically, the substrate 30 is provided with a cutting path S around the corresponding placement area 300, the position of the support portion 211 corresponds to the position of the cutting path S, and the width r of the support portion 211 is less than or equal to the cutting path S The width d of the cutting track S is, for example, 0.2 mm to 0.3 mm.
又,如第3B圖所示,於該蓋件21與該基板30間之間隔t中亦可形成有緩衝層32,該緩衝層32係為絕緣層,其材質例如為聚亞醯胺(Polyimide,簡稱PI)、聚對二唑苯(Polybenzoxazole,簡稱PBO)或其它高分子材料。 In addition, as shown in FIG. 3B, a buffer layer 32 may be formed in the interval t between the cover member 21 and the substrate 30. The buffer layer 32 is an insulating layer, and the material is, for example, polyimide (Polyimide). , Referred to as PI), polybenzoxazole (referred to as PBO) or other polymer materials.
後續,於進行熱製程(如回銲製程)時,該緩衝層32可配合該基板30之熱脹縮而變形,使該基板30能釋放熱脹縮的壓力,故當該基板30從本發明之承載治具2中取出 時,該基板30不會發生翹曲之現象。 Subsequently, during a thermal process (such as a reflow process), the buffer layer 32 can be deformed in accordance with the thermal expansion and contraction of the substrate 30, so that the substrate 30 can release the pressure of thermal expansion and contraction. Therefore, when the substrate 30 is removed from the present invention, The substrate 30 will not warp when it is taken out from the carrying jig 2.
綜上所述,本發明之電子構件置放製程及其應用之承載治具,主要藉由當基板設於承載件上時,利用蓋件與該基板之間具有間隔,以於進行熱製程時,該間隔可作為該基板之熱脹縮空間,故當該基板從承載治具中取出時,該基板不會發生翹曲之現象。 In summary, the electronic component placement process of the present invention and the application fixture thereof mainly use a gap between the cover and the substrate when the substrate is set on the carrier, so that during the thermal process, This interval can be used as the thermal expansion and contraction space of the substrate, so when the substrate is taken out from the carrying jig, the substrate will not warp.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.
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US6581278B2 (en) * | 2001-01-16 | 2003-06-24 | St Assembly Test Service Ltd. | Process and support carrier for flexible substrates |
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US8104666B1 (en) * | 2010-09-01 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal compressive bonding with separate die-attach and reflow processes |
US8373269B1 (en) * | 2011-09-08 | 2013-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Jigs with controlled spacing for bonding dies onto package substrates |
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US8809117B2 (en) * | 2011-10-11 | 2014-08-19 | Taiwain Semiconductor Manufacturing Company, Ltd. | Packaging process tools and packaging methods for semiconductor devices |
US10109612B2 (en) * | 2013-12-13 | 2018-10-23 | Taiwan Semiconductor Manufacturing Company | Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices |
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