TWI430421B - Flip-chip bonding method - Google Patents
Flip-chip bonding method Download PDFInfo
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- TWI430421B TWI430421B TW100140494A TW100140494A TWI430421B TW I430421 B TWI430421 B TW I430421B TW 100140494 A TW100140494 A TW 100140494A TW 100140494 A TW100140494 A TW 100140494A TW I430421 B TWI430421 B TW I430421B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Description
本發明係關於一種覆晶接合方法,更詳言之,本發明係為一種將晶片以覆晶方式接合至基板上之方法。The present invention relates to a flip chip bonding method, and more particularly to a method of bonding a wafer to a substrate in a flip chip manner.
現今半導體技術愈來愈成熟,製程的方式日新月異,相對的對於電子產品的尺寸之要求趨於輕薄短小,因此在晶片製造過程中之打線技術,其內部之各導電線的間距逐步縮短,造成晶片上之各銲墊(I/O pad)的間距更加接近,且因為製程技術先進,將不同功能之元件整合至同一晶片中,晶片之積集度大幅提昇,晶片上銲墊數也相對增加。傳統之晶片封裝技術為將晶片之銲墊經由銲線銲接到基板上,但如此高積集化之晶片銲墊及銲線之數量已然為能使用之空間所限,而成為製程上之瓶頸。因此,遂有不同於打線技術之覆晶技術之發展。覆晶技術大致上係於晶圓上形成複數個如銲球之凸塊,接著將切割晶圓以形成複數個晶片後再將晶片翻轉(flip)接置到基板,使凸塊能對應接合於基板之銲墊上,然後迴銲(reflow)該凸塊,以使銲球銲結至基板上之銲墊。Nowadays, semiconductor technology is becoming more and more mature, and the process of manufacturing is changing with each passing day. Relatively, the requirements for the size of electronic products tend to be light, thin and short. Therefore, in the wire manufacturing process of the wafer manufacturing process, the spacing of the internal conductive wires is gradually shortened, resulting in wafers. The spacing of the pads (I/O pads) is closer, and because of the advanced process technology, the components of different functions are integrated into the same wafer, the accumulation of the wafer is greatly increased, and the number of pads on the wafer is relatively increased. The conventional chip packaging technology is to solder the pad of the wafer to the substrate through the bonding wire. However, the number of such highly integrated wafer pads and bonding wires is limited by the space that can be used, and becomes a bottleneck in the process. Therefore, there is a development of flip chip technology that is different from wire bonding technology. The flip chip technology is generally formed on a plurality of bumps such as solder balls on a wafer, and then the wafer is diced to form a plurality of wafers, and then the wafer is flipped to the substrate, so that the bumps can be correspondingly bonded to the substrate. The bumps of the substrate are then reflowed to solder the solder balls to the pads on the substrate.
然而,在迴銲製程中,因晶片與基板的熱膨脹係數(Coefficient of thermal expansion;CTE)有差異,造成基板與晶片受熱膨脹而翹曲的程度亦不同。通常,當晶片面積較大或厚度較薄時,晶片與基板翹曲程度的差異會更加明顯,而基板越靠近邊緣之部位的翹曲程度最為明顯。However, in the reflow process, due to the difference in coefficient of thermal expansion (CTE) between the wafer and the substrate, the extent to which the substrate and the wafer are thermally expanded and warped is different. Generally, when the wafer area is large or the thickness is thin, the difference in warpage between the wafer and the substrate is more pronounced, and the degree of warpage of the substrate closer to the edge is most noticeable.
如第1圖所示,晶片10藉其底部之複數凸塊14接置於該基板12之頂面122上。迴銲製程中,晶片10與基板12因膨脹係數(CTE)不同,導致該晶片10與基板12靠近邊緣之部位會產生翹曲,造成該晶片10底部之部分凸塊14無法銲結至基板12上之銲墊,致位在該晶片10近邊緣部位之部分凸塊14形成空銲的現象,而產生銲接失敗或假銲等銲接不完全的問題,產品的不良率亦隨之增加。As shown in FIG. 1, the wafer 10 is attached to the top surface 122 of the substrate 12 by a plurality of bumps 14 at its bottom. In the reflow process, the wafer 10 and the substrate 12 are different in coefficient of expansion (CTE), which causes warpage of the portion of the wafer 10 and the substrate 12 near the edge, and the portion of the bump 14 at the bottom of the wafer 10 cannot be soldered to the substrate 12. In the upper pad, a part of the bumps 14 located at the near edge portion of the wafer 10 form an empty soldering phenomenon, which causes a problem of incomplete soldering such as soldering failure or false soldering, and the defective rate of the product also increases.
因而,如何克服上揭習知技術所有在之問題,實為一重要課題。Therefore, how to overcome all the problems in the prior art is an important issue.
為解決上述習知技術之問題,本發明遂研發出一種提升覆晶接合良率之方法。In order to solve the above problems of the prior art, the present invention has developed a method for improving the yield of flip chip bonding.
本發明之實施方法係包括:提供一其上設有晶片之基板,其中,該晶片具有相對之作用面與非作用面,該作用面上並形成有複數凸塊,以在該晶片接置於該基板上後,該複數凸塊係位於該晶片與基板之間,並藉之電性連接該晶片與基板,但部分之凸塊僅接置於晶片上,然後,將物件抵靠在晶片之非作用面上,予以施壓於該晶片,使僅接置於該晶片上之凸塊同時接觸該晶片與基板,並利用迴銲於該複數凸塊,使得該複數凸塊皆連接基板與晶片。The method of the present invention includes: providing a substrate on which a wafer is disposed, wherein the wafer has opposite working and non-active surfaces, and the working surface is formed with a plurality of bumps for being placed on the wafer After the substrate, the plurality of bumps are located between the wafer and the substrate, and electrically connected to the wafer and the substrate, but some of the bumps are only placed on the wafer, and then the object is abutted on the wafer. The non-active surface is pressed against the wafer so that the bumps placed on the wafer simultaneously contact the wafer and the substrate, and are soldered back to the plurality of bumps, so that the plurality of bumps are connected to the substrate and the wafer. .
此外,本發明另一種實施方法係包括:提供一其上設有晶片之基板,該晶片之底面係藉由複數凸塊設於該基板上,且部分之凸塊僅接置於該基板或晶片上,接著透過物件抵靠並施加壓力於該晶片頂面上,使僅接置於該基板或晶片上之凸塊同時接觸該基板及晶片,以迴銲該複數凸塊,使該複數凸塊皆連接基板與晶片。In addition, another implementation method of the present invention includes: providing a substrate on which a wafer is disposed, the bottom surface of the wafer is disposed on the substrate by a plurality of bumps, and a portion of the bumps are only placed on the substrate or the wafer. Then, the object is abutted against the top surface of the wafer, and the bumps only on the substrate or the wafer are simultaneously contacted with the substrate and the wafer to reflow the plurality of bumps to make the plurality of bumps. Both the substrate and the wafer are connected.
由上可知,本發明將該物件抵靠晶片頂面,以施加壓力,避免該晶片因面積較大或厚度較薄時,在迴銲製程中產生翹曲,使得晶片周圍之凸塊發生空銲的情況。而該晶片之翹曲部分於透過該物件給予壓力,使得翹曲部分趨於平整,藉由該凸塊與晶片及基板相互連觸,再做迴銲處理,以解決凸塊空銲之現象。As can be seen from the above, the object of the present invention is pressed against the top surface of the wafer to apply pressure to prevent the wafer from being warped in the reflow process due to the large area or thinner thickness, so that the bumps around the wafer are randomly welded. Case. The warped portion of the wafer is pressurized by the object, so that the warped portion tends to be flat, and the bump and the wafer and the substrate are in contact with each other, and then reflowed to solve the phenomenon of bump soldering.
因此,本發明之覆晶接合良率之方法,不僅能應用於輕薄或大尺寸之晶圓,並提高覆晶接合良率。Therefore, the method of the flip chip bonding yield of the present invention can be applied not only to a thin or large-sized wafer but also to improving the flip chip bonding yield.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“底”、“二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "bottom", "two" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments to a relationship are considered to be within the scope of the invention, without departing from the scope of the invention.
以下即配合第2A至2D圖詳細說明本發明第一實施例之覆晶接合方法。Hereinafter, the flip chip bonding method of the first embodiment of the present invention will be described in detail with reference to Figs. 2A to 2D.
如第2A圖所示,將一晶片10接置於一基板12上,而該基板12係為半導體晶片、印刷電路板或具有矽穿孔之基板,但不以此為限。另外,該晶片10之底面(於本實施例之作用面)102形成有複數銲錫凸塊(solder bump)14,並藉該凸塊14設於基板12上。該凸塊14係經由一次迴銲過程使之連接於該基板12,因初次迴銲時會產生熱源H,且該晶片10與基板12之熱膨脹係數不同,是故,該晶片10與基板12之邊緣均會翹曲,導致該晶片10底面(於本實施例之作用面)102上的部份凸塊14仍僅接置於晶片10上,未接置到基板12上。As shown in FIG. 2A, a wafer 10 is placed on a substrate 12, which is a semiconductor wafer, a printed circuit board or a substrate having a perforated hole, but is not limited thereto. In addition, a bottom surface of the wafer 10 (the active surface of the embodiment) 102 is formed with a plurality of solder bumps 14 , and the bumps 14 are disposed on the substrate 12 . The bump 14 is connected to the substrate 12 through a reflow process. Since the heat source H is generated during the initial reflow, and the thermal expansion coefficient of the wafer 10 and the substrate 12 is different, the wafer 10 and the substrate 12 are The edges are all warped, so that the partial bumps 14 on the bottom surface (the active surface of the embodiment) 102 of the wafer 10 are still only placed on the wafer 10 and are not attached to the substrate 12.
第2A圖所示之態樣中,該凸塊14係預先形成於該晶片10上。但於第2A’圖所示之另一態樣中,該凸塊14係預先形成於該基板12’上,則於初次迴銲時,部分之該凸塊14僅接置於該基板12’上,而未接置到晶片10’上。本實施例為便於說明,以下係接續第2A圖介紹本發明之方法。In the aspect shown in FIG. 2A, the bump 14 is formed on the wafer 10 in advance. However, in another aspect shown in FIG. 2A', the bump 14 is pre-formed on the substrate 12'. When the first reflow is performed, part of the bump 14 is only placed on the substrate 12'. Up, but not attached to the wafer 10'. In the present embodiment, for convenience of explanation, the method of the present invention will be described below in connection with FIG. 2A.
如第2B及2C圖所示,透過一物件16抵靠至該晶片10之頂面(於本實施例之非作用面)104,以施加壓力於該晶片10頂面(於本實施例之非作用面),使僅接置於該晶片10(或基板12’)上之凸塊14因受壓而同時接觸該基板12及晶片10,繼而二次迴銲該複數凸塊14。在此二次迴銲過程中,該晶片10均勻受物件16抵靠之壓力而抑制翹曲之狀態,使晶片10與基板12之平面度趨於一致,故經此二次迴銲,該凸塊14得能同時銲接至該基板12及晶片10。該物件16係為撓性體,例如矽膠體或容納有液體或複數顆粒之囊袋,但不以此為限。製成該物件16之材料皆為耐熱型導熱材料,如耐熱型導熱矽膠或裝有耐熱液體或沙粒之囊袋,以抗受回銲時之高溫。As shown in FIGS. 2B and 2C, an object 16 is abutted against the top surface of the wafer 10 (in the non-active surface of the embodiment) 104 to apply pressure to the top surface of the wafer 10 (in this embodiment). The active surface) causes the bumps 14 placed only on the wafer 10 (or the substrate 12') to simultaneously contact the substrate 12 and the wafer 10 by being pressed, and then re-weld the plurality of bumps 14 twice. During the second reflow process, the wafer 10 is uniformly subjected to the pressure of the object 16 to suppress the warpage, so that the flatness of the wafer 10 and the substrate 12 tends to be uniform, so that the second reflow is performed. Block 14 is capable of being soldered to both substrate 12 and wafer 10. The article 16 is a flexible body, such as a silicone or a bag containing a liquid or a plurality of particles, but is not limited thereto. The material of the article 16 is made of a heat-resistant heat-conductive material such as a heat-resistant heat-conductive silicone rubber or a bladder containing heat-resistant liquid or sand to resist the high temperature during reflow.
同樣地,如第2B’圖所示,若該凸塊14係預先形成於基板12’上,亦可透過該物件16抵靠至該晶片10’之頂面(於本實施例之非作用面)104’,以施加壓力於該晶片10’頂面(於本實施例之非作用面)104’上,使僅接置於該基板12’上之凸塊14同時接觸晶片10’底面(於本實施例之作用面)102’,並以迴銲該複數凸塊14。Similarly, as shown in FIG. 2B', if the bump 14 is formed on the substrate 12' in advance, the object 16 can also pass through the top surface of the wafer 10' (in the non-active surface of the embodiment). 104', to apply pressure on the top surface of the wafer 10' (on the non-active surface of the embodiment) 104', so that only the bumps 14 placed on the substrate 12' simultaneously contact the bottom surface of the wafer 10' (in The active surface of the embodiment is 102', and the plurality of bumps 14 are reflowed.
此外,該凸塊14具有剛性結構,如導電銅柱,可避免在迴銲製程中相鄰凸塊14因過度擠壓變形而造成橋接,所以,該凸塊14之剛性結構使覆晶接合之方法於二次迴銲製程後,該晶片10與基板12之間的距離均相同;並藉由該凸塊14,使晶片10及基板12相互接合。In addition, the bump 14 has a rigid structure, such as a conductive copper pillar, to avoid bridging of the adjacent bump 14 due to excessive extrusion deformation during the reflow process, so the rigid structure of the bump 14 enables flip-chip bonding. After the second reflow process, the distance between the wafer 10 and the substrate 12 is the same; and the bumps 14 are used to bond the wafer 10 and the substrate 12 to each other.
此外,如第2D圖所示,本發明之方法復可包括於抵靠該物件16之前,於該晶片10設置區域外之基板12上設置隔熱材18,以防止基板12受熱。In addition, as shown in FIG. 2D, the method of the present invention may include providing a heat insulating material 18 on the substrate 12 outside the installation area of the wafer 10 to prevent the substrate 12 from being heated before the object 16 is placed against the object 16.
或者,該晶片10與物件16之間設有隔離片19,以防止該晶片10遭受物件16污染,影響製程良率。Alternatively, a spacer 19 is disposed between the wafer 10 and the object 16 to prevent the wafer 10 from being contaminated by the object 16 and affecting the process yield.
請參閱第3A至3D圖,係本發明第二實施例之覆晶接合方法示意圖。本實施例與第一實施例的差異僅在於透過該物件16抵靠至該晶片10之頂面(於本實施例之非作用面)104,以施加壓力於該晶片10的步驟復包括於該物件16上施加增重件162,其重量係以大於該物件16之重量為準則,於輕薄、大尺寸面積,更為適用。該增重件162也可以是一提供穩定壓力之機械構造,以於迴銲過程中,穩定提供一定壓力使因熱膨脹產生之翹曲得到抑制。Please refer to FIGS. 3A to 3D, which are schematic views of a flip chip bonding method according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment is only that the object 16 is abutted against the top surface of the wafer 10 (in the non-active surface of the embodiment) 104, and the step of applying pressure to the wafer 10 is included in the step. The weighting member 162 is applied to the object 16 and its weight is greater than the weight of the object 16, which is more suitable for light and thin, large size area. The weight member 162 can also be a mechanical structure that provides a stable pressure to stably provide a certain pressure during the reflow process to suppress warpage caused by thermal expansion.
因初次迴銲製程所造成之翹曲,可以該增重件162使晶片10平面度與基板12更為一致,再藉由二次迴銲製程使該晶片10之凸塊14與基板12相互完全接合。Due to the warpage caused by the initial reflow process, the weight of the wafer 10 can be made more uniform with the substrate 12, and the bumps 14 and 12 of the wafer 10 can be completely replaced by the secondary reflow process. Engage.
如第3A圖所示,該晶片10經過初次迴銲製程,因該晶片10與基板12的熱膨脹係數不同,導致該晶片10與基板12邊緣均產生翹曲。As shown in FIG. 3A, the wafer 10 undergoes a primary reflow process because the thermal expansion coefficients of the wafer 10 and the substrate 12 are different, resulting in warpage of both the wafer 10 and the edge of the substrate 12.
如第3B圖所示,於該晶片10上設置物件16,且物件16上設有增重件162,且該增重件162之重量係大於物體16之重量。As shown in FIG. 3B, the object 16 is disposed on the wafer 10, and the weight 16 is disposed on the object 16, and the weight of the weight 162 is greater than the weight of the object 16.
如第3C圖所示,於二次迴銲製程使該晶片10之凸塊14與基板12相互完全固接,並且該晶片10之頂面(於本實施例之非作用面)104均勻受壓,使該晶片10之平面度與基板12平面度趨於一致。As shown in FIG. 3C, the bump 14 of the wafer 10 and the substrate 12 are completely fixed to each other in the secondary reflow process, and the top surface of the wafer 10 (in the non-active surface of the embodiment) 104 is uniformly pressed. The flatness of the wafer 10 is made to coincide with the flatness of the substrate 12.
如第3D圖所示,該晶片10設置區域外之基板12上亦可設置隔熱材18,以防止基板12受熱。另外,該晶片10頂面(於本實施例之非作用面)104亦可設有隔離片19,以防止該晶片10遭受物件16污染。As shown in FIG. 3D, a heat insulating material 18 may be disposed on the substrate 12 outside the installation area of the wafer 10 to prevent the substrate 12 from being heated. In addition, the top surface of the wafer 10 (in the non-active surface of the embodiment) 104 may also be provided with a spacer 19 to prevent the wafer 10 from being contaminated by the object 16.
由上可知,本發明之覆晶接合方法應用於半導體封裝技術中,將該物件16抵靠晶片10頂面(於本實施例之非作用面)104至該晶片10之頂面(於本實施例之非作用面)104,以施加壓力,校正該晶片10因面積較大或厚度較薄時,因迴銲製程所造成之翹曲問題,而該晶片10之翹曲部分,係透過該物件16給予的壓力,使得翹曲部分趨於平整,藉由該凸塊14與晶片10及基板12相互連接,以防止該凸塊14無法與晶片10及基板12完全相互連接,造成空銲現象。As can be seen from the above, the flip chip bonding method of the present invention is applied to a semiconductor package technology, and the object 16 is placed against the top surface of the wafer 10 (in the non-active surface of the embodiment) 104 to the top surface of the wafer 10 (in this embodiment) The non-active surface 104 of the example, by applying pressure, corrects the warpage caused by the reflow process when the wafer 10 is large or thin, and the warped portion of the wafer 10 passes through the object. The pressure applied by 16 causes the warped portion to be flat, and the bump 14 is connected to the wafer 10 and the substrate 12 to prevent the bump 14 from being completely connected to the wafer 10 and the substrate 12, thereby causing an empty soldering phenomenon.
本發明之概念,並不只限於上述之實施例之晶片與基板之接合,於相同發明概念下,更可應用於晶圓與晶圓之接合,晶圓與矽通孔(Through silicon via;TSV)晶圓之接合及其他因熱膨脹係數不同產生之翹曲而造成產品可靠度不佳之應用。The concept of the present invention is not limited to the bonding of the wafer and the substrate in the above embodiments. Under the same inventive concept, the wafer and the wafer are bonded to each other. The wafer and the through silicon via (TSV) are used. Wafer bonding and other applications where the reliability of the product is poor due to warpage caused by different thermal expansion coefficients.
上述該些實施樣態僅例示性說明本發明之功效,而非用於限制本發明,任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述該些實施態樣進行修飾與改變。此外,在上述該些實施態樣中之元件的數量僅為例示性說明,亦非用於限制本發明。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and those skilled in the art can practice the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10、10’...晶片10, 10’. . . Wafer
102、102’...底面102, 102’. . . Bottom
104、104’、122...頂面104, 104', 122. . . Top surface
12、12’...基板12, 12’. . . Substrate
14...凸塊14. . . Bump
16...物件16. . . object
162...增重件162. . . Weight gain
18...隔熱材18. . . Insulation material
19...隔離片19. . . Isolation piece
H...熱源H. . . Heat source
第1圖係用以說明覆晶製程中發生空銲之示意圖;Figure 1 is a schematic view for explaining the occurrence of void welding in the flip chip process;
第2A至2D圖係為本發明第一實施例之覆晶接合方法示意圖,其中,第2A’圖係於基板上預先形成有凸塊之示意圖,第2B’圖係顯示部分之凸塊僅接置於該基板上之示意圖;以及2A to 2D are schematic views showing a flip chip bonding method according to a first embodiment of the present invention, wherein the 2A' pattern is a schematic view in which bumps are formed in advance on the substrate, and the bumps of the 2B' pattern display portion are only connected. a schematic view placed on the substrate;
第3A至3D圖係為本發明第二實施例之覆晶接合方法示意圖。3A to 3D are schematic views showing a flip chip bonding method according to a second embodiment of the present invention.
10...晶片10. . . Wafer
102...底面102. . . Bottom
104...頂面104. . . Top surface
12...基板12. . . Substrate
14...凸塊14. . . Bump
16...物件16. . . object
18...隔熱材18. . . Insulation material
19...隔離片19. . . Isolation piece
H...熱源H. . . Heat source
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