TW201320278A - Flip-chip bonding method - Google Patents

Abstract

Disclosed is a novel flip-chip bonding method, comprising mounting a chip on a substrate in a flip-chip manner by means of a plurality of bumps, disposing parts of the bumps merely on the substrate or the chips; and using an object for abutting against and exerting pressure on the chip, such that the bumps that are disposed merely on the substrate or the chip are in contact with the substrate and the chip at the same time; reflowing the bumps in order to connect to both the substrate and the chip, thus increasing good yield of bonding.

Description

Flip chip bonding method

The present invention relates to a flip chip bonding method, and more particularly to a method of bonding a wafer to a substrate in a flip chip manner.

Nowadays, semiconductor technology is becoming more and more mature, and the process of manufacturing is changing with each passing day. Relatively, the requirements for the size of electronic products tend to be light, thin and short. Therefore, in the wire manufacturing process of the wafer manufacturing process, the spacing of the internal conductive wires is gradually shortened, resulting in wafers. The spacing of the pads (I/O pads) is closer, and because of the advanced process technology, the components of different functions are integrated into the same wafer, the accumulation of the wafer is greatly increased, and the number of pads on the wafer is relatively increased. The conventional chip packaging technology is to solder the pad of the wafer to the substrate through the bonding wire. However, the number of such highly integrated wafer pads and bonding wires is limited by the space that can be used, and becomes a bottleneck in the process. Therefore, there is a development of flip chip technology that is different from wire bonding technology. The flip chip technology is generally formed on a plurality of bumps such as solder balls on a wafer, and then the wafer is diced to form a plurality of wafers, and then the wafer is flipped to the substrate, so that the bumps can be correspondingly bonded to the substrate. The bumps of the substrate are then reflowed to solder the solder balls to the pads on the substrate.

However, in the reflow process, due to the difference in coefficient of thermal expansion (CTE) between the wafer and the substrate, the extent to which the substrate and the wafer are thermally expanded and warped is different. Generally, when the wafer area is large or the thickness is thin, the difference in warpage between the wafer and the substrate is more pronounced, and the degree of warpage of the substrate closer to the edge is most noticeable.

As shown in FIG. 1, the wafer 10 is attached to the top surface 122 of the substrate 12 by a plurality of bumps 14 at its bottom. In the reflow process, the wafer 10 and the substrate 12 are different in coefficient of expansion (CTE), which causes warpage of the portion of the wafer 10 and the substrate 12 near the edge, and the portion of the bump 14 at the bottom of the wafer 10 cannot be soldered to the substrate 12. In the upper pad, a part of the bumps 14 located at the near edge portion of the wafer 10 form an empty soldering phenomenon, which causes a problem of incomplete soldering such as soldering failure or false soldering, and the defective rate of the product also increases.

Therefore, how to overcome all the problems in the prior art is an important issue.

In order to solve the above problems of the prior art, the present invention has developed a method for improving the yield of flip chip bonding.

The method of the present invention includes: providing a substrate on which a wafer is disposed, wherein the wafer has opposite working and non-active surfaces, and the working surface is formed with a plurality of bumps for being placed on the wafer After the substrate, the plurality of bumps are located between the wafer and the substrate, and electrically connected to the wafer and the substrate, but some of the bumps are only placed on the wafer, and then the object is abutted on the wafer. The non-active surface is pressed against the wafer so that the bumps placed on the wafer simultaneously contact the wafer and the substrate, and are soldered back to the plurality of bumps, so that the plurality of bumps are connected to the substrate and the wafer. .

In addition, another implementation method of the present invention includes: providing a substrate on which a wafer is disposed, the bottom surface of the wafer is disposed on the substrate by a plurality of bumps, and a portion of the bumps are only placed on the substrate or the wafer. Then, the object is abutted against the top surface of the wafer, and the bumps only on the substrate or the wafer are simultaneously contacted with the substrate and the wafer to reflow the plurality of bumps to make the plurality of bumps. Both the substrate and the wafer are connected.

As can be seen from the above, the object of the present invention is pressed against the top surface of the wafer to apply pressure to prevent the wafer from being warped in the reflow process due to the large area or thinner thickness, so that the bumps around the wafer are randomly welded. Case. The warped portion of the wafer is pressurized by the object, so that the warped portion tends to be flat, and the bump and the wafer and the substrate are in contact with each other, and then reflowed to solve the phenomenon of bump soldering.

Therefore, the method of the flip chip bonding yield of the present invention can be applied not only to a thin or large-sized wafer but also to improving the flip chip bonding yield.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "bottom", "two" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments to a relationship are considered to be within the scope of the invention, without departing from the scope of the invention.

First embodiment

Hereinafter, the flip chip bonding method of the first embodiment of the present invention will be described in detail with reference to Figs. 2A to 2D.

As shown in FIG. 2A, a wafer 10 is placed on a substrate 12, which is a semiconductor wafer, a printed circuit board or a substrate having a perforated hole, but is not limited thereto. In addition, a bottom surface of the wafer 10 (the active surface of the embodiment) 102 is formed with a plurality of solder bumps 14 , and the bumps 14 are disposed on the substrate 12 . The bump 14 is connected to the substrate 12 through a reflow process. Since the heat source H is generated during the initial reflow, and the thermal expansion coefficient of the wafer 10 and the substrate 12 is different, the wafer 10 and the substrate 12 are The edges are all warped, so that the partial bumps 14 on the bottom surface (the active surface of the embodiment) 102 of the wafer 10 are still only placed on the wafer 10 and are not attached to the substrate 12.

In the aspect shown in FIG. 2A, the bump 14 is formed on the wafer 10 in advance. However, in another aspect shown in FIG. 2A', the bump 14 is pre-formed on the substrate 12'. When the first reflow is performed, part of the bump 14 is only placed on the substrate 12'. Up, but not attached to the wafer 10'. In the present embodiment, for convenience of explanation, the method of the present invention will be described below in connection with FIG. 2A.

As shown in FIGS. 2B and 2C, an object 16 is abutted against the top surface of the wafer 10 (in the non-active surface of the embodiment) 104 to apply pressure to the top surface of the wafer 10 (in this embodiment). The active surface) causes the bumps 14 placed only on the wafer 10 (or the substrate 12') to simultaneously contact the substrate 12 and the wafer 10 by being pressed, and then re-weld the plurality of bumps 14 twice. During the second reflow process, the wafer 10 is uniformly subjected to the pressure of the object 16 to suppress the warpage, so that the flatness of the wafer 10 and the substrate 12 tends to be uniform, so that the second reflow is performed. Block 14 is capable of being soldered to both substrate 12 and wafer 10. The article 16 is a flexible body, such as a silicone or a bag containing a liquid or a plurality of particles, but is not limited thereto. The material of the article 16 is made of a heat-resistant heat-conductive material such as a heat-resistant heat-conductive silicone rubber or a bladder containing heat-resistant liquid or sand to resist the high temperature during reflow.

Similarly, as shown in FIG. 2B', if the bump 14 is formed on the substrate 12' in advance, the object 16 can also pass through the top surface of the wafer 10' (in the non-active surface of the embodiment). 104', to apply pressure on the top surface of the wafer 10' (on the non-active surface of the embodiment) 104', so that only the bumps 14 placed on the substrate 12' simultaneously contact the bottom surface of the wafer 10' (in The active surface of the embodiment is 102', and the plurality of bumps 14 are reflowed.

In addition, the bump 14 has a rigid structure, such as a conductive copper pillar, to avoid bridging of the adjacent bump 14 due to excessive extrusion deformation during the reflow process, so the rigid structure of the bump 14 enables flip-chip bonding. After the second reflow process, the distance between the wafer 10 and the substrate 12 is the same; and the bumps 14 are used to bond the wafer 10 and the substrate 12 to each other.

In addition, as shown in FIG. 2D, the method of the present invention may include providing a heat insulating material 18 on the substrate 12 outside the installation area of the wafer 10 to prevent the substrate 12 from being heated before the object 16 is placed against the object 16.

Alternatively, a spacer 19 is disposed between the wafer 10 and the object 16 to prevent the wafer 10 from being contaminated by the object 16 and affecting the process yield.

Second embodiment

Please refer to FIGS. 3A to 3D, which are schematic views of a flip chip bonding method according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment is only that the object 16 is abutted against the top surface of the wafer 10 (in the non-active surface of the embodiment) 104, and the step of applying pressure to the wafer 10 is included in the step. The weighting member 162 is applied to the object 16 and its weight is greater than the weight of the object 16, which is more suitable for light and thin, large size area. The weight member 162 can also be a mechanical structure that provides a stable pressure to stably provide a certain pressure during the reflow process to suppress warpage caused by thermal expansion.

Due to the warpage caused by the initial reflow process, the weight of the wafer 10 can be made more uniform with the substrate 12, and the bumps 14 and 12 of the wafer 10 can be completely replaced by the secondary reflow process. Engage.

As shown in FIG. 3A, the wafer 10 undergoes a primary reflow process because the thermal expansion coefficients of the wafer 10 and the substrate 12 are different, resulting in warpage of both the wafer 10 and the edge of the substrate 12.

As shown in FIG. 3B, the object 16 is disposed on the wafer 10, and the weight 16 is disposed on the object 16, and the weight of the weight 162 is greater than the weight of the object 16.

As shown in FIG. 3C, the bump 14 of the wafer 10 and the substrate 12 are completely fixed to each other in the secondary reflow process, and the top surface of the wafer 10 (in the non-active surface of the embodiment) 104 is uniformly pressed. The flatness of the wafer 10 is made to coincide with the flatness of the substrate 12.

As shown in FIG. 3D, a heat insulating material 18 may be disposed on the substrate 12 outside the installation area of the wafer 10 to prevent the substrate 12 from being heated. In addition, the top surface of the wafer 10 (in the non-active surface of the embodiment) 104 may also be provided with a spacer 19 to prevent the wafer 10 from being contaminated by the object 16.

As can be seen from the above, the flip chip bonding method of the present invention is applied to a semiconductor package technology, and the object 16 is placed against the top surface of the wafer 10 (in the non-active surface of the embodiment) 104 to the top surface of the wafer 10 (in this embodiment) The non-active surface 104 of the example, by applying pressure, corrects the warpage caused by the reflow process when the wafer 10 is large or thin, and the warped portion of the wafer 10 passes through the object. The pressure applied by 16 causes the warped portion to be flat, and the bump 14 is connected to the wafer 10 and the substrate 12 to prevent the bump 14 from being completely connected to the wafer 10 and the substrate 12, thereby causing an empty soldering phenomenon.

The concept of the present invention is not limited to the bonding of the wafer and the substrate in the above embodiments. Under the same inventive concept, the wafer and the wafer are bonded to each other. The wafer and the through silicon via (TSV) are used. Wafer bonding and other applications where the reliability of the product is poor due to warpage caused by different thermal expansion coefficients.

The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and those skilled in the art can practice the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10, 10’. . . Wafer

102, 102’. . . Bottom

104, 104', 122. . . Top surface

12, 12’. . . Substrate

14. . . Bump

16. . . object

162. . . Weight gain

18. . . Insulation material

19. . . Isolation piece

H. . . Heat source

Figure 1 is a schematic view for explaining the occurrence of void welding in the flip chip process;

2A to 2D are schematic views showing a flip chip bonding method according to a first embodiment of the present invention, wherein the 2A' pattern is a schematic view in which bumps are formed in advance on the substrate, and the bumps of the 2B' pattern display portion are only connected. a schematic view placed on the substrate;

3A to 3D are schematic views showing a flip chip bonding method according to a second embodiment of the present invention.

10. . . Wafer

102. . . Bottom

104. . . Top surface

12. . . Substrate

14. . . Bump

16. . . object

18. . . Insulation material

19. . . Isolation piece

H. . . Heat source

Claims (10)

A flip chip bonding method comprising: providing a substrate on which a wafer is disposed, wherein the wafer has opposite working and non-active surfaces, and the working surface is formed with a plurality of bumps for being placed on the wafer After the substrate is mounted, the plurality of bumps are located between the wafer and the substrate, and electrically connected to the wafer and the substrate, and a portion of the bumps are only placed on the wafer; and an object is abutted to the wafer. An inactive surface for applying pressure to the wafer such that bumps only placed on the wafer simultaneously contact the substrate and the wafer; and reflowing the plurality of bumps. A flip chip bonding method includes: providing a substrate on which a wafer is disposed, wherein the wafer is disposed on the substrate by a plurality of bumps, and a portion of the bumps are only disposed on the substrate; and The object abuts and applies pressure to the top surface of the wafer such that the bumps only on the substrate simultaneously contact the substrate and the wafer to reflow the plurality of bumps. The method of claim 1 or 2, further comprising providing a heat insulating material on the substrate outside the wafer receiving area before the object is placed against the object. The method of claim 1 or 2, wherein a spacer is disposed between the wafer and the article. The method of claim 1 or 2, wherein the substrate is a semiconductor wafer, a printed circuit board or a substrate having a perforated hole. The method of claim 1 or 2, wherein the article is a flexible body. The method of claim 1 or 2, wherein the article is a colloidal gel or a pouch containing a liquid or a plurality of particles. The method of claim 1 or 2, wherein the step of abutting and applying pressure to the wafer through the object comprises applying a weighting member to the object, the weight of which is greater than the weight of the object. . The method of claim 1 or 2, wherein the bumps comprise a rigid structure. The method of claim 1 or 2, wherein the wafer and the substrate have different coefficients of thermal expansion.