CN103094139A - Flip chip bonding method - Google Patents
Flip chip bonding method Download PDFInfo
- Publication number
- CN103094139A CN103094139A CN2012101073693A CN201210107369A CN103094139A CN 103094139 A CN103094139 A CN 103094139A CN 2012101073693 A CN2012101073693 A CN 2012101073693A CN 201210107369 A CN201210107369 A CN 201210107369A CN 103094139 A CN103094139 A CN 103094139A
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- CN
- China
- Prior art keywords
- chip
- substrate
- projection
- acting surface
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 79
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000012774 insulation material Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 239000008119 colloidal silica Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 238000003466 welding Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
A flip chip bonding method is to place a chip on a substrate by flip chip mode through multiple bumps, make part of the bumps only place on the substrate or chip, and then use an object to lean against and apply pressure to the chip, so that the part of the bumps only place on the substrate or chip contact the substrate and chip at the same time, then reflow the multiple bumps, make the multiple bumps all connect the substrate and chip, in order to improve the flip chip bonding yield.
Description
Technical field
The present invention relates to a kind of chip bonding method, in more detail, the present invention a kind ofly is engaged to method on substrate with chip to cover crystal type.
Background technology
Semiconductor technology is more and more ripe now, the mode of technique is maked rapid progress, the requirement of relative size for electronic product is tending towards compact, so the routing technology in chip manufacturing proces, the spacing of each conductor wire of its inside progressively shortens, and causes the spacing of each weld pad (I/Opad) on chip more approaching, and because technology is advanced, the assembly of difference in functionality is integrated in same chip, and the integration of chip significantly promotes, and on chip, the weld pad number also increases relatively.Traditional chip encapsulation technology is for being welded to the weld pad of chip on substrate via bonding wire, but so the quantity of the chip pad of high integration and the bonding wire space that causes already using is limit, and becomes technologic bottleneck.Therefore, the development of the Flip Chip that is different from the routing technology is arranged then.Flip Chip is to form a plurality of projections as soldered ball on wafer haply, then cutting crystal wafer is put substrate to form chip upset (flip) to be connect after a plurality of chips again, projection can corresponding be engaged on the weld pad of substrate, then this projection of reflow (reflow) is so that the weld pad to the substrate is tied in soldered ball weldering.
Yet, in reflow process, because of thermal coefficient of expansion (the Coefficient of thermal expansion of chip and substrate; CTE) variant, the degree of warpage is also different from the chip expanded by heating to cause substrate.Usually, during large or thinner thickness, the difference of chip and substrate warp degree can be more obvious when chip area, and substrate is the most obvious the closer to the warpage degree at the position at edge.
As shown in Figure 1, chip 10 connects on the end face 122 that is placed in this substrate 12 by a plurality of projections 14 of its bottom.In reflow process, chip 10 is different because of the coefficient of expansion (CTE) from substrate 12, cause this chip 10 and substrate 12 submarginal position can produce warpage, cause the part projection 14 of this chip 10 bottoms to weld to tie the weld pad to the substrate 12, cause the phenomenons that the part projection 14 of position at this chip 10 proximal edge positions forms empty weldering, and producing the incomplete problems of welding such as welding failure or dry joint, the fraction defective of product also increases thereupon.
Thereby, how to overcome above-mentioned prior art all problem, be in fact an important topic.
Summary of the invention
For solving the problem of above-mentioned prior art, the present invention develops a kind of method that promotes the chip bonding yield then.
implementation method of the present invention comprises: a substrate which is provided with chip is provided, wherein, this chip has relative acting surface and non-acting surface, on this acting surface and be formed with a plurality of projections, with connect at this chip be placed on this substrate after, described a plurality of projection is between this chip and substrate, and by being electrically connected this chip and substrate, but the projection of part only connects and is placed on chip, then, object is resisted against on the non-acting surface of chip, applied pressure to this chip, make and only connect the projection that is placed on this chip and contact simultaneously this chip and substrate, and utilize reflow in described a plurality of projections, make described a plurality of projection all connection substrate and chip.
In addition, the another kind of implementation method of the present invention comprises: a substrate which is provided with chip is provided, a plurality of projections of the underrun of this chip are located on this substrate, and the projection of part only connects and is placed on this substrate or chip, then by object against and bring pressure to bear on this chip end face, make only to connect the projection that is placed on this substrate or chip and contact simultaneously this substrate and chip, with the described a plurality of projections of reflow, make described a plurality of projection all connection substrate and chip.
As from the foregoing, the present invention against the chip end face, to exert pressure, avoids this chip during large or thinner thickness, to produce warpage because of area in reflow process this object, makes projection around chip that the situation of empty weldering occur.And the warpage of this chip part makes warpage partly be tending towards smooth in give pressure by this object, interconnects mutually by this projection and chip and substrate tactile, then does reflow and process, to solve the phenomenon of the empty weldering of projection.
Therefore, the method for chip bonding yield of the present invention can not only be applied to frivolous or large-sized wafer, and improves the chip bonding yield.
Description of drawings
Fig. 1 covers the schematic diagram that empty weldering occurs in brilliant technique in order to explanation;
Fig. 2 A to 2D is the chip bonding method schematic diagram of first embodiment of the invention, and wherein, Fig. 2 A ' is the schematic diagram that is pre-formed projection on substrate, and the projection of Fig. 2 B ' display part only connects the schematic diagram that is placed on this substrate; And
Fig. 3 A to 3D is the chip bonding method schematic diagram of second embodiment of the invention.
The primary clustering symbol description
10,10 ' chip
102,102 ' bottom surface
104,104 ', 122 end faces
12,12 ' substrate
14 projections
140 rigid structures
16 objects
162 weightening finish parts
18 heat insulation materials
19 spacers
The H thermal source.
Embodiment
Below by particular specific embodiment, embodiments of the present invention are described, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, the appended graphic structure that illustrates of this specification, ratio, size etc., equal contents in order to coordinate specification to disclose only, understanding and reading for those skilled in the art, be not to limit the enforceable qualifications of the present invention, therefore the technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under the effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents and get in the scope that can contain.Simultaneously, quote in this specification as " on ", " end ", " two " reach terms such as " one ", also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when also being considered as the enforceable category of the present invention.
The first embodiment
Below namely coordinate Fig. 2 A to 2D to describe the chip bonding method of first embodiment of the invention in detail.
As shown in Fig. 2 A, a chip 10 is connect be placed on a substrate 12, and this substrate 12 is for semiconductor chip, printed circuit board (PCB) or have the substrate of silicon perforation, but not as limit.In addition, the bottom surface of this chip 10 (in the acting surface of the present embodiment) 102 is formed with many solder bumps (solder bump) 14, and is located on substrate 12 by this projection 14.This projection 14 makes it to be connected in this substrate 12 via a reflow process, can produce heat source H during because of first reflow, and this chip 10 is different from the thermal coefficient of expansion of substrate 12, therefore, the edge of this chip 10 and substrate 12 all can warpage, cause part projection 14 on these chip 10 bottom surfaces (in the acting surface of the present embodiment) 102 still only to connect and be placed on chip 10, do not connect and put on substrate 12.
In execution mode shown in Fig. 2 A, this projection 14 is pre-formed on this chip 10.But in another execution mode shown in Fig. 2 A ', this projection 14 is pre-formed on this substrate 12 ', and when first reflow, this projection 14 of part only connects and is placed on this substrate 12 ', does not put on chip 10 ' and connect.The present embodiment is for ease of explanation, and following hookup 2A introduces method of the present invention.
As shown in Fig. 2 B and 2C, by an object 16 against the end face (in the non-acting surface of the present embodiment) 104 to this chip 10, to bring pressure to bear on these chip 10 end faces (in the non-acting surface of the present embodiment), make only to connect the projection 14 that is placed on this chip 10 (or substrate 12 ') and contact simultaneously this substrate 12 and chip 10 because of pressurized, then the described a plurality of projections 14 of secondary reflow.In this secondary reflow process, this chip 10 evenly be subjected to object 16 against pressure and suppress the state of warpage, chip 10 and the flatness of substrate 12 are reached unanimity, thus through this secondary reflow, this projection 14 can be soldered to simultaneously this substrate 12 and chip 10.This object 16 is flexible body, colloidal silica or accommodate liquid or granose pouch for example, but not as limit.The material of making this object 16 is all the heat resistant type Heat Conduction Material, as the heat resistant type heat conductive silica gel or the pouch of heat-resisting liquid or the grains of sand is housed, with anti-high temperature when being subjected to reflow.
Similarly, as shown in Fig. 2 B ', if this projection 14 is pre-formed on substrate 12 ', also can be by this object 16 against the end face (in the non-acting surface of the present embodiment) 104 ' to this chip 10 ', to bring pressure to bear on this chip 10 ' end face (in the non-acting surface of the present embodiment) 104 ', make only to connect the projection 14 while contact chip 10 ' bottom surfaces (in the acting surface of the present embodiment) 102 ' that are placed on this substrate 12 ', and with the described a plurality of projections 14 of reflow.
In addition, this projection 14 has rigid structure 140, as conduction copper column, can avoid in reflow process adjacent projections 14 to cause bridge joint because of the excessive compression distortion, so, the rigid structure 140 of this projection 14 makes the method for chip bonding after the secondary returning Welding, and this chip 10 is all identical with distance between substrate 12; And by this projection 14, chip 10 and substrate 12 are bonded with each other.
In addition, as shown in Fig. 2 D, method of the present invention also can be included in before this object 16, on the substrate 12 outside this chip 10 setting areas, heat insulation material 18 is set, and is heated to prevent substrate 12.
Perhaps, be provided with spacer 19 between this chip 10 and object 16, polluted by object 16 to prevent this chip 10, affect the technique yield.
The second embodiment
Seeing also Fig. 3 A to 3D, is the chip bonding method schematic diagram of second embodiment of the invention.The difference of the present embodiment and the first embodiment only is by this object 16 against the end face (in the non-acting surface of the present embodiment) 104 to this chip 10, also be included in the step that brings pressure to bear on this chip 10 and apply weightening finish part 162 on this object 16, its weight take greater than the weight of this object 16 as criterion, in frivolous, large scale area, more applicable.This weightening finish part 162 can be also one to provide the mechanical realization of steady pressure, and with in reflow process, the stable warpage that provides certain pressure to make and produce because of thermal expansion is inhibited.
Warpage because first reflow process causes can make chip 10 flatnesses more consistent with substrate 12 by this weightening finish part 162, then the projection 14 of this chip 10 is engaged mutually fully with substrate 12.
As shown in Figure 3A, this chip 10 is through first reflow process, and is different from the thermal coefficient of expansion of substrate 12 because of this chip 10, causes this chip 10 and substrate 12 edges all to produce warpage.
As shown in Fig. 3 B, on this chip 10, object 16 is set, and object 16 is provided with weightening finish part 162, and weight that should weightening finish part 162 is greater than the weight of object 16.
As shown in Figure 3 C, make the projection 14 of this chip 10 mutually fully affixed with substrate 12 in the secondary returning Welding, and the end face of this chip 10 (in the non-acting surface of the present embodiment) 104 uniform-compressions reach unanimity the flatness of this chip 10 and substrate 12 flatnesses.
As shown in Fig. 3 D, on the substrate 12 outside this chip 10 setting areas, heat insulation material 18 also can be set, be heated to prevent substrate 12.In addition, these chip 10 end faces (in the non-acting surface of the present embodiment) 104 also can be provided with spacer 19, polluted by object 16 to prevent this chip 10.
as from the foregoing, chip bonding method of the present invention is applied in semiconductor packaging, with this object 16 against chip 10 end faces (in the non-acting surface of the present embodiment) 104 end faces to this chip 10 (in the non-acting surface of the present embodiment) 104, to exert pressure, proofread and correct this chip 10 because of area during large or thinner thickness, the warpage issues that causes because of reflow process, and the warpage part of this chip 10, the pressure that gives by this object 16, make warpage partly be tending towards smooth, interconnect by this projection 14 and chip 10 and substrate 12, to prevent that this projection 14 from can't interconnect fully with chip 10 and substrate 12, cause empty weldering phenomenon.
Concept of the present invention has more than engaging of the chip that is limited to the above embodiments and substrate, under identical inventive concept, more can be applicable to engaging of wafer and wafer, wafer and silicon through hole (Through silicon via; TSV) joint of wafer and other warpages because of the different generations of thermal coefficient of expansion cause the not good application of production reliability.
Above-mentioned those embodiment are illustrative effect of the present invention only, but not is used for restriction the present invention, and any those skilled in the art all can under spirit of the present invention and category, modify and change above-mentioned those embodiment.In addition, the quantity of the assembly in above-mentioned those embodiment is only illustrative, and is also non-for restriction the present invention.So the scope of the present invention, should be as listed in claims.
Claims (10)
1. chip bonding method comprises:
One substrate which is provided with chip is provided, wherein, this chip has relative acting surface and non-acting surface, on this acting surface and be formed with a plurality of projections, with connect at this chip be placed on this substrate after, described a plurality of projection is between this chip and substrate, and by being electrically connected this chip and substrate, and the projection of part only connects and is placed on chip;
One object against the non-acting surface to this chip, to bring pressure to bear on this chip, is made only to connect the projection that is placed on this chip and contact simultaneously this substrate and chip; And
The described a plurality of projections of reflow.
2. chip bonding method comprises:
One substrate which is provided with chip is provided, and wherein, this chip is located on this substrate by a plurality of projections, and the projection of part only connects and is placed on this substrate; And
By an object against and bring pressure to bear on this chip end face, make only to connect the projection that is placed on this substrate and contact simultaneously this substrate and chip, with the described a plurality of projections of reflow.
3. method according to claim 1 and 2 also is included in before this object, on this substrate is overseas for this chip connecting area, heat insulation material is set.
4. method according to claim 1 and 2, wherein, also be provided with spacer between this chip and object.
5. method according to claim 1 and 2, wherein, this substrate is semiconductor chip, printed circuit board (PCB) or the substrate with silicon perforation.
6. method according to claim 1 and 2, wherein, this object is flexible body.
7. method according to claim 1 and 2, wherein, this object is colloidal silica or accommodates liquid or granose pouch.
8. method according to claim 1 and 2, wherein, by this object against and bring pressure to bear on the step of this chip, also be included in and apply a weightening finish part on this object, its weight is greater than the weight of this object.
9. method according to claim 1 and 2, wherein, described projection also comprises rigid structure.
10. method according to claim 1 and 2, wherein, this chip has different thermal coefficient of expansions from substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100140494A TWI430421B (en) | 2011-11-07 | 2011-11-07 | Flip-chip bonding method |
| TW100140494 | 2011-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103094139A true CN103094139A (en) | 2013-05-08 |
Family
ID=48206562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101073693A Pending CN103094139A (en) | 2011-11-07 | 2012-04-12 | Flip chip bonding method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103094139A (en) |
| TW (1) | TWI430421B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183505A (en) * | 2013-05-20 | 2014-12-03 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030124769A1 (en) * | 2001-12-28 | 2003-07-03 | Yoshihisa Dotta | Semiconductor device, packaging method thereof, and package product thereof |
| CN1513206A (en) * | 2001-03-28 | 2004-07-14 | ض� | Fluxless flip chip inter connection |
| CN1537327A (en) * | 2001-03-28 | 2004-10-13 | ض� | Flip chip interconnection using no clean flux |
| US20060033214A1 (en) * | 2004-08-13 | 2006-02-16 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of the same |
| CN101447534A (en) * | 2007-11-27 | 2009-06-03 | 林志泽 | Light emitting diode and preparation method thereof |
-
2011
- 2011-11-07 TW TW100140494A patent/TWI430421B/en active
-
2012
- 2012-04-12 CN CN2012101073693A patent/CN103094139A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1513206A (en) * | 2001-03-28 | 2004-07-14 | ض� | Fluxless flip chip inter connection |
| CN1537327A (en) * | 2001-03-28 | 2004-10-13 | ض� | Flip chip interconnection using no clean flux |
| US20030124769A1 (en) * | 2001-12-28 | 2003-07-03 | Yoshihisa Dotta | Semiconductor device, packaging method thereof, and package product thereof |
| US20060033214A1 (en) * | 2004-08-13 | 2006-02-16 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of the same |
| CN101447534A (en) * | 2007-11-27 | 2009-06-03 | 林志泽 | Light emitting diode and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183505A (en) * | 2013-05-20 | 2014-12-03 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
| CN104183505B (en) * | 2013-05-20 | 2017-04-05 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201320278A (en) | 2013-05-16 |
| TWI430421B (en) | 2014-03-11 |
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Application publication date: 20130508 |