CN107968065A - Electronic component placing process and bearing jig applied by same - Google Patents
Electronic component placing process and bearing jig applied by same Download PDFInfo
- Publication number
- CN107968065A CN107968065A CN201610957213.2A CN201610957213A CN107968065A CN 107968065 A CN107968065 A CN 107968065A CN 201610957213 A CN201610957213 A CN 201610957213A CN 107968065 A CN107968065 A CN 107968065A
- Authority
- CN
- China
- Prior art keywords
- substrate
- bearing
- processing procedure
- cover piece
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000008569 process Effects 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000012545 processing Methods 0.000 claims description 27
- 238000005520 cutting process Methods 0.000 claims description 14
- 230000003139 buffering effect Effects 0.000 claims 1
- 230000008602 contraction Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- XLTRGZZLGXNXGD-UHFFFAOYSA-N benzene;1h-pyrazole Chemical compound C=1C=NNC=1.C1=CC=CC=C1 XLTRGZZLGXNXGD-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67772—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving removal of lid, door, cover
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
A process for placing electronic component and its bearing tool are disclosed, which features that a substrate is arranged on a bearing part, and a cover part is arranged on said bearing part, and a gap is arranged between said cover part and substrate.
Description
Technical field
The present invention is in relation to a kind of preparation method of electronic component, the carrying for putting processing procedure and its application of espespecially a kind of electronic component
Gauge.
Background technology
With flourishing for electronic industry, electronic product is also gradually marched toward multi-functional, high performance trend, it mainly leads to
More and more functions are integrated on excessively same electronic product, but this also requires electronic product volume frivolous at the same time, therefore, to coordinate
The trend of microminiaturization development, industry are satisfied by the thickness for reducing package substrate, to reach the mesh that electronic product is multi-functional, minimizes
's.
However, the package substrate after thinning, which since rigidity is poor and easily heated processing procedure influences and deforms, causes to connect, is placed in this
The probability increase of rosin joint (non-wetting) occurs for the convex block of flip on package substrate, therefore for package substrate in hot processing procedure
In planarization and the problem of stress release solved by cover piece.
As shown in Figure 1, it is to note semiconductor package part 4 using bearing fixture 1 in the diagrammatic cross-section of flip chip manufacturing process.It is first
First, the package substrate 40 for one being equipped with multiple chips 41 is arranged on a bearing part 10, and a cover piece 11 is arranged on the bearing part 10
Upper simultaneously gland package substrate 40, wherein, which connects through multiple 410 flips of solder bump and is placed in the package substrate 40
On, then, those solder bumps 410 of reflow (Reflow), wherein, though the package substrate 40 can produce deformation after heated,
Pressed by the cover piece 11 and touch the package substrate 40, be able to suppress the dimensional deformation of the package substrate 40.
However, noting in flip chip manufacturing process, contact the package substrate 40 by the cover piece 11 and limit the package substrate 40 and become
The mode of shape, also suppresses the space of 40 thermal expansion and contraction of package substrate, the package substrate 40 can not be discharged its internal pressure at the same time,
Thus increase the potential deformation amount of the package substrate 40, so that when the package substrate 40 takes out from the bearing fixture 1, should
The potential deformation amount of package substrate 40 can make the package substrate 40 cause the package substrate 40 can not be with this there is a phenomenon where warpage
The effectively contact or contact associativity of solder bump 410 is bad.
Therefore, above-mentioned the problem of noting technology how is overcome, it is real into the problem for desiring most ardently solution at present.
The content of the invention
In view of the above-mentioned disadvantages for noting technology, the storing processing procedure of the invention that a kind of electronic component is provided and its application
Bearing fixture, to avoid occur substrate warped the problem of.
The bearing fixture applied to electronic component of the present invention, including：Bearing part, its to bearing substrate, wherein, the base
Plate definition has at least one storing area；And cover piece, it is arranged on the bearing part, wherein, between having between the cover piece and the substrate
Every, and the cover piece has at least one opening in the corresponding storing area.
The present invention also provides a kind of storing processing procedure of electronic component, including：One substrate is arranged on a bearing part, wherein,
Substrate definition has at least one storing area；And a cover piece is arranged on the bearing part, wherein, have between the cover piece and the substrate
There is interval, and the cover piece has at least one opening in the corresponding storing area.
In the bearing fixture for putting processing procedure and its application of foregoing electronic component, which has multiple storing areas,
And the cover piece has the opening in multiple correspondences storing area.
In the bearing fixture for putting processing procedure and its application of foregoing electronic component, electronics member is provided with the storing area
Part.
In the bearing fixture for putting processing procedure and its application of foregoing electronic component, the electronic component is by multiple conductive elements
Part is arranged in the storing area.For example, the interval is more than the height of the conducting element.
In the bearing fixture for putting processing procedure and its application of foregoing electronic component, which also includes to contact this
The supporting part of substrate.For example, the substrate there is also defined the Cutting Road around the corresponding storing area, the position correspondence of the supporting part should
The position of Cutting Road, and the width of the supporting part is less than or equal to the width of the Cutting Road.
In the bearing fixture for putting processing procedure and its application of foregoing electronic component, in the interval between the cover piece and the substrate
It is also formed with cushion.
From the foregoing, it will be observed that the electronic component of the present invention puts processing procedure and its bearing fixture of application, mainly by when the base
When plate is arranged on the bearing part, there is interval, with when reflow operation is carried out, which can conduct between the cover piece and the substrate
The thermal expansion and contraction space of the substrate, enables the substrate to discharge the pressure of thermal expansion and contraction, therefore compared to noting technology, when the substrate is from this hair
When being taken out in bright bearing fixture, which will not be there is a phenomenon where warpage, thus is avoided that the substrate with putting electronics to connect
The problem of bad is in contact between the conducting element of element.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-section for the flip chip manufacturing process for noting semiconductor package part；
Fig. 2A and Fig. 2 B are the diagrammatic cross-section of the storing processing procedure of the electronic component of the present invention；And
Fig. 3 A and Fig. 3 B are the diagrammatic cross-section of the different embodiments of corresponding diagram 2B.
Symbol description
1,2 bearing fixtures
10,20 bearing parts
11,21 cover pieces
210 openings
211 supporting parts
212 pins
3 electronic components
30 substrates
300 put area
31 electronic components
310 conducting elements
32 cushions
4 semiconductor package parts
40 package substrates
41 chips
410 solder bumps
T intervals
H height
D, r width
S Cutting Roads.
Embodiment
Illustrate embodiments of the present invention by particular specific embodiment below, people skilled in the art can be by this theory
The bright revealed content of book understands other advantages and effect of the present invention easily.
It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., only coordinating specification to be taken off
The content shown, for the understanding and reading of people skilled in the art, is not limited to the enforceable qualifications of the present invention,
Therefore not having technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, are not influencing this hair
Under bright the effect of can be generated and the purpose that can reach, it should all still fall and obtain what can be covered in disclosed technology contents
In the range of.Meanwhile in this specification it is cited such as " on ", " first ", the term of " second " and " one ", be also only easy to chat
That states understands, and is not used to limit the enforceable scope of the present invention, its relativeness is altered or modified, and skill is being changed without essence
Held in art, when being also considered as the enforceable category of the present invention.
Fig. 2A is the diagrammatic cross-section of the bearing fixture 2 applied to electronic component of the present invention.
As shown in Figure 2 A, which includes a bearing part 20 and a cover piece 21.
The bearing part 20 is to carry a substrate 30, and the substrate 30 definition has multiple storing areas 300.
The cover piece 21 is arranged on the bearing part 20 and has by an at least pin 212 corresponds to the storing area respectively
300 multiple openings 210, and when the substrate 30 is arranged on the bearing part 20, between having between the cover piece 21 and the substrate 30
Every t.
Fig. 2A to Fig. 2 B is the diagrammatic cross-section of the storing processing procedure of the electronic component 3 of the present invention.
As shown in Figure 2 A, by taking above-mentioned bearing fixture 2 as an example, a substrate 30 is arranged on the bearing part 20, then by the cover piece
21 are arranged on the bearing part 20, and have interval t between the cover piece 21 and the substrate 30.
In this present embodiment, the substrate 30 tool line layer (not shown), it is, for example, line construction, the circuit of seedless central layer
Plate or the wiring board with core layer.
As shown in Figure 2 B, multiple electronic components 31 are arranged in the storing area 300 of the substrate 30 by the corresponding opening 210, its
In, which includes the substrate 30 and the electronic component 31.
In this present embodiment, the electronic component 31 be active member, passive device or combination etc. both it, and the active element
Part is, for example, semiconductor wafer, and the passive device is, for example, resistance, capacitance and inductance.Specifically, the electronic component 31 is with more
On a line layer that the substrate 30 is combined such as 310 flip of conducting element of solder bump or copper post, and interval t is more than the conduction
The height h of element 310, then those conducting elements 310 of reflow are the electronic component 31 is fixed on the substrate 30.
However, the combination of the electronic component 31 and the substrate 30 is depending on demand, however it is not limited to above-mentioned rewinding method,
Or it is fanned out to mode, routing mode or other means.
Due to having interval t in the present invention between the cover piece 21 and the substrate 30, therefore when the substrate 30 is arranged on the bearing part
On 20, and when carrying out hot processing procedure (such as back welding process), interval t can make the substrate 30 as the thermal expansion and contraction space of the substrate 30
The pressure of thermal expansion and contraction can be discharged, therefore compared to technology is noted, should when the substrate 30 takes out from the bearing fixture 2 of the present invention
Substrate 30 will not there is a phenomenon where warpage, thus be avoided that between the substrate 30 and the conducting element 310 be in contact it is undesirable
Problem.
In addition, as shown in Figure 3A, which also has to contact the supporting part 211 of the substrate 30.Specifically, the base
Plate 30 corresponds to and Cutting Road S is equipped with around the storing area 300, the position of the position correspondence of the supporting part 211 Cutting Road S, and should
The width r of supporting part 211 be less than or equal to Cutting Road S width d, for example, the width d of Cutting Road S for 0.2mm extremely
0.3mm。
Also, as shown in Figure 3B, also can be formed with cushion 32 in the interval t between the cover piece 21 and the substrate 30, this is slow
It is insulating layer to rush layer 32, its material is, for example, polyimide (Polyimide, abbreviation PI), gathers to diazole benzene
(Polybenzoxazole, abbreviation PBO) or other high molecular materials.
Subsequently, when hot processing procedure (such as back welding process) is carried out, which can coordinate the thermal expansion and contraction of the substrate 30 and become
Shape, enables the substrate 30 to discharge the pressure of thermal expansion and contraction, therefore when the substrate 30 takes out from the bearing fixture 2 of the present invention, the base
Plate 30 will not there is a phenomenon where warpage.
In conclusion the electronic component of the present invention puts processing procedure and its bearing fixture of application, mainly set by when substrate
When on bearing part, using having interval between cover piece and the substrate, with when hot processing procedure is carried out, which can be used as the substrate
Thermal expansion and contraction space, therefore when the substrate takes out from bearing fixture, the substrate will not there is a phenomenon where warpage.
Above-described embodiment is only to be illustrated the principle of the present invention and its effect, not for the limitation present invention.Appoint
What those skilled in the art can modify above-described embodiment under the spirit and scope without prejudice to the present invention.Cause
This scope of the present invention, should be as listed by claims.
Claims (18)
1. a kind of bearing fixture applied to electronic component, it is characterized in that, which includes：
Bearing part, its to bearing substrate, wherein, the substrate definition have at least one storing area；And
Cover piece, it is arranged on the bearing part, wherein, there is interval between the cover piece and the substrate, and the cover piece have it is corresponding should
Put at least one opening in area.
2. bearing fixture as claimed in claim 1, it is characterized in that, substrate definition has multiple storing areas, and the cover piece has
The opening in multiple correspondences storing area.
3. bearing fixture as claimed in claim 1, it is characterized in that, it is provided with electronic component in the storing area.
4. bearing fixture as claimed in claim 3, it is characterized in that, which is arranged on the storing by multiple conducting elements
Qu Shang.
5. bearing fixture as claimed in claim 4, it is characterized in that, which is more than the height of the conducting element.
6. bearing fixture as claimed in claim 1, it is characterized in that, which also includes the support for contacting the substrate
Portion.
7. bearing fixture as claimed in claim 6, it is characterized in that, which there is also defined the cutting around the storing area
Road, wherein, the position of the position correspondence of the supporting part Cutting Road.
8. bearing fixture as claimed in claim 7, it is characterized in that, the width of the supporting part is less than or equal to the width of the Cutting Road
Degree.
9. bearing fixture as claimed in claim 1, it is characterized in that, which further includes the buffering being formed in the interval
Layer.
10. a kind of storing processing procedure of electronic component, it is characterized in that, which includes：
One substrate is arranged on a bearing part, wherein, substrate definition has at least one storing area；And
By a cover piece on the bearing part, wherein, there is interval, and the cover piece has corresponding be somebody's turn to do between the cover piece and the substrate
Put at least one opening in area.
11. processing procedure is put as claimed in claim 10, it is characterized in that, which has multiple storing areas, and the cover piece has
There is the opening in multiple correspondences storing area.
12. processing procedure is put as claimed in claim 10, it is characterized in that, it is provided with electronic component in the storing area.
13. processing procedure is put as claimed in claim 12, it is characterized in that, which puts by multiple conducting elements arranged on this
Put in area.
14. processing procedure is put as claimed in claim 13, it is characterized in that, which is more than the height of the conducting element.
15. processing procedure is put as claimed in claim 10, it is characterized in that, which also includes the support for contacting the substrate
Portion.
16. processing procedure is put as claimed in claim 15, it is characterized in that, which there is also defined cutting around the storing area
Cut, wherein, the position of the position correspondence of the supporting part Cutting Road.
17. processing procedure is put as claimed in claim 16, it is characterized in that, the width of the supporting part is less than or equal to the Cutting Road
Width.
18. processing procedure is put as claimed in claim 10, it is characterized in that, formed with cushion in the interval.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105133869 | 2016-10-20 | ||
| TW105133869A TWI642133B (en) | 2016-10-20 | 2016-10-20 | Mounting method for electronic component and carrying jig applying the mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107968065A true CN107968065A (en) | 2018-04-27 |
Family
ID=61996499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610957213.2A Pending CN107968065A (en) | 2016-10-20 | 2016-11-03 | Electronic component placing process and bearing jig applied by same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107968065A (en) |
| TW (1) | TWI642133B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020093080A1 (en) * | 2001-01-16 | 2002-07-18 | St Assembly Test Services Pte Ltd | Process carrier for flexible substrates |
| CN101236282A (en) * | 2008-02-04 | 2008-08-06 | 日月光半导体制造股份有限公司 | Lens module group packaging fixture and its encapsulation method using same |
| CN102376598A (en) * | 2010-08-06 | 2012-03-14 | 三星电子株式会社 | Apparatus for wafer level bump reflow, system and method thereof |
| CN102386114A (en) * | 2010-09-01 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Method of bonding chips |
| CN103000559A (en) * | 2011-09-16 | 2013-03-27 | 富士电机株式会社 | Positioning clamp for semiconductor chip and manufacture method for semiconductor device |
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| CN103000550A (en) * | 2011-09-15 | 2013-03-27 | 株式会社日立高新技术仪器 | Die bonder and bonding method |
| US20130089952A1 (en) * | 2011-10-11 | 2013-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Process Tools and Packaging Methods for Semiconductor Devices |
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| CN105960708A (en) * | 2014-09-27 | 2016-09-21 | 英特尔公司 | Substrate warpage control using temper glass with uni-directional heating |
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| TW582083B (en) * | 2003-04-17 | 2004-04-01 | Advanced Semiconductor Eng | Fixture for die-pull test |
| TWI257674B (en) * | 2004-09-07 | 2006-07-01 | Siliconware Precision Industries Co Ltd | Fabrication method and carrier of semiconductor packages |
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2016
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|---|---|---|---|---|
| US20020093080A1 (en) * | 2001-01-16 | 2002-07-18 | St Assembly Test Services Pte Ltd | Process carrier for flexible substrates |
| CN101236282A (en) * | 2008-02-04 | 2008-08-06 | 日月光半导体制造股份有限公司 | Lens module group packaging fixture and its encapsulation method using same |
| CN102376598A (en) * | 2010-08-06 | 2012-03-14 | 三星电子株式会社 | Apparatus for wafer level bump reflow, system and method thereof |
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| CN103000550A (en) * | 2011-09-15 | 2013-03-27 | 株式会社日立高新技术仪器 | Die bonder and bonding method |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201816914A (en) | 2018-05-01 |
| TWI642133B (en) | 2018-11-21 |
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Application publication date: 20180427 |