TW201813043A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW201813043A
TW201813043A TW105128409A TW105128409A TW201813043A TW 201813043 A TW201813043 A TW 201813043A TW 105128409 A TW105128409 A TW 105128409A TW 105128409 A TW105128409 A TW 105128409A TW 201813043 A TW201813043 A TW 201813043A
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Taiwan
Prior art keywords
circuit structure
layer
electronic component
electronic package
electronic
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TW105128409A
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English (en)
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TWI676259B (zh
Inventor
張宏達
姜亦震
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW105128409A priority Critical patent/TWI676259B/zh
Priority to CN201610819247.5A priority patent/CN107799479A/zh
Priority to US15/494,814 priority patent/US20180068983A1/en
Publication of TW201813043A publication Critical patent/TW201813043A/zh
Priority to US16/356,589 priority patent/US20190214372A1/en
Application granted granted Critical
Publication of TWI676259B publication Critical patent/TWI676259B/zh

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Abstract

一種電子封裝件係包括：第一線路結構；設於該第一線路結構上之電子元件與導電柱；包覆該電子元件與導電柱之包覆層；形成於該包覆層上之第二線路結構；以及覆蓋於該第一線路結構、包覆層之側面與第二線路結構之側面之屏蔽層，使該電子元件外圍覆蓋有屏蔽層，以於該電子封裝件運作時，避免該電子元件遭受外界之電磁干擾。本發明復提供該電子封裝件之製法。

Description

電子封裝件及其製法
本發明係有關一種封裝技術，尤指一種避免電磁干擾之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足電子封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging，簡稱WLP)的技術。
第1A至1E圖係為習知晶圓級之半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一熱化離形膠層(thermal release tape)100於一承載件10上。
接著，置放複數半導體元件11於該熱化離形膠層100上，該些半導體元件11具有相對之作用面11a與非作用面11b，各該作用面11a上均具有複數電極墊110，且各該作用面11a黏著於該熱化離形膠層100上。
如第1B圖所示，形成一封裝膠體14於該熱化離形膠層100上，以包覆該半導體元件11。
如第1C圖所示，烘烤該封裝膠體14以硬化該熱化離形膠層100而移除該熱化離形膠層100與該承載件10，以外露出該半導體元件11之作用面11a。
如第1D圖所示，形成一線路結構16於該封裝膠體14與該半導體元件11之作用面11a上，令該線路結構16電性連接該電極墊110。接著，形成一絕緣保護層18於該線路結構16上，且該絕緣保護層18外露該線路結構16之部分表面，以供結合如銲球之導電元件17。
如第1E圖所示，沿如第1D圖所示之切割路徑L進行切單製程，以獲取複數個半導體封裝件1。
惟，習知半導體封裝件1於運作時，因其不具用於電磁干擾(Electromagnetic interference，簡稱EMI)屏蔽(shielding)的結構，故該半導體元件11容易遭受到外界之電磁干擾(EMI)，因而影響整體該半導體封裝件1的電性效能。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：第一線路結構，係具有相對之第一側與第二側，且該第一側上形成有電性連接該第一線路結構之導電柱；第一電子元件，係設於該第一線路結構之第一側上；包覆層，係形成於該第一線路結構之第一側上，以令該包覆層包覆該第一電子元件與該導電柱，且令該第一電子元 件之部分表面與該導電柱之端面外露於該包覆層；第二線路結構，係形成於該包覆層上且電性連接該導電柱與該第一電子元件；以及屏蔽層，係形成於該第一線路結構之第二側上並延伸至該第一線路結構之側面、包覆層之側面與第二線路結構之側面。
本發明復提供一種電子封裝件，係包括：第一線路結構，係具有相對之第一側與第二側，且該第一側上形成有電性連接該第一線路結構之導電柱；第一電子元件，係設於該第一線路結構之第一側上；包覆層，係形成於該第一線路結構之第一側上，以令該包覆層包覆該第一電子元件與該導電柱，且令該第一電子元件之部分表面與該導電柱之端面外露於該包覆層；第二線路結構，係形成於該包覆層上且電性連接該導電柱與該第一電子元件；第二電子元件，係設於該第一線路結構之第二側上；封裝層，係形成於該第一線路結構之第二側上，以令該封裝層包覆該第二電子元件；以及屏蔽層，係形成於該封裝層上並延伸至該第一線路結構之側面、包覆層之側面與第二線路結構之側面。
本發明亦提供一種電子封裝件之製法，係包括：提供一第一線路結構，該第一線路結構具有相對之第一側與第二側；形成電性連接該第一線路結構之導電柱於該第一側上，且設置第一電子元件於該第一線路結構之第一側上；形成包覆層於該第一線路結構之第一側上，以令該包覆層包覆該第一電子元件與該導電柱，且令該第一電子元件之 部分表面與該導電柱之端面外露於該包覆層；形成第二線路結構於該包覆層上，且該第二線路結構電性連接該導電柱與該第一電子元件；設置第二電子元件於該第一線路結構之第二側上；形成封裝層於該第一線路結構之第二側上，以令該封裝層包覆該第二電子元件；以及形成屏蔽層於該封裝層上，且令該屏蔽層延伸至該第一線路結構之側面、包覆層之側面與第二線路結構之側面。
前述之電子封裝件及其製法中，該屏蔽層係電性連接該第一線路結構。
前述之電子封裝件及其製法中，該屏蔽層係電性連接該第二線路結構。
前述之電子封裝件及其製法中，該屏蔽層係電性連接該第一線路結構與第二線路結構。
前述之電子封裝件及其製法中，該第二線路結構係外露於該封裝層。
前述之電子封裝件及其製法中，復包括複數導電元件，係形成於該第二線路結構上。
由上可知，本發明之電子封裝件及其製法，主要藉由該屏蔽層之設計，使該第一電子元件及/或第二電子元件外圍覆蓋有屏蔽層，以於運作該電子封裝件時，該第一電子元件及/或第二電子元件不會遭受外界之電磁干擾，故相較於習知技術，本發明之電子封裝件的電性功能得以正常運作。
1‧‧‧半導體封裝件
10‧‧‧承載件
100‧‧‧熱化離形膠層
11‧‧‧半導體元件
11a,21a‧‧‧作用面
11b,21b‧‧‧非作用面
110,210‧‧‧電極墊
14‧‧‧封裝膠體
16‧‧‧線路結構
17,27,27’‧‧‧導電元件
18,28‧‧‧絕緣保護層
2,2’,3,3’‧‧‧電子封裝件
20‧‧‧第一線路結構
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧第一絕緣層
201‧‧‧第一線路重佈層
21‧‧‧第一電子元件
211‧‧‧絕緣層
212‧‧‧導電體
214,91‧‧‧結合層
22‧‧‧第二電子元件
23‧‧‧導電柱
24‧‧‧封裝層
25‧‧‧包覆層
26‧‧‧第二線路結構
260,260’‧‧‧第二絕緣層
261,261’‧‧‧第二線路重佈層
270‧‧‧凸塊底下金屬層
29,29’,29”‧‧‧屏蔽層
290‧‧‧凹槽
9‧‧‧承載板
90‧‧‧離型層
L,S‧‧‧切割路徑
第1A至1E圖係為習知半導體封裝件之製法之剖面示意圖；第2A至2F圖係為本發明之電子封裝件之製法的剖面示意圖；第2F’及2F”圖係為本發明之電子封裝件之其它製法的剖面示意圖；以及第3A及3B圖係為本發明之電子封裝件之其它不同實施利的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之電子封裝件2之製法的剖 面示意圖。
如第2A圖所示，於一承載板9上結合一第一線路結構20，該第一線路結構20具有相對之第一側20a與第二側20b，且該第一線路結構20以其第二側20b結合至該承載板9上。接著，於該第一側20a上形成複數電性連接該第一線路結構20之導電柱23，且設置第一電子元件21於該第一線路結構20之第一側20a上，其中，該第一電子元件21上係結合並電性連接複數導電體212，且該導電體212係為如銲球之圓球狀、或如銅柱、銲錫凸塊等金屬材之柱狀、或銲線機製作之釘狀(stud)，但不限於此。
於本實施例中，該第一線路結構20係包括至少一第一絕緣層200與設於該第一絕緣層200上之一第一線路重佈層(redistribution layer，簡稱RDL)201。例如，形成該第一線路重佈層201之材質係為銅，且形成該第一絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。
再者，該承載板9係例如為半導體材質之圓形板體，其上以塗佈方式依序形成有一離型層90與一結合層91，以供該第一線路結構20設於該結合層91上。
又，該導電柱23係設於該第一線路重佈層201上並電性連接該第一線路重佈層201，且形成該導電柱23之材質係為如銅之金屬材或銲錫材。
另外，該第一電子元件21係為主動元件、被動元件或 其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第一電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，該第一電子元件21係以其非作用面21b藉由一結合層214黏固於該第一線路結構20之第一側20a上，而該作用面21a具有複數電極墊210，其中，該導電體212形成於該電極墊210上，另於該作用面21a上形成有一絕緣層211，以令該絕緣層211覆蓋該些電極墊210與該些導電體212。或者，亦可令該導電體212外露於該絕緣層211。
如第2B圖所示，形成一包覆層25於該第一線路結構20之第一側20a上，以令該包覆層25包覆該第一電子元件21、該些導電體212與該些導電柱23，再藉由整平製程，令該包覆層25之表面齊平該絕緣層211之表面、該導電柱23之端面與該導電體212之端面，使該絕緣層211之表面、該導電柱23之端面與該導電體212之端面外露於該包覆層25。
於本實施例中，該包覆層25係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該第一線路結構20之第一側20a上。
再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質、該絕緣層211之部分材質(依需求，可同時移除該導電體212之部分材質)、與該包覆層25之部分材質。
應可理解地，若該導電體212已外露於該絕緣層211， 則移除該絕緣層211之部分材質，即可令該些導電體212外露於該包覆層25(依需求，亦可同時移除該絕緣層211之部分材質與該導電體212之部分材質，而令該些導電體212外露於該包覆層25)。
如第2C圖所示，形成一第二線路結構26於該包覆層25上，且令該第二線路結構26電性連接該些導電柱23與該導電體212。
於本實施例中，該第二線路結構26係包括複數第二絕緣層260,260’、及設於該第二絕緣層260,260’上之複數第二線路重佈層(RDL)261,261’，且最外層之第二絕緣層260’可作為防銲層，以令最外層之第二線路重佈層261’外露於該防銲層。或者，該第二線路結構26亦可僅包括單一第二絕緣層260及單一第二線路重佈層261。
再者，形成該第二線路重佈層261,261’之材質係為銅，且形成該第二絕緣層260,260’之材質係為如聚對二唑苯(PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)之介電材。
如第2D圖所示，移除該承載板9及其上之離型層90。接著，形成複數如銲球之導電元件27於該第一線路結構20之第二側20b上，以供接置至少一第二電子元件22。
於本實施例中，該第二電子元件22係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
再者，可選擇性地形成一如防銲層之絕緣保護層28 於該第一線路結構20之第二側20b上(或該結合層91上)，再形成複數開孔於該絕緣保護層28與該結合層91上，以令該第一線路重佈層201之部分表面外露於該些開孔，俾供結合該些導電元件27。或者，可不形成該絕緣保護層28，而直接形成複數開孔於該結合層91上，以令該第一線路重佈層201之部分表面外露於該些開孔，俾供結合該些導電元件27。
如第2E圖所示，經切單製程後，再形成一封裝層24於該第一線路結構20之第二側20b上，以包覆該些第二電子元件22。接著，形成複數如銲球之導電元件27’於最外層之第二線路重佈層261’上，俾供後續接置如封裝結構或晶片等電子裝置(圖略)。
於本實施例中，可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)270於最外層之第二線路重佈層261’上，以利於結合該導電元件27’。
如第2F圖所示，形成一屏蔽層29於該封裝層24上並延伸至該第一線路結構20之側面、包覆層25之側面與第二線路結構26之側面。
於本實施例中，該屏蔽層29係為金屬材質，其電性連接該第一線路結構20之第一線路重佈層201。
再者，於另一製法中，如第2F’圖所示之電子封裝件2’，於第2C圖之製程後，係移除該承載板9及其上之離型層90，再形成一屏蔽層29於該第一線路結構20之第二側20b上(或該結合層91上)並延伸至該第一線路結構 20之側面、包覆層25之側面與第二線路結構26之側面，且該屏蔽層29係電性連接該第一線路結構20之第一線路重佈層201。
又，如第2F”圖所示，於另一製法中，如量產過程中，先形成複數凹槽290於該封裝層24上並貫穿結構上下側，再形成該屏蔽層29於該些凹槽290中，之後再沿如第2F"圖所示之切割路徑S(該切割路徑S通過該凹槽290)進行切單製程，以得到如第2F圖所示之電子封裝件2。
因此，本發明之電子封裝件2,2’之製法係藉由該屏蔽層29之設計，使該第一電子元件21或第二電子元件22外圍覆蓋有屏蔽層29，故該電子封裝件2,2’於運作時，該第一電子元件21或第二電子元件22不會遭受外界之電磁干擾(EMI)，因而該電子封裝件2,2’的電性運作功能得以正常，避免影響整體該電子封裝件2,2’的電性效能。
再者，該屏蔽層29可經由該第一線路結構21之第一線路重佈層201接地。或者，如第3A圖所示，該屏蔽層29’係電性連接該第二線路結構26之第二線路重佈層261，以令該屏蔽層29’經由該第二線路結構26之第二線路重佈層261接地。亦可如第3B圖所示，該屏蔽層29”係電性連接該第一線路重佈層201與第二線路重佈層261，以令該屏蔽層29”經由該第一線路重佈層201與第二線路重佈層261接地。
應可理解地，該第一電子元件21可經由該第二線路結構26接地(如第3A或3B圖所示)、或經由該第二線路結 構26、該導電柱23與該第一線路結構20接地(如第2F或3B圖所示)。或者，該第二電子元件22可經由該第一線路結構20接地(如第2F或3B圖所示)、或經由該第一線路結構20、該導電柱23與該第二線路結構26接地(如第3A或3B圖所示)。
本發明亦提供一種電子封裝件2，其包括：一第一線路結構20、一第一電子元件21、一包覆層25、一第二線路結構26、至少一第二電子元件22、一封裝層24以及一屏蔽層29,29’,29”。
所述之第一線路結構20係具有相對之第一側20a與第二側20b，且該第一側20a上形成有複數電性連接該第一線路結構20之導電柱23。
所述之第一電子元件21係設於該第一線路結構20之第一側20a上，且該第一電子元件21上結合有複數導電體212。
所述之包覆層25係形成於該第一線路結構20之第一側20a上，以令該包覆層25包覆該第一電子元件21與該些導電柱23，且令該導電柱23之端面與該導電體212之端面外露於該包覆層25。
所述之第二線路結構26係形成於該包覆層25上，且該第二線路結構26電性連接該導電柱23與該第一電子元件21之導電體212。
所述之第二電子元件22係設於該第一線路結構20之第二側20b上。
所述之封裝層24係形成於該第一線路結構20之第二側20b上，以令該封裝層24包覆該第二電子元件22。
所述之屏蔽層29,29’,29”係形成於該封裝層24上並延伸至該第一線路結構20之側面、包覆層25之側面與第二線路結構26之側面。
於一實施例中，該屏蔽層29係電性連接該第一線路結構20。
於一實施例中，該屏蔽層29’係電性連接該第二線路結構26。
於一實施例中，該屏蔽層29”係電性連接該第一線路結構20與第二線路結構26。
於一實施例中，該第二線路結構26係外露於該封裝層24。
於一實施例中，該電子封裝件2復包括複數導電元件27’，係形成於該第二線路結構26上。
本發明復提供一種電子封裝件2’，其包括：一第一線路結構20、一第一電子元件21、一包覆層25、一第二線路結構26、以及一屏蔽層29。
所述之屏蔽層29係形成於該第一線路結構20之第二側20b上並延伸至該第一線路結構20之側面、包覆層25之側面與第二線路結構26之側面。
綜上所述，本發明之電子封裝件及其製法，係藉由該屏蔽層，以於該電子封裝件運作時，能避免該第一電子元件及/或第二電子元件遭受外界之電磁干擾，使該電子封裝 件的電性功能得以正常運作。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (17)

  1. 一種電子封裝件，係包括：第一線路結構，係具有相對之第一側與第二側，且該第一側上形成有電性連接該第一線路結構之導電柱；第一電子元件，係設於該第一線路結構之第一側上；包覆層，係形成於該第一線路結構之第一側上，以令該包覆層包覆該第一電子元件與該導電柱，且令該第一電子元件之部分表面與該導電柱之端面外露於該包覆層；第二線路結構，係形成於該包覆層上且電性連接該導電柱與該第一電子元件；以及屏蔽層，係形成於該第一線路結構之第二側上並延伸至該第一線路結構之側面、包覆層之側面與第二線路結構之側面。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該屏蔽層係電性連接該第一線路結構及/或第二線路結構。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該第一電子元件具有相對之作用面與非作用面，該第一電子元件係以該非作用面結合於該第一線路結構之第一側上，而該作用面具有複數電極墊，且該電極墊上形成有導電體。
  4. 如申請專利範圍第3項所述之電子封裝件，其中，該導電體之端面係外露於該包覆層。
  5. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該第二線路結構上之複數導電元件。
  6. 一種電子封裝件，係包括：第一線路結構，係具有相對之第一側與第二側，且該第一側上形成有電性連接該第一線路結構之導電柱；第一電子元件，係設於該第一線路結構之第一側上；包覆層，係形成於該第一線路結構之第一側上，以令該包覆層包覆該第一電子元件與該導電柱，且令該第一電子元件之部分表面與該導電柱之端面外露於該包覆層；第二線路結構，係形成於該包覆層上且電性連接該導電柱與該第一電子元件；第二電子元件，係設於該第一線路結構之第二側上；封裝層，係形成於該第一線路結構之第二側上，以令該封裝層包覆該第二電子元件；以及屏蔽層，係形成於該封裝層上並延伸至該第一線路結構之側面、包覆層之側面與第二線路結構之側面。
  7. 如申請專利範圍第6項所述之電子封裝件，其中，該屏蔽層係電性連接該第一線路結構及/或第二線路結結構。
  8. 如申請專利範圍第6項所述之電子封裝件，其中，該第一電子元件具有相對之作用面與非作用面，該第一電子 元件係以該非作用面結合於該第一線路結構之第一側上，而該作用面具有複數電極墊，且該電極墊上形成有導電體。
  9. 如申請專利範圍第8項所述之電子封裝件，其中，該導電體之端面係外露於該包覆層。
  10. 如申請專利範圍第6項所述之電子封裝件，其中，該第二線路結構係外露於該封裝層。
  11. 如申請專利範圍第6項所述之電子封裝件，復包括形成於該第二線路結構上之複數導電元件。
  12. 一種電子封裝件之製法，係包括：提供一具有相對之第一側與第二側之第一線路結構；形成電性連接該第一線路結構之導電柱於該第一側上，且設置第一電子元件於該第一線路結構之第一側上；形成包覆層於該第一線路結構之第一側上，以令該包覆層包覆該第一電子元件與該導電柱，且令該第一電子元件之部分表面與該導電柱之端面外露於該包覆層；形成第二線路結構於該包覆層上，且令該第二線路結構電性連接該導電柱與該第一電子元件；設置第二電子元件於該第一線路結構之第二側上；形成封裝層於該第一線路結構之第二側上，以令該封裝層包覆該第二電子元件；以及形成屏蔽層於該封裝層上，且令該屏蔽層延伸至該 第一線路結構之側面、包覆層之側面與第二線路結構之側面。
  13. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該屏蔽層係電性連接該第一線路結構及/或第二線路結構。
  14. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該第一電子元件具有相對之作用面與非作用面，該第一電子元件係以該非作用面結合於該第一線路結構之第一側上，而該作用面具有複數電極墊，且該電極墊上形成有導電體。
  15. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該導電體之端面係外露於該包覆層。
  16. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該第二線路結構係外露於該封裝層。
  17. 如申請專利範圍第12項所述之電子封裝件之製法，復包括形成複數導電元件於該第二線路結構上。
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