TW201742224A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TW201742224A
TW201742224A TW106103765A TW106103765A TW201742224A TW 201742224 A TW201742224 A TW 201742224A TW 106103765 A TW106103765 A TW 106103765A TW 106103765 A TW106103765 A TW 106103765A TW 201742224 A TW201742224 A TW 201742224A
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epitaxial substrate
substrate
insulating film
interlayer insulating
semiconductor device
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TW106103765A
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Junichi Okayasu
Yoshiaki Abe
Takuya Oizumi
Takahiro Yashiro
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Advantest Corp
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Abstract

本發明提供能夠高速動作的半導體元件。半導體元件100中，磊晶基板102包括SiC（碳化矽）基板及形成於SiC基板上的GaN（氮化鎵）的磊晶層。多層配線結構300形成於磊晶基板102的表面側，包含至少一個金屬配線層M1及有機系層間絕緣膜。背面金屬層120形成於磊晶基板102的背面。至少一個通孔122形成於磊晶基板102，將多層配線結構300與背面金屬層120之間加以連接。

Description

半導體元件及其製造方法
本發明是有關於一種半導體元件。
作為現有的矽系半導體元件的代替品，能夠更高速動作的氮化物半導體元件的開發正在推進。圖1是現有的氮化物半導體元件的剖視圖。半導體元件100R具備磊晶（epitaxial）基板102、層間絕緣膜104、層間絕緣膜106及配線層110、配線層112、配線層114。半導體元件100R中，高電子遷移率電晶體（High Electron Mobility Transistor，HEMT）200、薄膜電阻（thin film resistor，TFR）202、金屬-絕緣體-金屬（Metal-Insulator-Metal，MIM）電容器204、GND端子（焊墊）206或VSS配線208等進行積體化，從而構成高頻電路（單晶微波積體電路（Monolithic Microwave Integrated Circuit，MMIC））。
為了強化相對於HEMT 200的接地，有時在磊晶基板102的背面形成背面金屬層120。而且，背面金屬層120與應成為接地電位的配線層110的配線之間經由通孔（through hole）122而連接。 [先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2013-191763號公報 [專利文獻2]日本專利特表2003-530716號公報 [專利文獻3]日本專利特表2008-532290號公報
[發明所欲解決之課題] 本發明者等人對圖1所示的現有技術進行了研究後，結果認識到以下的課題。另外，不應將此處的研究或認識當作業者的一般性認識、知識。
在形成通孔122時，需要對磊晶基板102，藉由蝕刻而施作開口（Via-hole蝕刻）。SiC因具有高耐蝕刻性，故若欲蝕刻出例如厚度100 μm的磊晶基板102，則基板溫度上升至300℃～400℃。因此，作為層間絕緣膜104、層間絕緣膜106，必須採用不易伴隨基板溫度的上升而受損的無機系的材料，例如SiN膜（氮化矽）。或者，亦存在利用空氣橋（air bridge）與SiN膜形成層間絕緣膜的情況。
然而，因SiN膜的介電常數高達7.0左右，故高於微波的毫米波區域的高頻動作變得困難。若使用SiN膜，則配線的多層化變得困難。
本發明鑒於該課題而完成，其一形態的例示性目的之一在於提供一種能夠高速動作的半導體元件。 [解決課題之手段]
本發明的一形態是有關於一種半導體元件。半導體元件包括：磊晶基板，包含SiC（碳化矽）基板及形成於SiC基板上的GaN（氮化鎵）的磊晶層；多層配線結構，形成於磊晶基板的表面側，包含至少一個金屬配線層及有機系層間絕緣膜；背面金屬層，形成於磊晶基板的背面；以及至少一個通孔，形成於磊晶基板，將多層配線結構與背面金屬層之間加以連接。
根據該形態，藉由使用介電常數低（low-k）的有機系層間絕緣膜，高頻動作成為可能。
通孔的形成中的通孔蝕刻亦可在層間絕緣膜不變質的條件下進行。
蝕刻速率亦可為1 μm/min以下。蝕刻中的晶圓的冷卻溫度亦可為0℃以下。由此，可較佳地抑制蝕刻中的基板溫度的上升，可防止層間絕緣膜的變質。
亦可在通孔蝕刻後，藉由超音波清洗將附著於磊晶基板的雜質剝離。由此，可良好地形成鍍覆層。
超音波清洗亦可在純水中進行。藉由使用了純水的超音波清洗，比起使用了酸或鹼的清洗，可較佳地將含有NiF（氟化鎳）的雜質除去。
本發明的另一形態是有關於一種半導體元件的製造方法。該製造方法包括下述步驟：在包含SiC（碳化矽）基板及形成於SiC基板上的GaN（氮化鎵）的磊晶層的磊晶基板，形成電晶體單元；在磊晶基板的上側，形成包含至少一個金屬配線層及有機系層間絕緣膜的多層配線結構；對磊晶基板的背面進行研磨；自磊晶基板的背面側，在有機系層間絕緣膜不變質的條件下，施作通孔蝕刻；以及鍍覆磊晶基板的背面及通孔的側壁。
另外，將以上的構成要素的任意組合或本發明的構成要素或表達在方法、裝置等之間相互置換而成者作為本發明的形態亦有效。 [發明的效果]
根據本發明的一形態，可提供能夠高速動作的半導體元件。
以下，一面基於較佳的實施形態並參照圖式，一面對本發明進行說明。在各圖式所示的相同或同等的構成要素、構件、處理中，附上相同的符號，並適當省略重複的說明。而且，實施形態為例示而非限定發明，實施形態中記述的所有的特徵或其組合未必限於發明的本質。
本說明書中，「將構件A與構件B連接的狀態」除包含構件A與構件B以物理的方式直接連接的情況外，亦包含構件A與構件B經由不對電性連接狀態造成影響的其他構件而間接地連接的情況。 同樣地，「將構件C設置於構件A與構件B之間的狀態」除包含構件A與構件C、或者構件B與構件C直接連接的情況外，亦包含經由不對電性連接狀態造成影響的其他構件而間接地連接的情況。
圖2是實施形態的半導體元件100的剖視圖。與圖1同樣地，在半導體元件100中HEMT 200、薄膜電阻202、電容器204、焊墊206、配線208等進行積體化，而構成MMIC。
半導體元件100具備磊晶基板102、多層配線結構300、背面金屬層120、通孔122。
磊晶基板102包含SiC（碳化矽）基板及形成於SiC基板上的GaN（氮化鎵）的磊晶層。多層配線結構300形成於磊晶基板102的表面側。多層配線結構300包含至少一個金屬配線層M1～金屬配線層M4及有機系層間絕緣膜I1～有機系層間絕緣膜I3。背面金屬層120形成於磊晶基板102的背面。作為有機系層間絕緣膜，可使用聚醯亞胺、苯并環丁烯（benzocyclobutene，BCB）、氟系樹脂等介電常數為2.5～3左右的所謂的low-k材料。另外，多層配線結構300的層數不作特別限定。
進而，多層配線結構300亦可具備插入至層間絕緣膜I1及金屬配線層M1之間的保護層302。保護層302例如可由SiN（氮化矽）形成。至少一個通孔122形成於磊晶基板102。各通孔122將多層配線結構300與背面金屬層120之間加以連接。
根據圖2的半導體元件100，因層間絕緣膜I1～層間絕緣膜I3包含low-k材料，故高速動作成為可能。而且，與使用了SiN膜的現有技術相比，可視需要實現進一步的多層化。
以上為半導體元件100的基本結構。繼而，對其製造方法進行說明。
在磊晶基板102形成著HEMT 200等電晶體單元（閘極、源極、汲極）。繼而，在磊晶基板102的上側形成著多層配線結構300。此處的步驟與先前相同。
繼而，對磊晶基板102的背面進行研磨，將基板厚度設為100 μm。然後，自磊晶基板102的背面側，在有機系層間絕緣膜I1～有機系層間絕緣膜I3不變質的條件下，施作通孔蝕刻。關於不變質的條件，考慮用作層間絕緣膜I1～層間絕緣膜I3的材料的耐熱溫度等而決定即可。
本發明者等人研究後，確認藉由將磊晶基板102的基板溫度抑制為300℃以下，不會產生層間絕緣膜I1～層間絕緣膜I3的變質（裂紋、剝離、變色等），而形成通孔的開口。若考慮安全，則更佳為亦可將磊晶基板102的基板溫度抑制為250℃以下。
通常的通孔蝕刻中的蝕刻速率一般較1 μm/min更快，但本實施形態中，蝕刻速率較佳為1 μm/min以下，具體而言設為0.5 μm/min～1 μm/min左右。由此，可較佳地抑制蝕刻引起的磊晶基板102的發熱，可防止層間絕緣膜超過其耐熱溫度。
除蝕刻速率的降低外，較佳為在通孔蝕刻中，將磊晶基板102以0℃以下（例如-30℃～0℃）進行熱冷卻。由此，可防止層間絕緣膜超過其耐熱溫度。
蝕刻結束後，將磊晶基板102的背面及通孔122的側壁鍍覆（例如鍍Au（金））。由此，形成背面金屬層120及通孔122。
本發明者等人研究後，認識到在鍍覆處理前，若雜質附著於磊晶基板102的背面或通孔122的側壁，則會發生鍍覆不良。尤其，在通孔蝕刻中，若使用作為代表性的蝕刻氣體的SF6與Ni（鎳）的金屬遮罩的組合，則產生NiF（氟化鎳），該NiF（氟化鎳）會附著於磊晶基板102的背面或通孔122的側壁。
先前，雜質的清洗中一般使用酸或鹼。然而，會產生如下問題，即，存在雜質中含NiF（氟化鎳）的情況，無法利用酸或鹼將雜質完全除去的情況，鍍Au無法良好地形成。而且，即便假如可形成鍍Au，但若NiF殘留，則MMIC的高溫高濕試驗等中，當空氣中的水分與NiF反應時，氟為水溶性，會腐蝕通孔122的周邊的配線金屬等。圖3（a）是於使用了酸或鹼的清洗後形成的通孔122的剖視圖。
因此，製造方法中，藉由超音波清洗而將附著於磊晶基板102的雜質除去、剝離。理想的是較佳為將超音波清洗在50℃以上（100℃以下）的純水中進行。圖3（b）是於超音波清洗後形成的通孔122的剖視圖。如此，藉由超音波清洗，可將酸或鹼所無法除去的雜質除去，而形成良好的通孔。
而且，使用了酸或鹼的清洗中，對金屬配線造成的損傷會成為問題，但本實施形態中使用利用了純水的超音波清洗，因而可以說無損傷（damage free）。
另外，在金屬遮罩不含Ni，因此，雜質不含NiF的情況下，亦可與先前同樣地進行使用了酸或鹼的清洗。
基於實施形態對本發明進行了說明，但實施形態只不過表示本發明的原理、應用，在不脫離申請專利範圍所規定的本發明的思想範圍內，實施形態中認可許多變形例或配置的變更。
100、100R‧‧‧半導體元件
102‧‧‧磊晶基板
104、106‧‧‧層間絕緣膜
110、112、114‧‧‧配線層
120‧‧‧背面金屬層
122‧‧‧通孔
200‧‧‧HEMT
202‧‧‧薄膜電阻
204‧‧‧電容器
206‧‧‧焊墊（GND端子）
208‧‧‧配線
300‧‧‧多層配線結構
302‧‧‧保護層
M1～M4‧‧‧金屬配線層
I1～I3‧‧‧層間絕緣膜
圖1是現有的氮化物半導體元件的剖視圖。 圖2是實施形態的半導體元件的剖視圖。 圖3（a）是於使用酸或鹼的清洗後形成的通孔的剖視圖，圖3（b）是於超音波清洗後形成的通孔的剖視圖。
100‧‧‧半導體元件
102‧‧‧磊晶基板
120‧‧‧背面金屬層
122‧‧‧通孔
200‧‧‧HEMT
202‧‧‧薄膜電阻
204‧‧‧電容器
206‧‧‧焊墊
208‧‧‧配線
300‧‧‧多層配線結構
302‧‧‧保護層
M1~M4‧‧‧金屬配線層
I1~I3‧‧‧層間絕緣膜

Claims (8)

  1. 一種半導體元件，其包括： 磊晶基板，包含SiC（碳化矽）基板及形成於所述SiC基板上的GaN（氮化鎵）的磊晶層； 多層配線結構，形成於所述磊晶基板的表面側，包含至少一個金屬配線層及有機系層間絕緣膜； 背面金屬層，形成於所述磊晶基板的背面；以及 至少一個通孔，形成於所述磊晶基板，將所述多層配線結構與所述背面金屬層之間加以連接。
  2. 如申請專利範圍第1項所述的半導體元件，其中所述通孔的形成中的通孔蝕刻在所述層間絕緣膜不變質的條件下進行。
  3. 如申請專利範圍第1項或第2項所述的半導體元件，其中蝕刻速率為1 μm/min以下。
  4. 如申請專利範圍第1項或第2項所述的半導體元件，其中蝕刻中的所述磊晶基板的冷卻溫度為0℃以下。
  5. 如申請專利範圍第1項或第2項所述的半導體元件，其中在通孔蝕刻後，藉由超音波清洗將附著於所述磊晶基板的雜質剝離。
  6. 如申請專利範圍第5項所述的半導體元件，其中所述超音波清洗在純水中進行。
  7. 一種製造方法，是半導體元件的製造方法，其包括下述步驟： 在包含SiC（碳化矽）基板及形成於所述SiC基板上的GaN（氮化鎵）的磊晶層的磊晶基板，形成電晶體單元； 在所述磊晶基板的上側，形成包含至少一個金屬配線層及有機系層間絕緣膜的多層配線結構； 對所述磊晶基板的背面進行研磨； 自所述磊晶基板的背面側，在所述有機系層間絕緣膜不變質的條件下，施行通孔蝕刻；以及 鍍覆所述磊晶基板的背面及通孔的側壁。
  8. 如申請專利範圍第7項所述的製造方法，其進而包括如下步驟：在所述鍍覆之前，藉由超音波清洗將附著於所述磊晶基板的雜質剝離。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US11652043B2 (en) 2020-04-29 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with backside via

Families Citing this family (3)

* Cited by examiner, † Cited by third party
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WO2019017504A1 (ko) * 2017-07-18 2019-01-24 이상훈 웨이퍼 레벨에서 온도 및 알에프 특성 모니터링이 가능한 알에프 파워 소자
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Family Cites Families (7)

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US6563079B1 (en) * 1999-02-25 2003-05-13 Seiko Epson Corporation Method for machining work by laser beam
US6475889B1 (en) * 2000-04-11 2002-11-05 Cree, Inc. Method of forming vias in silicon carbide and resulting devices and circuits
US7476918B2 (en) * 2004-11-22 2009-01-13 Panasonic Corporation Semiconductor integrated circuit device and vehicle-mounted radar system using the same
JP2006173595A (ja) * 2004-11-22 2006-06-29 Matsushita Electric Ind Co Ltd 半導体集積回路装置及びそれを用いた車載レーダシステム
JP5117698B2 (ja) * 2006-09-27 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置
JP5888027B2 (ja) * 2012-03-14 2016-03-16 富士通株式会社 半導体装置の製造方法
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