TW201717315A - 用於成品率改善的使用銅合金的混合鍵 - Google Patents

用於成品率改善的使用銅合金的混合鍵 Download PDF

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TW201717315A
TW201717315A TW104139108A TW104139108A TW201717315A TW 201717315 A TW201717315 A TW 201717315A TW 104139108 A TW104139108 A TW 104139108A TW 104139108 A TW104139108 A TW 104139108A TW 201717315 A TW201717315 A TW 201717315A
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Taiwan
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metal
copper
layer
bond
feature
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TW104139108A
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TWI624006B (zh
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蔡喻丞
莊俊傑
王俊智
楊敦年
洪豐基
黃志輝
盧彥池
陳如曦
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台灣積體電路製造股份有限公司
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Abstract

提供使用基於混合鍵的銅合金的積體電路(IC)。積體電路包括一對垂直堆疊於彼此之上的半導體結構。半導體結構包含對應的介電層及佈置在介電層中的對應的金屬特徵。金屬特徵包含銅合金，其具有銅和次要金屬。積體電路另包括混合鍵，該混合鍵佈置在半導體結構之間的界面。混合鍵包含將介電層接合在一起的第一鍵及將金屬特徵接合在一起的第二鍵。第二鍵包含佈置於金屬特徵的銅晶粒之間的空隙且該空隙被次要金屬填充。本揭露還提供了使用基於混合鍵的銅合金將一對半導體結構接合在一起的方法。

Description

用於成品率改善的使用銅合金的混合鍵
半導體產業藉由縮小最小特徵尺寸已不斷地改善了製程能力及積體電路(ICs)的功率消耗。然而，最近幾年，製程限制使得繼續縮小最小特徵尺寸變得困難。二維(2D)積體電路垂直整合成三維積體電路(3D ICs)已成為提高製程能力及改善積體電路的功率消耗的一種潛在的方法。藉由垂直整合二維積體電路變為三維積體電路，減少了佔用空間且縮短了金屬互連距離，從而提高了製程能力且降低了功率消耗。
本發明提供一積體電路(IC)，其包括：一對堆疊於彼此之上的半導體結構，且其包含對應的介電層及佈置在介電層中的對應的金屬特徵，其中金屬特徵包含一銅合金，其具有銅和次要金屬；以及一混合鍵，混合鍵佈置在對半導體結構之間的一界面，其中混合鍵包含將介電層接合在一起的一第一鍵及將金屬特徵接合在一起的一第二鍵，其中第二鍵包含佈置於金屬特徵的銅晶粒之間的空隙且空隙被次要金屬填充。
優選地，其中金屬特徵包含銅合金的一金屬特徵，其中混合鍵另包含將介電層的其中之一接合至金屬特徵的一第三鍵，且其中第三鍵包含藉由次要金屬填充的附加空隙。
優選地，其中金屬特徵包含銅合金的一第一金屬特徵及 純銅的一第二金屬特徵，其中第一金屬特徵及第二金屬特徵藉由第二鍵接合在一起。
優選地，其中金屬特徵包含集成至一雙鑲嵌結構的一金屬特徵，雙鑲嵌結構具有直接耦合至一接墊的通路。
優選地，其中次要金屬小於金屬特徵中的原子總數或銅合金的總質量的約1%。
優選地，其中次要金屬具有一小於銅的原子量、銅中的溶解度且與銅的原子大小的差異小於約10%。
優選地，其中次要金屬是鋁、鈦、鎳、鈷、錳、鋯和鉿的其中之一。
優選地，其中對半導體結構另包含襯接金屬特徵的對應的擴散阻擋層，且擴散阻擋層經配置以防止銅從金屬特徵擴散至介電層。
優選地，其中對半導體結構是積體電路且對半導體結構在界面處鄰接，界面貫穿在界面處對應的後工序生產線(BEOL)金屬化堆疊。
本發明亦提供一種用於將一對半導體結構接合在一起的方法，方法包括：提供一對半導體結構，對半導體結構包含對應的介電層及佈置在介電層中的對應的金屬特徵，其中金屬特徵包含一銅合金，其具有銅及次要金屬；將對半導體結構接合在一起以於一界面處形成一混合鍵，界面位於對半導體結構之間，混合鍵包含將介電層接合在一起的一第一鍵及將金屬特徵接合在一起的一第二鍵，且其中第二鍵包含佈置在金屬特徵的銅晶粒之間的空隙；以及執行一退火至混合鍵以形成次要金屬沿著銅晶粒的邊界的區域，且用次要金屬填充空隙。
優選地，其中金屬特徵包含銅合金的一金屬特徵，其中 混合鍵另包含將介電層的其中之一接合至金屬特徵的一第三鍵，且其中方法另包含：執行退火以用次要金屬填充第三鍵的附加空隙。。
優選地，其中金屬特徵包含銅合金的一第一金屬特徵及純銅的一第二金屬特徵，且其中將對半導體結構接合在一起包含：用第二鍵將第一金屬特徵接合至第二金屬特徵。
優選地，其另包括：用一次要金屬形成銅合金，次要金屬具有一小於銅的原子量、銅中的溶解度且與銅的原子大小的差異小於約10%。
優選地，其另包括：用一次要金屬形成銅合金，次要金屬是鋁、鈦、鎳、鈷、錳、鋯和鉿的其中之一。
優選地，其中提供對半導體結構包括：其中提供對半導體結構包括：提供一半導體結構，其包含一介電層；執行一蝕刻至介電層以形成用於一金屬特徵的一開口；形成襯接開口的一擴散阻擋層；形成於擴散阻擋層上的襯接開口的銅合金的一晶種層；形成於晶種層上填充開口的銅的一填充層；以及執行一化學機械拋光(CMP)至擴散阻擋層、晶種層及填充層以使擴散阻擋層、晶種層及填充層的上表面與介電層的一上表面共面，且以形成一金屬特徵。
優選地，其另包括：執行化學機械拋光前，執行晶種層及填充層的一第二退火以互相擴散晶種層的銅合金與填充層的銅。。
優選地，其另包括：執行蝕刻至介電層以形成用於一雙鑲嵌結構的一對金屬特徵的開口；以及執行化學機械拋光至擴散阻擋層、晶種層及填充層以形成用於雙鑲嵌結構的對金屬特徵。
優選地，其另包括：形成氮氧化矽、氧化物或氮化矽的介電層。
優選地，其中對半導體結構是積體電路，且其中方法另包括：藉由對應的後工序生產線(BEOL)金屬化堆疊將對半導體結構接 合在一起以形成混合鍵。
本發明更提供一三維(3D)積體電路(IC)，其包括：一第一積體電路晶粒，其具有耦合至一第一金屬特徵的一第一複數個金屬互連層，其中第一金屬特徵包含具有銅及一次要金屬的一銅合金，且其中第一金屬特徵佈置在一第一層間介電(ILD)層內；一第二積體電路晶粒，其具有耦合至一第二金屬特徵的一第二複數個金屬互連層，其中第二金屬特徵包含銅，且第二金屬特徵佈置在一第二層間介電層內；其中，第一金屬特徵沿著一界面接觸第二金屬特徵，界面包含第一層間介電層和第二層間介電層。
100A、100B、200、300A、300B、500、600、700、800、900、1000、1100、1200‧‧‧截面圖
102‧‧‧上半導體結構
104‧‧‧下半導體結構
106、108、206、206’‧‧‧混合鍵
108、208‧‧‧界面
110、112、504、504’‧‧‧介電層
114、224‧‧‧介電-介電鍵
116、118‧‧‧銅特徵
120、242、242’‧‧‧銅-銅鍵
122、244‧‧‧銅-介電鍵
124、312、320、802‧‧‧邊界區域
126、128、318、318’、1010‧‧‧擴散阻擋層
130、1104‧‧‧附加鍵
132‧‧‧銅晶粒
134、1202‧‧‧沉積物
136‧‧‧空隙
202、204、202”、202''''‧‧‧積體電路
202’、202'''‧‧‧第一積體電路
204’‧‧‧第二積體電路
210、1002‧‧‧裝置區域
212、502‧‧‧半導體基板
214、216、214’、214”、214'''、214''''、216’‧‧‧金屬化堆疊
218‧‧‧層間介電層
220、220’、1004‧‧‧蝕刻停止層
222、222’、1006‧‧‧接合層
228’‧‧‧銅合金層
232‧‧‧通路
234‧‧‧接點
236‧‧‧金屬線
238、240‧‧‧接墊
238’‧‧‧第一金屬特徵
240’‧‧‧第二金屬特徵
302、304‧‧‧雙鑲嵌結構
306、308‧‧‧銅層
310‧‧‧阻擋層
314、316‧‧‧鑲嵌結構
400‧‧‧流程圖
402~420‧‧‧步驟
602‧‧‧開口
604‧‧‧光阻層
606‧‧‧蝕刻劑
702‧‧‧晶種層
704‧‧‧填充層
1102‧‧‧奈米級空隙
為協助讀者達到最佳理解效果，建議在閱讀本揭露時同時結合附圖及以下詳細說明。應該注意的是，遵照行業內標準做法，各特徵不是按比例繪製。事實上，為了清楚的討論，各特徵尺寸可以任意放大或縮小。
圖1A示出藉由基於混合鍵的銅合金接合在一起的一對半導體結構的一些實施例的截面圖。
圖1B示出藉由使用銅合金的銅-銅鍵接合在一起的金屬特徵的一些實施例的截面圖。
圖2為示出包含藉由基於混合鍵的銅合金接合在一起的一對垂直堆疊的積體電路的三維(3D)積體電路(ICs)的一些實施例的截面圖。
圖3A示出包含圖2中的三維積體電路的對應的銅特徵的一對雙鑲嵌結構的一些實施例的截面圖。
圖3B為示出包含圖2中的三維積體電路的對應的銅特徵的一對鑲嵌結構的一些實施例的截面圖。
圖4為示出使用基於混合鍵的銅合金將一對積體電路接 合成為三維積體電路的方法的一些實施例的流程圖。
圖5至圖12示出圖4中的方法在各階段的一系列截面圖。
本揭露提供了數個不同的實施例或示例，用於實現本揭露的不同特徵。為簡化本揭露，各器件和佈局的具體示例描述如下。當然，這些僅僅是示例且並不旨在有所限定。例如，本描述中的第一特徵基於第二特徵之上，跟隨第二特徵的形成可以包括一些實施例，該實施例中第一特徵和第二特徵以直接接觸形成；也可以包括一些實施例，該實施例中附加特徵形成於第一特徵和第二特徵之間，以使得該第一特徵和第二特徵以間接接觸形成。此外，本揭露可在各個示例中重複參考數值和/或字母。這種重複是為了簡化和清楚的目的，本身並不表明所討論的各個實施例和/或配置之間的關係。
此外，為便於描述本文，空間相對術語，如“在...之下”，“以下”，“下”，“上方”，“上面的”等，在本文中被使用。該術語用來描述一個元件，或與另一元件(複數個)特徵的關係，或圖中所示的特徵(複數個特徵)。空間相對術語意在包含正在使用或操作中的裝置的不同方向，除了在附圖中已描述的方向。該裝置可被另外定位(旋轉90度或沿其它方向)，並在此使用的空間相對描述符同樣可以對應地解釋。
一些三維(3D)積體電路(ICs)是藉由垂直堆疊一對二維(2D)積體電路(ICs)形成。在面對面(FTF)堆疊中，二維積體電路隨後可以使用在界面處的混合鍵貫穿對應的後工序生產線(BEOL)金屬化堆疊接合在一起，該界面位於後工序生產線金屬化堆疊之間。混合鍵包含受限於純銅的介電-介電鍵及銅-銅鍵。混合鍵的缺點是銅-銅鍵遭受來自沿著後工序生產線金屬化堆疊之間的界面及銅晶粒的邊界的空隙(即，缺陷)的影響。這些空隙減小了製造製程窗 口的大小，降低了混合鍵的可靠性，且根據晶圓接受度測試(WAT)降低了成品率。
鑒於前述，本申請涉及一種三維積體電路，其包括與基於混合鍵的銅合金接合在一起的一對垂直堆疊的二維積體電路，該三維積體電路彌補了前述的缺陷。混合鍵包括使用銅合金的介電-介電鍵及銅-銅鍵。例如，銅-銅鍵可以是純銅-銅合金鍵或銅合金-銅合金鍵。銅-銅鍵包含銅晶粒，該銅晶粒具有沿著位於二維積體電路之間的界面的空隙，且包含填充空隙的銅合金的次要金屬。有利的是，用次要金屬填充空隙增大了製程窗口的大小，提高了混合鍵的可靠性，且根據晶圓接受度測試提高了成品率。
參考圖1A，圖1A提供了藉由基於混合鍵106的銅合金接合在一起的一對半導體結構102及104的一些實施例的截面圖100A。半導體結構102及104垂直堆疊且在界面108處藉由基於混合鍵106的銅合金接合在一起，界面108位於半導體結構102及104之間，界面108例如基本上水平的界面。半導體結構102及104包括下半導體結構102及位於下半導體結構102之上的上半導體結構104。例如，半導體結構102及104對應於二維積體電路的後工序生產線金屬化堆疊。在一些實施例中，半導體結構102及104可分別包括集成晶片晶粒，其佈置在三維集成晶片(3D IC)的獨立的層。
對應於半導體結構102及104的介電層110及112在界面108處彼此鄰接以定義混合鍵106的介電-介電鍵114。在一些實施例中，介電-介電鍵114是熔接或氧化物-氧化物鍵。例如，介電層110及112可包括一個或複數個氮氧化矽、二氧化矽和氮化矽。此外，例如，介電層110及112可對應於後工序生產線金屬化堆疊的介電層，如層間介電(ILD)層和/或蝕刻停止層。
對應於半導體結構102及104的銅特徵116及118佈置於介 電層110及112中，且彼此在界面108處鄰接以定義混合鍵106的銅-銅鍵120。在一些實施例中，銅特徵116及118具有相互漸縮遠離的寬度。此外，在一些實施例中，銅特徵116及118具有約0.5微米至約2.0微米之間的寬度。例如，銅特徵116及118可具有約1.0微米或約1.5微米的寬度。甚至更多，在一些實施例中，銅特徵116及118具有不同的佔用空間和/或具有橫向彼此偏移的中心。在這樣的實施例中，銅特徵116及118在界面108處鄰接介電層110及112以定義混合鍵106的銅-介電鍵122。例如，銅特徵116及118可以對應於金屬線和/或後工序生產線金屬化堆疊的接墊。
銅特徵116及118中至少其中之一是銅合金，且在一些實施例中，銅特徵116及118兩者都是銅合金。例如，對應於下半導體結構102的下銅特徵116可以是銅合金，且對應於上半導體結構104的上銅特徵118可以是純銅。與純銅相比，銅合金具有降低的熔點、增加的阻力，且具有更小的晶粒尺寸。此外，銅合金是由銅和次要金屬構成。
相對於至少一銅合金特徵的中心區域，次要金屬沿著至少一銅合金特徵的邊界區域124具有升高的濃度。在一些實施例中，次要金屬具有一小於銅的原子量、銅中的溶解度且與銅的原子大小的差異小於約10%(如，約2%至8%)。此外，在一些實施例中，次要金屬是在銅合金中的在原子數或質量上的少數金屬。例如，次要金屬可以占小於銅合金的原子數或質量的約50%，例如小於約30%、20%、10%或1%。次要金屬可以是例如鋁、鈦、鎳、鈷、錳、鋯或鉿。正如下面將進一步描述的，次要金屬藉由填充沿著界面108的奈米級空隙有利地改善了銅-銅鍵120及與至少一銅合金特徵的例如銅-介電鍵122的任何其他的接合的強度及可靠性。
擴散阻擋層126及128襯接且將銅特徵116及118與介電層110及112分隔。擴散阻擋層126及128經配置以防止材料從銅特徵116 及118擴散至介電層110及112。擴散阻擋層126及128彼此鄰接，且鄰接介電層110及112和/或銅特徵116及118。在界面108處，擴散阻擋層126及128可垂直鄰接相鄰層以定義混合鍵106的附加鍵130。例如，擴散阻擋層126及128可包括一種或多種金屬，例如鉭、氮化鉭和氮化鈦。在一些實施例中，每一擴散阻擋層126及128包括鉭層和堆疊於鉭層上的氮化鉭層。
參考圖1B，圖1B提供了沿著界面108的銅特徵116及118的一些實施例的截面圖100B。銅特徵116及118包括具有不同尺寸和方向的銅晶粒(如，微晶)132(即，是多晶)，且包括次要金屬的沉積物134。銅晶粒132定義了銅特徵116及118的本體，且定義了沿著銅晶粒132的邊界與界面108的空隙136。在一些實施例中，至少一些銅晶粒132具有小於純銅的尺寸。例如，在銅合金區域中的銅晶粒可具有約30奈米至約40奈米的尺寸，例如約35奈米，而在純銅區域中的銅晶粒可具有於約40奈米的尺寸，例如約41奈米。
沉積物134分散遍及銅特徵116及118的本體。此外，沉積物134集中在銅特徵116及118的晶粒邊界處，且沿著晶粒邊界與界面108填充空隙136。藉由填充空隙136，銅-銅鍵120及混合鍵106的(參照圖1A)強度有利地增加。此外，用於製造混合鍵106的製程窗口增加及提高了製造產出率。
參考圖2，圖2提供了包含藉由基於混合鍵206的銅合金接合在一起的一對垂直堆疊的積體電路202及204的三維積體電路的一些實施例的截面圖200。垂直堆疊的積體電路202及204通常是二維積體電路，且藉由基於混合鍵206的銅合金於界面208處接合在一起，界面208位於垂直堆疊的積體電路202及204之間。基於混合鍵206的銅合金可以是如上述結合圖1A及圖1B的描述。垂直堆疊積體電路202及204包括對應的裝置區域210，該裝置區域210堆疊於對應的半導體基板212及對應 的後工序生產線金屬化堆疊214及216之間。裝置區域210包括電子裝置(未示出)，例如電晶體及光電二極體等。半導體基板212可以是，例如體半導體基板，例如體矽基板或矽絕緣體(SOI)基板。
對應於後工序生產線金屬化堆疊214及216的介電層堆疊在界面208處彼此鄰接以定義混合鍵206的介電-介電鍵224。介電層堆疊包括對應的層間介電層218，例如，其可以是低介電係數，例如具有小於約3.9的介電常數的電介質，或氧化物，例如二氧化矽。此外，在一些實施例中，介電層堆疊包括對應的蝕刻停止層220和/或對應的接合層222。例如，蝕刻停止層220可以佈置在層間介電層218之間。此外，例如，蝕刻停止層220可以是氮化物，例如氮氧化矽或氮化矽。接合層222佈置在界面208處，且可以是，例如氮化矽、氧氮化矽或二氧化矽。
對應於後工序生產線金屬化堆疊214及216的金屬層堆疊佈置在界電層堆疊中。金屬層堆疊包括通路232、接點234、金屬線236及接墊238及240。通路232將金屬線236連接至彼此和/或連接至接墊238及240，且接點234將金屬線236連接至裝置區域210。在一些實施例中，金屬層堆疊的金屬層在通路232或接點234之間及金屬線236或接墊238及240之間交替。此外，在一些實施例中，金屬層堆疊的金屬層藉由對應的擴散阻擋層(未示出)所襯接，其經配置以防止金屬擴散，例如銅。金屬層堆疊另包括在界面208處彼此鄰接的對應銅特徵238及240以定義混合鍵206的銅-銅鍵242。
在一些實施例中，銅特徵238及240對應於鑲嵌或雙鑲嵌結構，和/或經配置用於將垂直堆疊的積體電路202及204接合一起的重新分配層(RDLs)。此外，在一些實施例中，銅特徵238及240具有約0.5微米至2.0微米之間的寬度，和/或耦合至具有約0.1微米至1.0微米的寬度的對應的通路232。例如，下銅特徵238可具有約1微米的寬度，上銅特徵240可具有約1.5微米的寬度，且下銅特徵238及上銅特徵240的 對應的通路232可具有約0.4微米的寬度。甚至更多，在一些實施例中，銅特徵238及240具有不同的佔用空間和/或橫向彼此偏移的中心。在這樣的實施例中，銅特徵238及240可在界面208處鄰接介電層堆疊以定義混合鍵206的銅-介電鍵244。
銅特徵238及240中至少其中之一是銅合金。與純銅相比，銅合金具有降低的熔點、增加的阻力(resistance)，且具有更小的晶粒尺寸。此外，銅合金是由銅和次要金屬構成。相對於中心區域，次要金屬沿著至少一銅合金特徵的邊界區域具有升高的濃度。此外，在一些實施中，次要金屬具有一小於銅的原子量、銅中的溶解度且與銅的原子大小的差異小於約10%。在一些實施例中，次要金屬是在銅合金中的在原子數或質量上的少數金屬。次要金屬可以是例如鋁、鈦、鎳、鈷、錳、鋯或鉿。有利地是，次要金屬藉由填充沿界面208的奈米級空隙改善了銅-銅鍵242及涉及至少一銅合金特徵的例如銅-介電鍵244的任何其他的接合的強度及可靠性。
參考圖3A，圖3A提供了藉由銅-銅鍵242接合在一起的一對雙鑲嵌結構302及304的一些實施例的截面圖300A。雙鑲嵌結構302及304對應於後工序生產線金屬化堆疊214及216(參照圖2)，且其鄰接於界面208處。雙鑲嵌結構302及304包括對應的銅層306、銅層308及對應的擴散阻擋層310。銅層306、銅層308及擴散阻擋層310佈置在介電層堆疊中。銅層306及308包括對應的多對通路232及鄰接通路232的接墊238及240。銅層306及308中至少其中之一是銅合金，且沿著邊界區域312具有升高的次要金屬的濃度。擴散阻擋層310沿著通路232和接墊238及240的側壁表面不斷延伸，使得擴散阻擋層310襯接銅層306及308以將銅層306及308從介電層堆疊中分隔。
參考圖3B，圖3B提供了藉由銅-銅鍵242接合在一起的一對鑲嵌結構314及316的一些實施例的橫截面圖300B。鑲嵌結構314及 316對應後工序生產線金屬化堆疊214及216(參照圖2)，且其鄰接於界面208處。鑲嵌結構314及316包括對應的接墊238、接墊240及對應的擴散阻擋層318。接墊238、接墊240及擴散阻擋層318掩埋在介電層堆疊中。接墊238及240藉由擴散阻擋層318垂直地從相鄰的通路232被分隔，該擴散阻擋層318沿著接墊238及240的表面橫向延伸，該表面是相對於接墊238、接墊240及通路232之間的界面108的表面。接墊238及240中至少其中之一是銅合金，且沿著邊界區域320具有增加的次要金屬的濃度。擴散阻擋層318襯接接墊238及240以從介電堆疊中將接墊238及240分隔。
參考圖4，流程圖400提供了使用基於混合鍵的銅合金將一對積體電路接合成為三維積體電路的方法的一些實施例。
步驟402中，提供了包含第一後工序生產線金屬化堆疊的第一積體電路。
步驟404中，執行第一蝕刻至第一後工序生產線金屬化堆疊的第一介電層以形成開口。典型地，該開口暴露後工序生產線金屬化堆疊的金屬特徵，例如金屬線。
步驟406中，擴散阻擋層襯接開口而形成。
步驟408中，晶種層由銅合金形成，且於擴散阻擋層上襯接開口。銅合金包含銅和次要金屬。在一些實施例中，次要金屬具有一小於銅的原子量、銅中的溶解度且與銅的原子大小的差異小於約10%。
步驟410中，形成包含銅的填充層且於晶種層上填充開口。
步驟412中，執行第一積體電路的第一退火以互相擴散晶種層的銅合金與填充層的銅，從而將晶種層及填充層整合為銅合金層，該銅合金層包括銅和次要金屬。
步驟414中，執行化學機械拋光(CMP)以使銅合金層及第一介電層的上表面共面，從而形成銅合金的第一金屬特徵。
步驟416中，提供了包含第二後工序生產線金屬化堆疊的第二積體電路。第二後工序生產線金屬化堆疊包含第二介電層及包含佈置在第二介電層中的銅的第二金屬特徵。在一些實施例中，第二金屬特徵是純銅或銅合金。此外，在一些實施例中，第二金屬特徵與第一金屬特徵形成方式相同(即，為第二積體電路執行步驟402至414)。
步驟418中，第一積體電路及第二積體電路藉由第一後工序生產線金屬化堆疊及第二後工序生產線金屬化堆疊接合在一起以在第一及第二後工序生產線金屬化堆疊之間的界面形成混合鍵。該混合鍵包含位於第一介電層及第二介電層之間的介電-介電鍵，且包含第一金屬特徵和第二金屬特徵之間的銅-銅鍵。介電-介電鍵和銅-銅鍵可以使用已知的接合方法形成，例如熔接製程和/或金屬接合製程。
步驟420中，沿著位於第一金屬及第二金屬特徵之間的界面，執行第二退火至第一積體電路及第二積體電路以沉積次要金屬且以填充空隙。在一些實施例中，如當第一金屬及第二金屬特徵具有不同的佔用空間和/或橫向彼此偏移的中心時，次要金屬也沿著第一金屬特徵或第二金屬特徵及相對的介電層的之間的界面沉積且填充空隙。用次要金屬的沉積物填充空隙有利地提高了銅-銅鍵的強度及可靠性，且在一些實施例中，有利地提高了銅-介電鍵的強度及可靠性。相應地，增加了製造製程窗口的大小且根據晶圓接受度測試提高了成品率。
在替代實施例中，步驟412的第一退火被省略。在這樣的實施例中，晶種層及填充層在步驟420的第二退火期間互相擴散，從而將晶種層及填充層整合為銅合金層。
可在晶圓和/或晶粒級上執行該方法。例如，第一積體電 路可以被集成到晶圓，而第二積體電路可以單片化。作為另一示例，第一積體電路可以集成在第一晶圓中且第二積體電路可以集成至第二晶圓。在另一實施例中，第一積體電路可以被單片化且第二積體電路可以被單片化。其中當晶圓級被涉及時(如，第一積體電路或第二積體電路在執行該方法期間集成到晶圓上)，在第二退火之後可以執行單片化以單片化從該方法得到的三維積體電路。
此外，儘管所公開的方法(如，藉由流程圖400所描述的方法)被示出和描述為一系列動作或事項，應當理解的是，所示的這樣的動作或事項的順序不應解釋為限制性的。例如，一些動作可以按照不同的順序發生和/或同時與除了已經在此示出和/或描述的動作或事件的其它動作或事件發生。此外，并非要求所有所示的動作以完成一個或複數個方面或本文所描述的實施例，且本文所描述的一個或複數個動作可在一個或複數個單獨的動作和/或階段進行。
參考圖5至圖12，圖5至圖12提供了在製造的不同階段具有基於混合鍵的銅合金的三維積體電路的截面圖以說明圖4中所示方法。儘管描述圖5至圖12與圖4的方法有關，應當理解的是，圖5至圖12中所揭露的結構並不對圖4的方法有所限制，而是可單獨地作為獨立於圖4的結構。類似的，儘管圖4中的描述方法與圖5至圖12有關，應當理解的是，圖4的方法並不對圖5至圖12所揭露的結構有所限制，而是可單獨地作為獨立於圖5至圖12所揭露的結構。
圖5示出了對應於步驟402的一些實施例的截面圖。如圖所示，提供第一積體電路202’。第一積體電路202'包含垂直堆疊於後工序生產線金屬化堆疊214’與半導體基板502之間的裝置區域210。後工序生產線金屬化堆疊214’包括介電層堆疊及佈置在介電層中的金屬層堆疊。介電層堆疊包含層間介電層504，在一些實施例中，介電層堆疊包含蝕刻停止層220’和/或接合層222’。蝕刻停止層220’佈置在層間介 電層504與裝置區域210之間，且接合層222’沿著後工序生產線金屬化堆疊214’的頂面橫向延伸。金屬層堆疊包含金屬特徵，如通路232、接點、金屬線236及接墊。
圖6示出對應於步驟404的一些實施例的截面圖600。如圖所示，執行蝕刻至介電層220’、介電層222’'及介電層504(參照圖5)以形成積體電路202”的後工序生產線金屬化堆疊214’的剩餘的介電層220、介電層222及介電層504’的開口602。在一些實施例中，執行蝕刻至接合層222’(參照圖5)、最上的層間介電層504(參照圖5)及最上的蝕刻停止層220’(參照圖5)。開口602暴露金屬層堆疊的通路232，且在一些實施例中，開口602具有約0.5微米至2.0微米的寬度，例如約1.0微米。在一些實施例中，如圖所示，開口602可對應於鑲嵌結構。在替代實施例中，開口602可對應於雙鑲嵌結構。當開口602對應於雙鑲嵌結構時，開口602包括藉由通路232佔用的空間，使得圖5中通路232被省略。
用於執行蝕刻的製程可包括形成介電層220’、介電層222’及介電層504的光阻層604遮罩區域圍繞開口602。根據光阻層604的圖案，然後可以順序地將一種或多種蝕刻劑606應用到介電層220’、介電層222’及介電層504，從而定義開口602。介電層220’、介電層222’及介電層504包括蝕刻停止層220’和/或接合層222’。蝕刻劑(複數個)606通常地包含多種類型的蝕刻劑。應用蝕刻劑(複數個)606後，光阻層604可被移除。
圖7示出對應於步驟406、步驟408及步驟410的一些實施例的截面圖。如圖所示，擴散阻擋層318’襯接開口602而形成。擴散阻擋層318’是由一種或多種材料形成，且其經配置以單獨地或共同地防止銅擴散至介電層220、介電層222及介電層504’中。在一些實施例中，擴散阻擋層318’是由氮化鉭層及覆蓋在氮化鉭層上的鉭層形成。此 外，在一些實施例中，擴散阻擋層318’使用氣相沉積技術和/或共形沉積技術形成，例如物理氣相沉積(PVD)。
仍舊如圖7所示，晶種層702於擴散阻擋層318’上襯接開口602而形成。晶種層702是由銅合金形成，且在一些實施例中，晶種層702使用氣相沉積技術和/或共形沉積技術形成，例如物理氣相沉積。與純銅相比，銅合金具有降低的熔點、增加的阻力及更小的晶粒尺寸(即，微晶)。此外，銅合金是由銅和次要金屬構成。在一些實施例中，次要金屬具有一小於銅的原子量、銅中的溶解度且與銅的原子大小的差異小於約10%。次要金屬可以是例如鋁、鈦、鎳、鈷、錳、鋯或鉿。在一些實施例中，0.5%的銅合金的重量是鋁，銅合金重量的其餘部分為銅。
仍舊如圖7所示，填充層704是由銅形成，例如純銅，其填充於晶種層702上的開口602。在一些實施例中，填充層704藉由電化學沉積(ECD)形成。填充層704的形成與晶種層702及擴散阻擋層318’一起導致相對於圖6的具有擴大的後工序生產線金屬化堆疊214'''的積體電路202'''。
圖8示出對應於步驟412的一些實施例的截面圖800。如圖所示，執行第一退火至第一積體電路202'''(參照圖7)以互相擴散晶種層702的銅合金(參照圖7)與填充層704的銅(參照圖7)。第一退火導致積體電路202''''的後工序生產線金屬化堆疊214''''，積體電路202''''包括銅合金層228’。銅合金層228’集成了晶種層702及填充層704，且沿著晶種層702所在的邊界區域802具有升高的次要金屬的濃度。在一些實施例中，藉由加熱第一積體電路202'''至約攝氏300度至約攝氏400度之間執行第一退火，例如約攝氏350度或約攝氏340度至約攝氏360度。
圖9示出對應於步驟414的一些實施例的截面圖900。如圖 所示，執行化學機械拋光至擴散阻擋層318’(參照圖8)及銅合金層228’(參照圖8)。化學機械拋光使銅合金層228’、擴散阻擋層318’和介電層220、介電層222及介電層504’的堆疊的上表面共面。此外，化學機械拋光導致積體電路202''''的後工序生產線金屬化堆疊214''''，積體電路202''''包括在開口602中的一個或複數個第一金屬特徵238’，藉由剩餘擴散阻擋層318襯接。如圖所示，在對應於鑲嵌結構的開口602處，單一金屬特徵238’形成於開口602中。對應於雙鑲嵌結構的開口602處，兩個金屬特徵形成於開口602中。
圖10示出對應於步驟416的一些實施例的截面圖1000。如圖所示，提供第二積體電路204’。第二積體電路204’包含垂直堆疊於後工序生產線金屬化堆疊216’與半導體基板212之間的裝置區域1002。工序生產線金屬化堆疊216’包含介電層堆疊及佈置在介電層堆疊中的金屬層堆疊。介電層堆疊包含層間介電層218，且在一些實施例中，介電層堆疊包括蝕刻停止層1004和/或接合層1006。蝕刻停止層1004佈置在層間介電層218與裝置區域1002之間的接合層，且接合層1006沿著後工序生產線金屬化堆疊216’的頂面橫向延伸。金屬層堆疊包含通路、接點234、金屬線及接墊240’。此外，金屬層堆疊包含具有上表面基本上與介電層堆疊的上表面共面的第二金屬特徵240’。在一些實施例中，第二金屬特徵240’是藉由與第二積體電路204’執行步驟402至步驟414形成。金屬特徵234及金屬特徵240’藉由對應的擴散阻擋層1010襯接。
圖11示出對應於步驟418的一些實施例的截面圖1100。如圖所示，藉由對應的後工序生產線金屬化堆疊214'''''及216’將第一積體電路202'''''和第二積體電路204’接合以在後工序生產線金屬化堆疊214'''''及216之間的界面208處形成混合鍵206’。混合鍵206’包含在界面208處的介電-介電鍵224，該界面208位於對應於後工序生產線金 屬化堆疊214'''''及216’的介電層堆疊之間。此外，混合鍵206’包含在界面208處的銅-銅鍵242’，界面208位於第一金屬特徵238’及第二金屬特徵240’之間。在一些實施例中，例如第一金屬特徵238’及第二金屬特徵240’具有不同的佔用空間和/或橫向彼此偏移的中心，混合鍵206’包含附加鍵，例如在界面208處的銅-介電鍵244’，其位於第一金屬特徵238’或第二金屬特徵240’及介電層相對的堆疊。用於接合第一積體電路202'''''及第二積體電路204’的製程可以包括常規接合方法，例如熔接和/或金屬接合。
形成混合鍵206’後，奈米級空隙1102沿著位於第一金屬特徵238’及第二金屬特徵240’之間的界面208，且沿著位於第一金屬特徵238’及第二金屬特徵240’中的銅晶粒1104的邊界出現。空隙1102降低了銅-銅鍵242'及混合鍵206’的強度及可靠性。此外，空隙1102減小了製造製程窗口的大小，且根據晶圓接受度測試降低了成品率。為應對這些挑戰，執行第二退火以沉積空隙1102中的第一金屬特徵238’及第二金屬特徵240’的次要金屬且填充空隙1102。
圖12示出對應於步驟420的一些實施例的截面圖1200。如圖所示，於第一積體電路202'''''及第二積體電路204’上執行第二退火(參照圖11)。在一些實施例中，藉由加熱第一積體電路202'''''及第二積體電路204’至約攝氏300度與約攝氏400度之間，例如約攝氏350度。第二退火使次要金屬沉積且沿著位於第一金屬特徵238’及第二金屬特徵240’之間的界面208填充空隙1102(參照圖11)。此外，在一些實施例中，第二退火使次要金屬沉積且沿著界面208填充空隙1102，該界面208位於第一金屬特徵238’或第二金屬特徵240’及相對的介電層堆疊之間。
一旦第二退火完成，沉積物1202填充空隙1102，且在鄰接界面208的第一金屬特徵238及第二金屬特徵240的區域相對於中心 區域具有升高的次要金屬的濃度。此外，所得的混合鍵206的強度藉由填充空隙1102有利地提高。
因此，如從上述所理解的，本揭露提供了一積體電路，該積體電路包括一對垂直堆疊於彼此之上的半導體結構。該對半導體結構包含對應的介電層及佈置在該些介電層中的對應的金屬特徵。該些金屬特徵包含具有銅的一銅合金和次要金屬。該積體電路另包括一混合鍵，該混合鍵佈置在該對半導體結構之間的一界面。該混合鍵包含將該些介電層接合在一起的一第一鍵及將該些金屬特徵接合在一起的一第二鍵。該第二鍵包含佈置於該些金屬特徵的銅晶粒之間的空隙且該空隙被該次要金屬填充。
在其他的實施例中，本揭露提供了一種用於將一對半導體結構接合在一起的方法。該對半導體結構包含對應的介電層及佈置在該些介電層中的對應的金屬特徵。該些金屬特徵包含一銅合金，其具有銅及次要金屬。將該對半導體結構接合在一起以於一界面處形成一混合鍵，該界面位於該對半導體結構之間。該混合鍵包含將該些介電層接合在一起的一第一鍵及將該些金屬特徵接合在一起的一第二鍵。該第二鍵包含佈置在該些金屬特徵的銅晶粒之間的空隙。執行一退火至該混合鍵以形成該次要金屬沿著該些銅晶粒的邊界的區域，且用該次要金屬填充該些空隙。
在其他的實施例中，本揭露提供了一三維積體電路。該三維積體電路包括一第一積體電路晶粒，其具有耦合至一第一金屬特徵的一第一複數個金屬互連層，其中該第一金屬特徵佈置在一第一層間介電(ILD)層內。該第一金屬特徵包含具有銅及一次要金屬的一銅合金。該三維積體電路另包括一第二積體電路晶粒，其具有耦合至一第二金屬特徵的一第二複數個金屬互連層，該第二金屬特徵佈置在一第二層間介電層內。該第二金屬特徵包含銅。該第一金屬特徵沿著 一界面接觸該第二金屬特徵，該界面包含該第一層間介電層和第二層間介電層。
前述概述了幾個實施例的特徵，使得本領域技術人員可以更好地理解本揭露的各個方面。本領域技術人員應當理解，他們可以容易地使用本揭露作為用於實現相同目的和/或實現本文所介紹的實施例的相同的優點設計或修改其他製程和結構的基礎。本領域技術人員也應該認識到，這樣的等效構造不偏離本揭露的精神和範圍，並且它們可以在不脫離本揭露的精神和範圍的前提下進行各種改變、替換和變更。
400‧‧‧流程圖
402~420‧‧‧步驟

Claims (10)

  1. 一積體電路(IC)，包括：一對堆疊於彼此之上的半導體結構，且其包含對應的介電層及佈置在該些介電層中的對應的金屬特徵，其中該些金屬特徵包含一銅合金，其具有銅及次要金屬(secondary metal)；以及一混合鍵，該混合鍵佈置在該對半導體結構之間的一界面，其中該混合鍵包含將該些介電層接合在一起的一第一鍵及將該些金屬特徵接合在一起的一第二鍵，其中該第二鍵包含佈置於該些金屬特徵的銅晶粒之間的空隙且該空隙被該次要金屬填充。
  2. 根據請求項1所述的積體電路，其中該些金屬特徵包含該銅合金的一金屬特徵，其中該混合鍵另包含將該些介電層的其中之一接合至該金屬特徵的一第三鍵，且其中該第三鍵包含藉由該次要金屬填充的附加空隙。
  3. 根據請求項1所述的積體電路，其中該些金屬特徵包含該銅合金的一第一金屬特徵及純銅的一第二金屬特徵，其中該第一金屬特徵及該第二金屬特徵藉由該第二鍵接合在一起。
  4. 根據請求項1所述的積體電路，其中該些金屬特徵包含集成至一雙鑲嵌結構(dual damascene structure)的一金屬特徵，該雙鑲嵌結構具有直接耦合至一接墊的通路。
  5. 根據請求項1所述的積體電路，其中該次要金屬是鋁、鈦、鎳、鈷、錳、鋯和鉿的其中之一。
  6. 根據請求項1所述的積體電路，其中該對半導體結構另包含襯接該些金屬特徵的對應的擴散阻擋層，且該些擴散阻擋層經配置以防止銅從該些金屬特徵擴散至該些介電層。
  7. 一種用於將一對半導體結構接合在一起的方法，該方法包括：提供一對半導體結構，該對半導體結構包含對應的介電層及佈置在該些介電層中的對應的金屬特徵，其中該些金屬特徵包含一銅合金，其具有銅及次要金屬；將該對半導體結構接合在一起以於一界面處形成一混合鍵，該界面位於該對半導體結構之間，該混合鍵包含將該些介電層接合在一起的一第一鍵及將該些金屬特徵接合在一起的一第二鍵，且其中該第二鍵包含佈置在該些金屬特徵的銅晶粒之間的空隙；以及執行一退火至該混合鍵以形成該沿著該些銅晶粒的邊界的次要金屬的區域，且用該次要金屬填充該些空隙。
  8. 根據請求項7所述的方法，其另包括：用一次要金屬形成該銅合金，該次要金屬是鋁、鈦、鎳、鈷、錳、鋯和鉿的其中之一。
  9. 根據請求項7所述的方法，其中提供該對半導體結構包括：提供一半導體結構，其包含一介電層；執行一蝕刻至該介電層以形成用於一金屬特徵的一開口；形成襯接該開口的一擴散阻擋層；形成於該擴散阻擋層上的襯接該開口的該銅合金的一晶種層； 形成於該晶種層上填充該開口的銅的一填充層；以及執行一化學機械拋光(CMP)至該擴散阻擋層、該晶種層及該填充層以使該擴散阻擋層、該晶種層及該填充層的上表面與該介電層的一上表面共面，且以形成一金屬特徵。
  10. 一三維(3D)積體電路(IC)，包括：一第一積體電路晶粒，其具有耦合至一第一金屬特徵的一第一複數個金屬互連層，其中該第一金屬特徵包含具有銅及一次要金屬的一銅合金，且其中該第一金屬特徵佈置在一第一層間介電(ILD)層內；一第二積體電路晶粒，其具有耦合至一第二金屬特徵的一第二複數個金屬互連層，其中該第二金屬特徵包含銅，且該第二金屬特徵佈置在一第二層間介電層內；其中，該第一金屬特徵沿著一界面接觸該第二金屬特徵，該界面包含該第一層間介電層和第二層間介電層。
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