CN113889420A - 半导体元件结构及接合二基板的方法 - Google Patents

半导体元件结构及接合二基板的方法 Download PDF

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CN113889420A
CN113889420A CN202010637115.7A CN202010637115A CN113889420A CN 113889420 A CN113889420 A CN 113889420A CN 202010637115 A CN202010637115 A CN 202010637115A CN 113889420 A CN113889420 A CN 113889420A
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pad
test
substrate
ring
square
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盛志瑞
陈慧玲
郭忠幸
叶俊廷
林明哲
许荐恩
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US16/984,601 priority patent/US11557558B2/en
Publication of CN113889420A publication Critical patent/CN113889420A/zh
Priority to US18/077,191 priority patent/US20230101900A1/en
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Abstract

本发明公开一种半导体元件结构及接合二基板的方法，其中该半导体元件结构包括第一电路结构，形成在第一基板上。第一测试垫，设置在所述第一基板上。第二电路结构形成在第二基板上。第二测试垫设置在所述第二基板上。所述第一电路结构的第一连接垫是接合到所述第二电路结构的第二连接垫，且所述第一测试垫与所述第二测试垫的其一是内垫，而所述第一测试垫与所述第二测试垫的另其一是外垫，其中所述外垫环绕所述内垫。

Description

半导体元件结构及接合二基板的方法
技术领域
本发明涉及一种半导体制造技术，且特别是涉及半导体元件结构及接合二基板的方法。
背景技术
如半导体制造的技术的发展，一个整体的集成电路可以分为两个部分在两个基板上分别制造其对应部分的电路。对于个别的基板，在完成电路的制造后，其在要与另一基板的电路接合(bonding)的表面上会在预定位置形成多个连接垫(bonding pad)。其后两个基板的接合面通过封装的技术而互相接合。如此在理想的条件下，在两个基板的连接垫会互相对准接合。如此两个部分电路通过在基板表面的多个连接垫连接在一起，构成完整的集成电路。
在两个基板要接合的工艺(process)中，基板与基板之间需要进行对准后才进行接合。此对准的工艺会在基板上分别制造形成对准标记。然而用于基板与基板之间的对准，其所使用的对准标记的尺寸相对于基板上的元件结构的连接垫的尺寸是相对大很多，因此其对准的准度较宽松。如此，即使基板的对准标记能对准，但是较精细得元件结构的连接垫之间可能会有移位，造成电性的连接不良或是甚至连接失败。
如此，如果基板与基板之间产生对不准，其预期会造成两片晶片上的连接垫无法良好接合，甚至造成接合失败，同时也无法有效地对个别的电路进行检测，以确定电路接合的程度，进而能排除有接合不良的电路。
发明内容
本发明提出半导体元件结构及接合二基板的方法，至少可以有效检测出两个基板接合后，两部分电路之间的连接垫的接合状态，可以检测出接合不良的电路。
在一实施例，本发明提供一种半导体元件结构。半导体元件结构包括第一电路结构，形成在第一基板上。第一测试垫设置在所述第一基板上。第二电路结构形成在第二基板上。第二测试垫设置在所述第二基板上。所述第一电路结构的第一连接垫是接合到所述第二电路结构的第二连接垫，且所述第一测试垫与所述第二测试垫的其一是内垫，而所述第一测试垫与所述第二测试垫的另其一是外垫，其中所述外垫环绕所述内垫。
在一实施例，对于所述的半导体元件结构，其还包括第一引线电路，设置在所述第一基板上以连接到所述第一测试垫；以及第二引线电路，设置在所述第二基板上以连接到所述第二测试垫。
在一实施例，对于所述的半导体元件结构，所述第一引线电路及所述第二引线电路分别提供用于测试的测试端点。
在一实施例，对于所述的半导体元件结构，所述内垫包括至少一垫，且所述外垫包括环形垫。
在一实施例，对于所述的半导体元件结构，所述至少一垫包括圆垫、长方形垫、三角形垫、方形垫或是几何形垫，其中所述环形垫包括至少一圆环垫、长方形环垫、三角形环垫、方形环垫或是几何形环垫。
在一实施例，对于所述的半导体元件结构，所述至少一垫是具有圆形、长方形、三角形、方形或几何形的单一个垫、其中所述环形垫是均匀环绕所述单一个垫的环形状。
在一实施例，对于所述的半导体元件结构，所述内垫包括至少一第一垫，且所述外垫包括多个第二垫，构成一分布环绕所述内垫。
在一实施例，对于所述的半导体元件结构，所述至少一第一垫包括圆垫、长方形垫、三角形垫、方形垫或是几何形垫。
在一实施例，对于所述的半导体元件结构，所述至少一第一垫具有圆形、长方形、三角形、方形或几何形的单一个垫、其中所述多个第二垫是均匀环绕所述单一个垫的环形状。
在一实施例，对于所述的半导体元件结构，所述内垫是单个圆垫、单个长方形垫、单个三角形垫、单个方形垫或是单个几何形垫，其中所述外垫对应所述内垫是圆形环、长方形环、三角形环、方形环或是几何形环。
在一实施例，本发明也提供一种接合二基板的方法，包括提供第一基板，其中所述第一基板上形成有第一电路结构以及第一测试垫。提供第二基板，其中所述第二基板上形成有第二电路结构以及第二测试垫。接合所述第一电路结构的第一连接垫与所述第二电路结构的第二连接垫，同时所述第一测试垫与所述第二测试垫的其一构成内垫，而所述第一测试垫与所述第二测试垫的另其一构成外垫。在接合所述第一电路结构与所述第二电路结构后，所述外垫环绕所述内垫。
在一实施例，对于所述的接合二基板的方法，所提供的所述第一基板还包括第一引线电路连接到所述第一测试垫，其中所提供的所述第二基板还包括第二引线电路连接到所述第二测试垫。
在一实施例，对于所述的接合二基板的方法，所提供的所述第一引线电路与所述第二引线电路分别提供用于测试的测试端点。
在一实施例，对于所述的接合二基板的方法，所提供的所述内垫包括至少一垫，且所述外垫包括环形垫。
在一实施例，对于所述的接合二基板的方法，所提供的所述至少一垫包括圆垫、长方形垫、三角形垫、方形垫或是几何形垫，其中所述环形垫包括至少一圆环垫、长方形环垫、三角形环垫、方形环垫或是几何形环垫。
在一实施例，对于所述的接合二基板的方法，所述至少一垫是具有圆形、长方形、三角形、方形或几何形的单一个垫、其中所述环形垫是均匀环绕所述单一个垫的环形状。
在一实施例，对于所述的接合二基板的方法，所提供的所述内垫包括至少一第一垫，且所提供的所述外垫包括多个第二垫，构成一分布环绕所述内垫。
在一实施例，对于所述的接合二基板的方法，所述至少一第一垫包括圆垫、长方形垫、三角形垫、方形垫或是几何形垫。
在一实施例，对于所述的接合二基板的方法，所述至少一第一垫具有圆形、长方形、三角形、方形或几何形的单一个垫、其中所述多个第二垫是均匀环绕所述单一个垫的环形状。
在一实施例，对于所述的接合二基板的方法，所述内垫是单个圆垫、单个长方形垫、单个三角形垫、单个方形垫或是单个几何形垫，其中所述外垫对应所述内垫是圆形环、长方形环、三角形环、方形环或是几何形环。
附图说明
包含附图以便进一步理解本发明，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例，并与描述一起用于解释本发明的原理。
图1是一实施例基板对基板接合的剖面结构示意图；
图2是一实施例基板对基板准确接合的剖面结构示意图；
图3是一实施例基板对基板不准确接合的剖面结构示意图；
图4是一实施例对于设置有测试垫的半导体元件结构，其基板对基板接合的剖面结构示意图；
图5A是一实施例半导体元件结构的测试垫的上视示意图；
图5B是一实施例在不准确接合的情形下，半导体元件结构的测试垫的上视示意图；以及
图6到图11是一实施例测试垫的多种配置方式的示意图。
附图标号说明
50:基板
52:基板
54:内层介电层
56:连接垫
56a:插塞结构5
56b:电路
60:基板
62:基板
64:内层介电层
66:连接垫
66a:插塞结构
66b:电路
70:接合面
90:内联机结构
95:内联机结构
100:测试结构
102:测试垫
104:插塞结构
106:引线电路
110:测试垫
114:引线电路
120:局部结构
122:插塞结构
具体实施方式
本发明提出可以用于基板对基板的接合时测试结构。在基板对基板接合后可以有效检测在两个基板上的两个部分电路之间的连接垫的接合状态，如此可以有效简易检测出不良的电路。
以下提出多个实施例来说明本发明，但是本发明不限于所举的多个实施例。另外，所举的多个实施例之间也可以有适当的结合。
图1是依据一实施例，基板对基板接合的剖面结构示意图。参阅图1，在基板50中，例如以工作基板52为基础，制造完成整体电路的一部分电路。基于半导体制造技术，其依照结构而需要多层的介电层来制造与支撑，而完成预计的电路，这些介电层统称为内层介电(inter-layer dielectric，ILD)层54。此工作基板52上的部分电路是由内层介电层54包覆与支撑。部分电路会在基板50的表面形成暴露的连接垫56，用以在基板对基板接合的过程中，可以与另一个基板60的连接垫66电连接。在基板60也是根据半导体制造技术，分别以工作基板62为基础，制造完成整体电路的另一部分电路，其包含最上层的连接垫66。此部分电路也是由内层介电层64包覆与支撑。基板60与基板50分别制造完成后，在接合面70上依照接合工艺而相互接合，使得连接垫66与连接垫56电连接。
要使连接垫66与连接垫56能够连接，基板50与基板60需要对准。在基板50与基板60在非线路的区域会另外还会形成对准标记。对准标记可以包含多个标记单元，其例如沿伸于互相垂直的两个方向。如此分别形成在基板50与基板60的对准标记，可以进行二维对准，如此基板50与基板60在理想状态下，其连接垫66与连接垫56是可以对准与接合。
然而，由于对准标记的尺寸是相对于要形成的半导体元件的尺寸是大很多。即使在基板50与基板60的对准标记在对准工艺预计的准度下达到对准，而一些半导体元件的连接垫56与连接垫66之间仍存在可能的移位(shift)或甚至没有连接的情形。一般例如，电路的位置是在基板的边缘区域的电路有较大机率会有连接移位的情形。
图2是依据一实施例，基板对基板准确接合的剖面结构示意图。参阅图2，对于一对要连接的连接垫56、66，在对准的状态下是可以大面积，例如全部面积都会接触而连接。实际的电路结构，例如连接垫56、66会通过插塞(plug)结构56a、66a，与电路56b、66b连接构成在基板50、60上的电路结构。由连接垫56、66有大面积接触，其电连接状态良好，是所预期的连接状态。
图3是依据一实施例，基板对基板不准确接合的剖面结构示意图。参阅图3，由于连接垫56、66的尺寸以及相互的间隔距离是元件结构是小于对准标记的尺寸的多倍。另外对于个别电路随着在基板上的位置也可能有制造的误差。因此对于一些连接垫56、66，其之间可能存在有移位，即是不对准的状态。
如果连接垫56、66之间的接触面积不足，其可能造成连接导电性的不足，而影响电路的性能。又甚至如果连接垫56、66之间实质错开，其导致连接失败，则造成整体电路的制造不良，需要排除。
本发明至少基于能在接合的阶段可以较准去对准，且也较容易检测出可能发生连接不良的电路的考虑，提出在元件结构尺寸下，对应电路也同时形成测试结构，其至少能辅助在基板对基板接合的阶段时有效地检测出个别电路的连接状态。
图4是依据一实施例，对于设置有测试垫的半导体元件结构，其基板对基板接合的剖面结构示意图。参阅图4，半导体元件结构包括基板50与基板60。基板50上的电路结构例如包括电路56b，插塞结构56a以及连接垫56。连接垫56是要与在基板60上的连接垫66电连接。电路56b进一步通过插塞结构66a而与另一部分的电路66b连接而构成整体电路。
本发明提出测试结构100，其在基板50与基板60其形成的测试垫102、110的制造尺寸范围是与连接垫56、66的尺寸相当。测试结构100的测试垫102、110与连接垫56、66同时形成，而在接合表面70上暴露出来。
图5A是依据一实施例，半导体元件结构的测试垫的上视示意图。测试结构100可以同时参阅图4与图5A。在一实施例，测试结构100的局部结构120的上视图如图5A所示。在基板50中形成的测试垫102例如是当作外垫且在基板60中形成的测试垫110例如是当作内垫，但是内垫与外垫的形成也可以在基板60与基板50互换。
也就是，测试垫102与测试垫110的其一是当作内垫，而测试垫102与测试垫110的另其一是当作外垫。测试结构100的外垫是环绕内垫。如图4的实施例，测试垫102是外垫而测试垫110是内垫。测试垫102环绕测试垫110。
电路66b例如还包含内联机结构90，用以对外进一步连接。同时测试垫102与测试垫110有通过插塞结构104、122与引线电路114与引线电路106连接。引线电路114与引线电路106进而连接到外部测试装置，例如利用测试探针对测试垫102与测试垫110之间进行电性信号的量测，例如漏电流的量测。另外可以再配置内联机结构95与引线电路114连接，但是本发明不限于此。就一般来说，测试垫102与测试垫110例如分别提供用于测试的测试端点。
其检测的判断机制如下描述。如果连接垫56与连接垫66是良好对准的状态，则当作内垫的测试垫110会在当作外垫的测试垫102的中心区域，如此测试垫110与测试垫102之间的隔离状态是较佳的状态，相对不会产生漏电流，或是处于相对性小的漏电流值。在此检测状态下，其可以判定连接垫56与连接垫66之间的连接是良好对准。
图5B是依据一实施例，在不准确接合的情形下，半导体元件结构的测试垫的上视示意图。参阅图4与图5B，当连接垫56与连接垫66之间的连接是不是良好对准的状态时，当作内垫的测试垫110会偏离当作外垫的测试垫102的中心区域。在一实施例，测试垫110有一区域会较接近于测试垫102。在这状态下，测试垫110与测试垫102之间的隔离状态会相对减弱，因此可能产生较大的漏电流。如果测试垫110与测试垫102之间甚至完全错开时，测试垫110与测试垫102之间也可能直接碰触而处于短路状态。
由于测试垫110与测试垫102的几何配置准度是与连接垫56与连接垫66相当，因此测试垫110与测试垫102之间的接近状态可以较准确检测出连接垫56与连接垫66再接合工艺中是否有良好连接。
基于测试垫110的内垫与测试垫102的外垫的配置方式，其不限于图5A的方形配置方式。在利用内垫与外垫的检测机制下，以下更举例多种其他的变化。
图6到图11是依据一实施例，测试垫的多种配置方式的示意图。参阅图6，测试垫110与测试垫102的几何形状可以是圆形的配置方式。测试垫102维持均匀环绕测试垫110。
参阅图7，测试垫110与测试垫102的几何形状可以是长方形的配置方式。参阅图8，测试垫110与测试垫102的几何形状可以是预定的几何形状的配置，不需要是圆形、方形或是长方形。在一实施例，测试垫110与测试垫102的形状是三角形。参阅图9，在一实施例，测试垫110与测试垫102的形状也可以不需要相同。例如根据图8的变化，测试垫102是三角形而测试垫102是圆形。
参阅图10，再从测试垫110的数量来看，其也不需要是单一个，而可以是多个。在多个测试垫110配置方式下，测试垫110如图4与图5A，可以分别与引线电路114连接。在一实施例，多个测试垫110之间也可以互相电连接。多个测试垫110的数量不限于所举的四个，例如可以两个或是更多。
参阅图11，就当作外垫的测试垫102也可以是由多个几何形状的垫，其分布可以环绕测试垫110。在多个测试垫102配置方式下，测试垫102如图4与图5A，可以分别与引线电路106连接。在一实施例，多个测试垫102之间也可以互相电连接。多个测试垫110的数量不限于所举的数量，其可以环绕测试垫110，而能显示出连接垫56与连接垫66之间的对准状态的配置方式即可。
本发明从接合二基板的机制来看，也提供一种接合二基板的方法，包括提供第一基板50，其中所述第一基板50上形成有第一电路结构以及第一测试垫102。第一电路结构例如包含连接垫56、插塞结构56a及电路56b。另外也提供第二基板60，其中所述第二基板上形成有第二电路结构以及第二测试垫110。第二电路结构例如包含连接垫66、插塞结构66a及电路66b。在接合面70，接合所述第一电路结构的连接垫56与所述第二电路结构的连接垫66，同时所述第一测试垫102与所述第二测试垫110的其一构成内垫，而所述第一测试垫102与所述第二测试垫110的另其一构成外垫。在接合所述第一电路结构与所述第二电路结构后，所述外垫环绕所述内垫。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (20)

1.一种半导体元件结构，其特征在于，包括:
第一电路结构，形成在第一基板上；
第一测试垫，设置在所述第一基板上；
第二电路结构，形成在第二基板上；以及
第二测试垫，设置在所述第二基板上，
其中所述第一电路结构的第一连接垫是接合到所述第二电路结构的第二连接垫，且所述第一测试垫与所述第二测试垫的其一是内垫，而所述第一测试垫与所述第二测试垫的另其一是外垫，其中所述外垫环绕所述内垫。
2.根据权利要求1所述的半导体元件结构，其特征在于，还包括:
第一引线电路，设置在所述第一基板上以连接到所述第一测试垫；以及
第二引线电路，设置在所述第二基板上以连接到所述第二测试垫。
3.根据权利要求2所述的半导体元件结构，其特征在于，所述第一引线电路及所述第二引线电路分别提供用于测试的测试端点。
4.根据权利要求2所述的半导体元件结构，其特征在于，所述内垫包括至少一垫，且所述外垫包括环形垫。
5.根据权利要求4所述的半导体元件结构，其特征在于，所述至少一垫包括圆垫、长方形垫、三角形垫、方形垫或是几何形垫，其中所述环形垫包括至少一圆环垫、长方形环垫、三角形环垫、方形环垫或是几何形环垫。
6.根据权利要求4所述的半导体元件结构，其特征在于，所述至少一垫是具有圆形、长方形、方形或几何形的单一个垫、其中所述环形垫是均匀环绕所述单一个垫的环形状。
7.根据权利要求1所述的半导体元件结构，其特征在于，所述内垫包括至少一第一垫，且所述外垫包括多个第二垫，构成一分布环绕所述内垫。
8.根据权利要求7所述的半导体元件结构，其特征在于，所述至少一第一垫包括圆垫、长方形垫、三角形垫、方形垫或是几何形垫。
9.根据权利要求7所述的半导体元件结构，其特征在于，所述至少一第一垫具有圆形、长方形、三角形、方形或几何形的单一个垫、其中所述多个第二垫是均匀环绕所述单一个垫的环形状。
10.根据权利要求1所述的半导体元件结构，其特征在于，所述内垫是单个圆垫、单个长方形垫、单个三角形垫、单个方形垫或是单个几何形垫，其中所述外垫对应所述内垫是圆形环、长方形环、三角形环、方形环或是几何形环。
11.一种接合二基板的方法，其特征在于，包括:
提供第一基板，其中所述第一基板上形成有第一电路结构以及第一测试垫；
提供第二基板，其中所述第二基板上形成有第二电路结构以及第二测试垫；以及
接合所述第一电路结构的第一连接垫与所述第二电路结构的第二连接垫，同时所述第一测试垫与所述第二测试垫的其一构成内垫，而所述第一测试垫与所述第二测试垫的另其一构成外垫，
其中在接合所述第一电路结构与所述第二电路结构后，所述外垫环绕所述内垫。
12.根据权利要求11所述的接合二基板的方法，其特征在于，所提供的所述第一基板还包括第一引线电路连接到所述第一测试垫，其中所提供的所述第二基板还包括第二引线电路连接到所述第二测试垫。
13.根据权利要求12所述的接合二基板的方法，其特征在于，所提供的所述第一引线电路与所述第二引线电路分别提供用于测试的测试端点。
14.根据权利要求11所述的接合二基板的方法，其特征在于，所提供的所述内垫包括至少一垫，且所述外垫包括环形垫。
15.根据权利要求14所述的接合二基板的方法，其特征在于，所提供的所述至少一垫包括圆垫、长方形垫、三角形垫、方形垫或是几何形垫，其中所述环形垫包括至少一圆环垫、长方形环垫、三角形环垫、方形环垫或是几何形环垫。
16.根据权利要求14所述的接合二基板的方法，其特征在于，所述至少一垫是具有圆形、长方形、三角形、方形或几何形的单一个垫、其中所述环形垫是均匀环绕所述单一个垫的环形状。
17.根据权利要求11所述的接合二基板的方法，其特征在于，所提供的所述内垫包括至少一第一垫，且所提供的所述外垫包括多个第二垫，构成一分布环绕所述内垫。
18.根据权利要求17所述的接合二基板的方法，其特征在于，所述至少一第一垫包括圆垫、长方形垫、三角形垫、方形垫或是几何形垫。
19.根据权利要求17所述的接合二基板的方法，其特征在于，所述至少一第一垫具有圆形、长方形、三角形、方形或几何形的单一个垫、其中所述多个第二垫是均匀环绕所述单一个垫的环形状。
20.根据权利要求11所述的接合二基板的方法，其特征在于，所述内垫是单个圆垫、单个长方形垫、单个三角形垫、单个方形垫或是单个几何形垫，其中所述外垫对应所述内垫是圆形环、长方形环、三角形环、方形环或是几何形环。
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