WO2024026914A1 - 半导体结构及测量方法 - Google Patents

半导体结构及测量方法 Download PDF

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Publication number
WO2024026914A1
WO2024026914A1 PCT/CN2022/111771 CN2022111771W WO2024026914A1 WO 2024026914 A1 WO2024026914 A1 WO 2024026914A1 CN 2022111771 W CN2022111771 W CN 2022111771W WO 2024026914 A1 WO2024026914 A1 WO 2024026914A1
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test
wafer
chip
pad
test pad
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PCT/CN2022/111771
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English (en)
French (fr)
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张志伟
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a measurement method.
  • Wafer bonding technology refers to the close bonding of two polished homogeneous wafers or heterogeneous wafers through chemical and physical effects. After the wafers are bonded, the atoms at the bonding interface are reacted by external forces to form Covalent bonding makes the bonding interface achieve a specific bonding strength.
  • Wafer bonding requires controlling the accuracy of wafer-to-wafer alignment. It is usually necessary to design alignment marks at the bonding interface of two wafers. However, the current alignment marks are used to align the two bonded wafers. In an accurate process, it is impossible to accurately know the amount of offset between the two bonded wafers. This will lead to poor alignment accuracy of the two bonded wafers, which will affect the bonding process. Properties of Semiconductor Structures.
  • embodiments of the present disclosure provide a semiconductor structure, including: a first wafer having a first bonding surface; a second wafer having a third bonding surface bonded to the first bonding surface. Two bonding surfaces; at least one set of test structures, the test structure includes: a first test pad, the first bonding surface exposes the surface of the first test pad, and the first test pad has an exposed surface in the first direction.
  • first and second ends of the bonding surface Opposite first and second ends of the bonding surface; at least two second test pads, the two second test pads are spaced apart in the second wafer along the first direction, and the second bonding surface The surface of the second test pad is exposed, the area between the first test pad and the two second test pads is directly opposite, and the first second test pad is adjacent to the first end, and the second second test pad The pad is adjacent to the second end; wherein, the minimum distance between the first second test pad and the first end is the first length, and the minimum distance between the second second test pad and the second end is the first length. Two lengths, the first length is equal to the second length, and both the first length and the second length are greater than zero and less than the preset value.
  • each second test pad exposed on the second bonding surface has the same shape.
  • the first test pad further includes a third end and a fourth end arranged along the second direction
  • the test structure further includes two second test pads spaced apart along the second direction, the first The direction is different from the second direction; wherein, the third second test pad is adjacent to the third terminal, the fourth second test pad is adjacent to the fourth terminal, and the third second test pad is adjacent to the third terminal.
  • the minimum distance is the third length
  • the minimum distance between the fourth second test pad and the fourth terminal is the fourth length
  • the third length is equal to the fourth length
  • both the third length and the fourth length are greater than zero and less than default value.
  • the third length is equal to the first length.
  • the semiconductor structure has at least two sets of test structures, wherein the first direction in at least one set of test structures is the X direction, and the first direction in at least another test structure is the Y direction.
  • the first wafer has a first middle region and a first edge region
  • the second wafer has a second middle region and a second edge region
  • the first middle region is directly opposite to the second middle region
  • the first wafer has a first middle region and a first edge region.
  • the edge area is directly opposite to the second edge area
  • the first middle area and the opposite second middle area have corresponding test structures
  • the first edge area and the opposite second edge area also have corresponding test structures.
  • the first wafer includes a plurality of first chips
  • the second wafer includes a plurality of second chips
  • each first chip is directly opposite to a corresponding second chip; part of the first chip and the opposite third chip are The two chips have corresponding test structures.
  • both the first chip and the second chip have a chip middle area and a chip edge area
  • the chip middle area of the first chip is directly opposite to the chip middle area of the second chip
  • the chip edge of the first chip is directly opposite to the chip middle area of the second chip.
  • the area is directly opposite to the chip edge area of the opposite second chip, and the test structure is located in the opposite chip middle area and the opposite chip edge area.
  • both the first chip and the second chip have a chip middle area
  • the chip middle area of the first chip is directly opposite the chip middle area of the second chip
  • the first wafer also includes a chip located at the edge of the first chip.
  • the first dicing lane, the second wafer also includes a second dicing lane located at the edge of the second chip and directly opposite the corresponding first dicing lane
  • the test structure is located in the opposite central area of the chip, and is located between the first dicing lane and the corresponding first dicing lane. In the opposite second cutting lane.
  • the first test pad is made of the same material as the second test pad.
  • the semiconductor structure further includes: a first signal pad, the first bonding surface exposing the first signal pad; a second signal pad, the second bonding surface exposing the second signal pad, and The first signal pad is directly opposite to the second signal pad.
  • the width of the first signal pad exposed on the first bonding surface is the same as the width of the second signal pad exposed on the second bonding surface.
  • test structure is adjacent the first signal pad and the corresponding second signal pad.
  • embodiments of the present disclosure also provide a measurement method, which includes: providing a first wafer and a second wafer in any of the above semiconductor structures; connecting the first bonding surface with the second bonding surface. Fitting for pre-alignment; after pre-alignment, obtaining the connection status between the first test pad and the first second test pad, and obtaining the first test pad and the second second test pad.
  • the connection state between the pads wherein if the first test pad and the first second test pad are in a disconnected state, it is determined that the second wafer points to the first end at the second end relative to the first wafer There is a displacement in the direction. If the first test pad and the second second test pad are in a disconnected state, it is determined that the second wafer is displaced relative to the first wafer in the direction from the first end to the second end. .
  • the method of obtaining the connection status of the first test pad and the specific second test pad includes: measuring the contact resistance of the first test pad and the specific second test pad; if the contact resistance If the value is greater than or equal to the preset value, it is determined that the first test pad and the specific second test pad are in a disconnected state.
  • Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic structural diagram showing part of the second bonding surface of the first test pad provided by an embodiment of the present disclosure
  • Figure 4 is another structural schematic diagram showing part of the second bonding surface of the first test pad provided by an embodiment of the present disclosure
  • FIG. 5 is another structural schematic diagram showing part of the second bonding surface of the first test pad provided by an embodiment of the present disclosure
  • FIG. 6 is another structural schematic diagram showing part of the second bonding surface of the first test pad provided by an embodiment of the present disclosure
  • FIG. 7 is another structural schematic diagram showing part of the second bonding surface of the first test pad provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of a first wafer provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of the positional relationship between the test structure and the first chip on the first wafer provided by an embodiment of the present disclosure.
  • Figure 10 is a structural schematic diagram of the positional relationship between the test structure and the first chip on another first wafer provided by an embodiment of the present disclosure
  • Figure 11 is a schematic diagram of a test structure in which the second wafer is offset relative to the first wafer according to an embodiment of the present disclosure
  • Figure 12 is a schematic diagram of another test structure in which the second wafer is offset relative to the first wafer provided by an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of yet another test structure in which the second wafer is offset relative to the first wafer according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a semiconductor structure and a measurement method. Through the test structure in the semiconductor structure, it can be determined whether the second wafer and the first wafer are aligned and bonded, and the displacement of the second wafer relative to the first wafer can be obtained. Based on the displacement, the next semiconductor structure can be determined Calibrating the bonding of the first wafer and the second wafer can improve the alignment accuracy of the bonding of the first wafer and the second wafer in the semiconductor structure, thereby helping to improve the performance of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a first semiconductor structure provided by an embodiment of the present disclosure.
  • a schematic structural diagram of part of the second bonding surface of the test pad
  • Figure 4 is another schematic structural diagram showing part of the second bonding surface of the first test pad provided by an embodiment of the present disclosure
  • Figure 5 is an implementation of the present disclosure.
  • Another example provides a schematic structural diagram showing part of the second bonding surface of the first test pad
  • FIG. 6 is another example showing part of the second bonding surface of the first test pad provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a first semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 7 is another schematic structural diagram showing part of the second bonding surface of the first test pad provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of a first wafer provided by an embodiment of the present disclosure. Structural schematic diagram
  • Figure 9 is a structural schematic diagram of the positional relationship between a first on-wafer test structure and the first chip provided by an embodiment of the present disclosure
  • Figure 10 is another first on-wafer test provided by an embodiment of the present disclosure.
  • the semiconductor structure includes: a first wafer 100 having a first bonding surface; a second wafer 110 having a second bond bonded to the first bonding surface. Bonding surface; at least one set of test structures 120, the test structure 120 includes: a first test pad 101, the first bonding surface exposes the surface of the first test pad 101, and the first test pad 101 has an exposed surface in the first direction On the opposite first end 200 and the second end 201 of the first bonding surface; at least two second test pads 111, the two second test pads 111 are spaced apart along the first direction on the second wafer 110 inside, and the second bonding surface exposes the surface of the second test pad 111, the area between the first test pad 101 and the two second test pads 111 is directly opposite, and the first second test pad 111 is adjacent to the first end 200, and the second second test pad 111 is adjacent to the second end 201; wherein, the minimum distance between the first second test pad 111 and the first end 200 is the first length, and the second second test pad
  • the first test pad 101 and the second test pad 111 arranged at intervals along the first direction are used to measure the displacement of the second wafer 110 relative to the first wafer 100 in the first direction. Measure the quantity.
  • the first second test pad 111 is offset relative to the first end 200 by a first offset direction parallel to the first direction.
  • a length, the second second test pad 111 is offset by a second length relative to the second end 201 in the second offset direction, the first offset direction and the second offset direction are opposite directions, the first offset
  • the direction is also the direction in which the second second test pad 111 points to the first second test pad 111 .
  • the first end 200 and the first second test pad 111 are in a disconnected state, and the second end 201 of the first test pad 101 and the second second test pad 111 are in a connected state.
  • the first direction as the X direction, the first offset direction as the -X direction, and the second offset direction as the +X direction as an example, if the second wafer 110 is in the +X direction relative to the first wafer 100 displacement occurs, the first second test pad 111 is shifted in the +X direction relative to the first end 200, the first second test pad 111 and the first end 200 are connected to each other, and the second second test pad 111 is connected to the first end 200.
  • the second test pad 111 and the second terminal 201 are still disconnected from each other.
  • the second wafer 110 is displaced in the -X direction relative to the first wafer 100
  • the first second test pad 111 is displaced in the -X direction relative to the first end 200
  • the first second test pad 111 is disconnected from the first terminal 200
  • the second second test pad 111 is connected to the second terminal 201 .
  • the different offsets in the X direction between the first wafer 100 and the second wafer 110 cause the connection states of the second test pad 111 and the first test pad 101 to show different changing trends.
  • the connection status of the second test pad 111 and the first test pad 101 in the test structure 120 it can be determined whether the second wafer 110 and the first wafer 100 are aligned and bonded, and whether the second wafer 110 and the first wafer 100 are aligned and bonded.
  • the deflection direction when the first wafer 100 is deflected it is deflected.
  • the displacement amount of the second wafer 110 relative to the first wafer 100 can be obtained.
  • the displacement Calibrating the bonding of the first wafer 100 and the second wafer 110 in the next semiconductor structure can improve the alignment accuracy of the bonding of the first wafer 100 and the second wafer 110 in the semiconductor structure, and thus It is beneficial to improve the performance of semiconductor structures.
  • the preset value may be the smallest size that can be measured by the measuring equipment.
  • the first length and the second length are greater than zero and less than the preset value. The same length ensures that during alignment bonding, the first end 200 and the first second test pad 111 are in a disconnected state, and the second end 201 and the second second test pad 111 are also in a disconnected state.
  • the first length and the second length are the same, which is beneficial to improving the test accuracy of the test structure 120 .
  • the first wafer 100 and the second wafer 110 are wafers manufactured with semiconductor devices or circuits.
  • the wafers may be wafers manufactured with semiconductor devices or circuits using silicon as a substrate.
  • the substrate of the wafer may also be other semiconductor materials or other materials that can be used as substrates.
  • the first wafer 100 and the second wafer 110 are bonded so that the semiconductor devices or circuits in the first wafer 100 are electrically connected to the semiconductor devices or circuits in the second wafer 110 .
  • the first bonding surface of the first wafer 100 and the second bonding surface of the second wafer 110 are arranged opposite and bonded to each other.
  • the first bonding surface can expose the semiconductor device or circuit in the first wafer 100 .
  • the second bonding surface can expose the bonding pad leading out the semiconductor device or circuit in the second wafer 110 to bond the first wafer 100 to the second wafer 110.
  • the first bonding surface and the second bonding surface can The bonding surfaces are in contact, and the pads on the first bonding surface are in contact with the corresponding pads on the second bonding surface.
  • the connection between the pads and the pads is used to realize the connection between the semiconductor device or circuit in the first wafer 100 and the second bonding surface.
  • the test structure 120 in the semiconductor structure provided by the embodiment of the present disclosure is a structure used to improve the alignment accuracy of the first wafer 100 and the second wafer 110 .
  • the test structure 120 includes a first test pad 101 and at least two second test pads 111 spaced apart along a first direction.
  • the first direction can be any direction parallel to the surface of the first wafer 100 or the second wafer 110 .
  • direction if the first direction is the X direction, the two ends of the first test pad 101 in the first direction and the corresponding two second test pads 111 arranged in the first direction can test the second wafer 110
  • the offset occurring in the X direction relative to the first wafer 100 is measured.
  • the first direction can be defined according to the testing requirements to achieve testing of the second wafer 110 relative to the first wafer 110 in any direction parallel to the surface of the first wafer 100 or parallel to the surface of the second wafer 110 .
  • the displacement of wafer 100 is measured.
  • the second wafer 110 is offset relative to the first wafer 100 in the The displacement occurs in the +X direction.
  • Another situation is that the second wafer 110 is displaced in the -X direction relative to the first wafer 100.
  • a set of tests is set in the X direction.
  • the structure 120 can measure the two displacements of the second wafer 110 relative to the first wafer 100 in the X direction.
  • test structure 120 can measure more offset directions, avoiding the need to reserve a large installation area for the test structure 120 in the first wafer 100 and the second wafer 110, which is beneficial to reducing the manufacturing difficulty of the test structure 120. .
  • both the first wafer 100 and the second wafer 110 include an insulating layer 130 , and the material of the insulating layer 130 may be silicon oxide or silicon nitride.
  • the first bonding surface exposes the insulating layer 130 of the first wafer 100, and the first test pad 101 is located in the insulating layer 130.
  • the material of the first test pad 101 is a conductive material, such as copper, tungsten or aluminum.
  • the second bonding surface exposes the insulating layer 130 of the second wafer 110, and the second test pad 111 is located in the insulating layer 130 of the second wafer 110.
  • the material of the second test pad 111 is also a conductive material, for example, it can be Copper, tungsten or aluminum.
  • the first test pad 101 is made of the same material as the second test pad 111 . In this way, it is beneficial to use the same preparation process and the same source material to form the first test pad 101 and the second test pad 111, which is beneficial to reducing the preparation difficulty of the first test pad 101 and the second test pad 111.
  • each second test pad 111 exposed on the second bonding surface has the same shape.
  • Forming the second test pad 111 usually requires the use of a photolithography process and an etching process.
  • the photolithography process is used to define the shape and size of the second test pad 111.
  • the incident light used for the exposure is Light will produce undesired reflected light or refracted light.
  • the undesired reflected light or refracted light may cause undesired exposure of the photoresist.
  • the formed photoresist pattern will be different from the preset photoresist pattern. Has errors.
  • the intensity and direction of the reflected light or refracted light are also related to the preset photoresist pattern. If the preset photoresist pattern is different, the error of the photolithography process will also be different. Therefore, if each second If the shapes of the test pads 111 are different, the preset photoresist patterns related to the second test pads 111 are also different. The different preset photoresist patterns may cause different second test pads 111 to have different shapes. Different photolithography errors lead to different setting errors between different second test pads 111, which affects the test accuracy of the second test pads 111. Therefore, configuring each second test pad 111 exposed on the second bonding surface to have the same shape can avoid different dimensional errors between second test pads 111 of different shapes due to different photolithography errors. , which is conducive to reducing the dimensional error between different second test pads 111, and thus is conducive to using the second test pad 111 with smaller dimensional error to more accurately measure the alignment accuracy of wafer bonding.
  • the shape of the first test pad 101 exposed on the first bonding surface is square; the shape of the second test pad 111 exposed on the second bonding surface is also square, and the square shape
  • the length direction of the first test pad 101 is parallel to the first direction and the width direction is perpendicular to the first direction.
  • the length direction of the square second test pad 111 is parallel to the first direction and the width direction is perpendicular to the first direction.
  • the square area of the overlapping portion of the soldering pad 111 and the first testing pad 101 has a linear relationship with the displacement of the second testing pad 111 relative to the first testing pad 101 in the first direction. In this way, it is easier to adjust the second testing pad 111 according to the second testing pad 101 .
  • the square area of the overlapping portion of the test pad 111 and the first test pad 101 can deduce the displacement amount of the second wafer 110 relative to the first wafer 100 , which is helpful to reduce the difficulty of measuring the displacement amount.
  • the width of the second test pad 111 may be the Y direction.
  • the width of the first test pad 101 is the same as the width of the second test pad 111, when the first test pad 101 is relative to the second test pad 111, when the pad 111 is displaced in the X direction, and the first test pad 101 is also displaced in the Y direction relative to the second test pad 111, the overlapping area of the first test pad 101 and the second test pad 111 is equal to The displacement amount of the second test pad 111 relative to the first test pad 101 in the first direction does not have a relatively simple linear relationship. The width of the overlapping direction obtains the displacement.
  • setting the width of the first test pad 101 to be smaller than the width of the second test pad 111 is beneficial to the first test pad 101 and the second test pad 111 according to the width.
  • the overlapping area of the test pads 111 determines the amount of displacement of the first wafer 100 relative to the second wafer 110 , thereby helping to reduce the difficulty of testing the displacement.
  • the width of the first test pad 101 exposed on the first bonding surface may also be larger than the width of the second test pad 101 exposed on the second bonding surface.
  • the width of the test pad 111 in this way, the displacement amount of the first wafer 100 relative to the second wafer 110 can also be determined based on the overlapping area of the first test pad 101 and the second test pad 111, which is beneficial to Reduce the difficulty of testing displacement.
  • the shape of the first test pad 101 exposed on the first bonding surface or the shape of the second test pad 111 exposed on the second bonding surface may also be circular or other shapes.
  • the semiconductor structure may have at least two groups of test structures 120 , wherein the first direction in at least one group of test structures 120 is the X direction, and the first direction in at least another group of test structures 120 is the X direction.
  • the first direction is the Y direction.
  • the Y direction and the The first direction is the Y direction
  • the displacement of the second wafer 110 relative to the first wafer 100 in the X direction is measured using the test structure 120 whose first direction is the X direction.
  • the displacement of the second wafer 110 relative to the first wafer 100 in the Y direction can be measured in multiple directions, which is conducive to measurement in multiple directions.
  • the test structure 120 is used to improve the alignment accuracy of the first wafer 100 and the second wafer 110 in two directions.
  • the Y direction is perpendicular to the The displacement occurring in the surface direction of a wafer 100 is measured. In this way, it is beneficial to use the test structure 120 to improve the alignment accuracy of the first wafer 100 and the second wafer 110 .
  • the first test pad 101 further includes a third end 202 and a fourth end 203 arranged along the second direction
  • the test structure 120 further includes a third end 202 and a fourth end 203 arranged along the second direction.
  • Two second test pads 111, the first direction and the second direction are different; among them, the third second test pad 111 is adjacent to the third end 202, and the fourth second test pad 111 is adjacent to the fourth end 203 , the minimum distance between the third second test pad 111 and the third end 202 is the third length, the minimum distance between the fourth second test pad 111 and the fourth end 203 is the fourth length, The third length is equal to the fourth length, and both the third length and the fourth length are greater than zero and less than the preset value.
  • the second crystal can be determined.
  • the state in which the circle 110 is offset relative to the first wafer 100 in the second direction, and the amount of displacement of the second wafer 110 relative to the first wafer 100 in the second direction are determined using a set of test structures 120
  • the displacement of the second wafer 110 relative to the first wafer 100 can be measured in multiple directions, without the need to install more test structures 120 in the first wafer 100 and the second wafer 110, thus avoiding Reserve a larger installation area for the test structure 120 in the first wafer 100 and the second wafer 110 , which is helpful to reduce the manufacturing difficulty of the test structure 120 .
  • the Y direction is perpendicular to the X direction.
  • the third length is equal to the first length. If the third length is longer and the first length is shorter, the test structure 120 can measure the displacement only when the second wafer 110 has a larger displacement in the first direction relative to the first wafer 100. When the second wafer 110 has a smaller displacement in the second direction relative to the first wafer 100, the test structure 120 can measure the displacement, causing the test structure 120 to measure in different directions. The positional relationship between the first wafer 100 and the second wafer 110 has an error. Similarly, if the first length is longer and the third length is shorter, the positional relationship between the first wafer 100 and the second wafer 110 measured in different directions by the test structure 120 will also have errors. Therefore, the first When the wafer 100 and the second wafer 110 are aligned and bonded, the first length and the second length are the same, which is beneficial to improving the test accuracy of the test structure 120 .
  • the maximum lengths of the first to second ends 200 to 201 are the same as the maximum lengths of the third to fourth ends 202 to 203 . In this way, it is helpful to reduce the difficulty of setting the first test pad 101 and the second test pad 111 .
  • the width of the first test pad 101 may be 100 nm to 10000 nm, for example, it may be 250 nm, 450 nm, 500 nm, or 5400 nm. , 8900nm, etc.
  • the width of the second test pad 111 may be 100 nm to 10000 nm, for example, it may be 100 nm, 1500 nm, 2500 nm, 4500 nm, 9500 nm, etc.
  • the widths of the first test pad 101 and the second test pad 111 in the first direction can be reasonably set according to the sizes of the first wafer 100 and the second wafer 110 in the first direction. .
  • the first direction as the 500nm, 800nm, etc.
  • the length of the second test pad 111 is 100nm ⁇ 1000nm, for example, it can be 450nm, 360nm, 480nm, 550nm, 760nm, etc.
  • the width of the first test pad 101 and the second test pad 111 in the first direction can be reasonably set according to the dimensions of the first wafer 100 and the second wafer 110 perpendicular to the first direction.
  • the semiconductor structure further includes: a first signal pad 102 , the first bonding surface exposing the first signal pad 102 ; a second signal pad 112 , the second bonding surface exposing The second signal pad 112 is opposite to the first signal pad 102 and the second signal pad 112 .
  • the first signal pad 102 may be a pad used to provide a test signal for a semiconductor device or circuit in the first wafer 100
  • the second signal pad 112 may be a pad used to provide a test signal for a semiconductor device or circuit in the second wafer 110 .
  • the circuit provides pads for test signals, and the opposite first signal pads 102 and second signal pads 112 are connected to each other, so that the semiconductor devices or circuits in the first wafer 100 are connected to the semiconductor devices or circuits in the second wafer 110
  • the circuits share one signal lead, which is beneficial to reducing the complexity of lead layout in the semiconductor structure and reducing the manufacturing difficulty of the semiconductor structure.
  • the width of the first signal pad 102 exposed on the first bonding surface is the same as the width of the second signal pad 112 exposed on the second bonding surface.
  • the first direction as the X direction as an example, the first signal pad 102 and the second signal pad 112 having the same width and facing each other in the first direction can be provided as the first test pad 101 and the second test pad 111
  • the positioning marks in the process are thus conducive to accurately setting the first test pad 101 in the first wafer 100 using the existing pads in the semiconductor structure, and accurately setting the second test pad 101 in the second wafer 110
  • the pad 111 avoids setting additional positioning marks, which is beneficial to reducing the manufacturing difficulty of the first test pad 101 and the second test pad 111 .
  • test structure 120 is adjacent first signal pad 102 and corresponding second signal pad 112 .
  • the first signal pad 102 and the second signal pad 112 can also be pads that provide operating signals for devices or circuits in the semiconductor structure.
  • the test structure 120 is disposed adjacent to the first signal pad 102 and facing the first signal.
  • the position of the pad 102 can be measured by using the test structure 120 to measure the alignment state of the first signal pad 102 and the second signal pad 112 , and using the test structure 120 to obtain the relative position of the second signal pad 112 to the first signal.
  • the displacement amount of the pad 102 is offset, and according to the displacement amount, the first signal pad 102 and the opposite second signal pad 112 are accurately aligned and bonded.
  • the aligned first signal pad 102 and The connecting area of the second signal pad 112 is larger, which is conducive to improving the conduction speed of the test signal or the working signal through the first test pad 101 and the second test pad 111, which is conducive to improving the conduction speed of the test signal in the semiconductor structure.
  • the first signal pad 102 is also disposed within the insulating layer 130 of the first wafer 100
  • the second signal pad 112 is also disposed within the insulating layer 130 of the second wafer 110
  • the first signal pad 102 and the second signal pad 112 are made of the same material, and the material of the first signal pad 102 or the second signal pad 112 may include copper, tungsten or aluminum.
  • the surface of the first wafer 100 opposite the first bonding surface also exposes the first signal pad 102
  • the surface of the second wafer 110 opposite the second bonding surface also exposes the second signal pad 112. In this way, it is advantageous to utilize the exposed first signal pad 102 to provide electrical signals to the first signal pad 102 , and to utilize the exposed second signal pad 112 to provide electrical signals to the second signal pad 112 .
  • the first wafer 100 has a first middle region 103 and a first edge region 104
  • the second wafer 110 has a second middle region and a second edge region
  • the first middle region 103 and The second middle area is directly opposite
  • the first edge area 104 is directly opposite to the second edge area
  • the first middle area 103 and the opposite second middle area have corresponding test structures 120
  • the first edge area 104 and the opposite second edge Zones also have corresponding test structures.
  • the first middle region 103 is a region located near the center of the first wafer 100
  • the first edge region 104 is a region close to the edge of the first wafer 100
  • the second middle area is an area located near the center of the second wafer 110
  • the second edge area is an area close to the edge of the second wafer 110 .
  • the center of the first wafer 100 and the center of the second wafer 110 are aligned and measured using the test structure 120 in the middle of the first wafer 100 and the second wafer 110.
  • the test structure 120 on the edge of the second wafer 110 is used to align and measure the edge of the first wafer 100 and the edge of the second wafer 110. By aligning the center and the edge, the first wafer 100 and the edge can be measured.
  • the entire second wafer 110 is aligned and measured, which facilitates accurate measurement of the bonding between the first wafer 100 and the second wafer 110 using a limited number of test structures 120 .
  • the second middle region and the second edge region of the second wafer 110 are similar to the first wafer 100, and the second middle region and the second edge region of the second wafer 110 are not shown.
  • first middle region 103 and the second opposite middle region are provided with multiple sets of test structures 120
  • first edge region 104 and the second opposite edge region are also provided with multiple sets of test structures 120 .
  • More test structures 120 are beneficial to improving the alignment accuracy of the first wafer 100 and the second wafer 110 .
  • the first wafer 100 includes a plurality of first chips 105
  • the second wafer 110 includes a plurality of second chips
  • each first chip 105 is associated with a corresponding second chip.
  • Opposite; part of the first chip 105 and the opposite second chip have corresponding test structures 120 .
  • test structure 120 not only can be used to measure the overall displacement of the second wafer 110 relative to the first wafer 100, but also the displacement of the second chip relative to the corresponding first chip 105 can be measured, which is beneficial to the use of testing.
  • the structure 120 accurately obtains the displacement between the second chip and the first chip 105, thereby achieving accurate alignment and bonding of the second chip and the first chip 105, and aligning the first chip 105 and the second chip with higher accuracy. It is beneficial to improve the performance of semiconductor structures.
  • the arrangement of the second chip in the second wafer 110 is similar to that of the first chip 105 in the first wafer 100. Therefore, the structure of the second chip in the second wafer 110 is not shown.
  • the first chip 105 and the second chip both have a chip middle area and a chip edge area, and the chip middle area of the first chip 105 is directly opposite to the chip middle area of the second chip, The chip edge area of the first chip 105 is directly opposite to the opposite chip edge area of the second chip, and the test structure 120 is located in the opposite chip middle area and the opposite chip edge area.
  • the chip middle area is an area located near the center of the first chip 105 or the second chip
  • the chip edge area is an area close to the edge of the first chip 105 or the second chip.
  • at least two sets of corresponding test structures 120 can be provided in the first chip 105 and the facing second chip.
  • the two sets of test structures 120 may be located in the middle area of the chip and the edge area of the chip respectively.
  • test structure 120 in the middle area of the chip can be used to measure the alignment state between the middle part of the first chip 105 and the middle part of the second chip, and then the test structure 120 in the edge area of the chip can be used to measure the alignment state between the edge of the first chip 105 and the second chip. Measuring the alignment state of the edges of the two chips facilitates the use of the test structure 120 to accurately measure the alignment state of the bonding between the first chip 105 and the facing second chip.
  • both the first chip 105 and the second chip have a chip middle area, and the chip middle area of the first chip 105 is directly opposite to the chip middle area of the second chip.
  • the first wafer 100 also includes a first dicing lane 106 located at the edge of the first chip 105.
  • the second wafer 110 also includes a second dicing lane located at the edge of the second chip and directly opposite the corresponding first dicing lane 106.
  • the test structure 120 is located directly opposite the first dicing lane 106.
  • the central area of the chip is located in the first dicing lane 106 and the opposite second dicing lane.
  • the middle area of the chip is an area located near the center of the first chip 105 or the second chip.
  • test structure 120 in the middle area of the chip can be used to measure the alignment state of the middle part of the first chip 105 and the middle part of the second chip, and then the test structures in the first dicing lane 106 and the second dicing lane at the edge of the chip can be measured. 120 measures the alignment state of the edge of the first chip 105 and the edge of the second chip.
  • the test structure 120 is the test structure 120 shown in FIGS. 3 to 5 , that is, a set of test structures 120 only tests the second wafer 110 relative to the first wafer 100 in the first step. The direction deviation is tested. For example, if the alignment of the first chip 105 and the middle part of the second chip facing each other is measured for bonding, the middle part of the first chip 105 and the middle part of the second chip facing each other can be measured. At least two sets of test structures 120 are provided, and the first directions in the two sets of test structures 120 can be respectively the X direction and the Y direction that are perpendicular to each other.
  • the test structure 120 for measuring the displacement in various directions of the edge of the first chip 105 and the opposite second chip is also similar, and can be set at the edge of the first chip 105 and the opposite edge of the second chip.
  • the first directions in the two sets of test structures 120 may be the X direction and the Y direction that are perpendicular to each other respectively.
  • the spacing distance between adjacent test structures 120 may be smaller.
  • a first chip 105 and an opposite second chip have multiple adjacent sets of test structures 120 .
  • the distance between adjacent test structures 120 can also be relatively far.
  • a first chip 105 and an opposite second chip only have one set of adjacent test structures 120 .
  • the semiconductor structure includes a first wafer 100 and a second wafer 110 that are bonded to each other, and the first bonding surface of the first wafer 100 and the second bond of the second wafer 110
  • the first wafer 100 and the second wafer 110 that are bonded to each other have a test structure 120 for measuring the alignment deviation of the first wafer 100 and the second wafer 110.
  • the test structure 120 includes an exposed The first test pad 101 on the first bonding surface and at least two second test pads 111 exposed on the second bonding surface, both ends of the first test pad 101 and the two second test pads 111 They are all arranged at intervals along the first direction and used to measure the displacement of the second wafer 110 relative to the first wafer 100 in the first direction.
  • the area between the first test pad 101 and the two second test pads 111 is directly opposite, the first end 200 of the first test pad 101 corresponds to the first second test pad 111, and the first The second end 201 of the test pad 101 corresponds to the second second test pad 111, and the first second test pad 111 is offset relative to the first end 200 in a first offset direction parallel to the first direction.
  • the first length, the second second test pad 111 is offset by the second length relative to the second end 201 in the second offset direction, the first offset direction and the second offset direction are opposite directions, the first offset direction
  • the moving direction is also the direction in which the second second test pad 111 points to the first second test pad 111 .
  • the first length and the second length are both less than a preset value, and the preset value can be the smallest size that can be measured by the measuring equipment.
  • the preset value can be the smallest size that can be measured by the measuring equipment.
  • the test structure 120 it can be determined whether the second wafer 110 and the first wafer 100 are aligned and bonded, and the displacement of the second wafer 110 relative to the first wafer 100 can be obtained. According to the displacement, the next step can be determined. Calibrating the bonding of the first wafer 100 and the second wafer 110 in the semiconductor structure can improve the alignment accuracy of the bonding of the first wafer 100 and the second wafer 110 in the semiconductor structure, thereby helping to improve the semiconductor structure performance.
  • the embodiments of the present disclosure also provide a measurement method, which can measure the semiconductor structure provided in the above embodiments. It should be noted that for parts that are the same as or corresponding to the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments and will not be described in detail below.
  • FIG. 11 is a schematic diagram of a test structure in which a second wafer is offset relative to the first wafer provided by an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of another second wafer relative to the first wafer provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a test structure in which the second wafer is shifted relative to the first wafer provided by an embodiment of the present disclosure.
  • the measurement method includes: providing the first wafer 100 and the second wafer 110 in any of the above semiconductor structures; connecting the first bonding surface with the second The bonding surfaces are bonded together for pre-alignment; after pre-alignment, the connection status between the first test pad 101 and the first second test pad 111 is obtained, and the connection status between the first test pad 101 and the first second test pad 111 is obtained.
  • the connection state between the second test pads 111 If the first test pad 101 and the first second test pad 111 are in a disconnected state, it is determined that the second wafer 110 is relative to the first test pad 111.
  • the wafer 100 is displaced in the direction from the second end 201 to the first end 200.
  • first test pad 101 and the second second test pad 111 are in a disconnected state, it is determined that the second wafer 110 is relative to the second test pad 111.
  • the first wafer 100 is displaced in the direction from the first end 200 to the second end 201 .
  • the first test pad 101 in the test structure 120 also includes a third end 202 and a fourth end 203.
  • the first direction is the X direction
  • the first offset direction is -X direction
  • the second offset direction is the +X direction
  • the second offset direction is the Y direction
  • the third offset direction is the -Y direction
  • the fourth offset direction is the +Y direction.
  • the third offset direction and the The fourth offset direction is an opposite direction parallel to the second direction
  • the third offset direction is also the direction in which the fourth second test pad 111 points to the third second test pad 111 .
  • first terminal 200 and the first second test pad 111 are in a connected state, the second terminal 201 and the second second test pad 111 are in a disconnected state, and the fourth terminal 203 and the fourth second test pad 111 are in a disconnected state.
  • the pad 111 is in a connected state, and the third end 202 and the third second test pad 111 are in a disconnected state, then it is determined that the second wafer 110 is offset in the +X direction relative to the first wafer 100, Furthermore, the second wafer 110 is also offset in the ⁇ Y direction relative to the first wafer 100 .
  • the displacement amount of the second wafer 110 relative to the first wafer 100 is analyzed and obtained, which is beneficial to the analysis based on the displacement amount.
  • the bonding of the next first wafer 100 and the bonded second wafer 110 is calibrated so that the first wafer 100 and the second wafer 110 have a smaller offset, which is beneficial to improving the performance of the semiconductor structure. .
  • the method of obtaining the connection status between the first test pad 101 and the specific second test pad 111 includes: measuring the contact resistance between the first test pad 101 and the specific second test pad 111; if If the resistance value of the contact resistance is greater than or equal to the preset value, it is determined that the first test pad 101 and the specific second test pad 111 are in a disconnected state.
  • wires may be provided to lead out the first test pad 101 and the second test pad 111 , and provide test current to the first test pad 101 and the second test pad 111 through the wires, as shown in FIG. 7 Taking this embodiment as an example, when the first wafer 100 and the second wafer 110 are aligned and bonded, the resistance values of the contact resistances of the first test pad 101 and the four second test pads 111 are all infinite, then The first test pad 101 and the four second test pads 111 are all in a disconnected state.
  • the contact resistance of the first test pad 101 and the first second test pad 111 in the test structure 120 is a measurable specific resistance value
  • the first test pad The contact resistance of the pad 101 and the fourth second test pad 111 is also a measurable specific resistance value, and the contact resistances of the first test pad 101 and the remaining two second test pads 111 are infinite. is large, then the first test pad 101 and the first second test pad 111 are in a connected state, and the first test pad 101 and the fourth second test pad 111 are also in a connected state.
  • the first test pad 101 The first test pad 101 and the third second test pad 111 are also in a disconnected state.
  • the facing area of the first test pad 101 and the corresponding second test pad 111 can also be measured by infrared measurement.
  • the displacement state of the second wafer 110 relative to the first wafer 100 can be determined, and By measuring the overlapping area of the first test pad 101 and the corresponding second test pad 111, the displacement of the second wafer 110 relative to the first wafer 100 can be determined, and then the measured displacement can be used to determine the next step.
  • the bonding of the first wafer 100 and the bonded second wafer 110 is calibrated so that the first wafer 100 and the second wafer 110 have a smaller offset, which is beneficial to improving the performance of the semiconductor structure.

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Abstract

一种半导体结构以及一种测量方法，其中半导体结构包括：第一晶圆（100）、第二晶圆（110）以及至少一组测试结构（120），测试结构（120）包括：第一测试焊盘（101）和至少两个第二测试焊盘（111），两个第二测试焊盘（111）沿第一方向间隔排布于第二晶圆（110）内，且第二键合面暴露出第二测试焊盘（111）表面，第一测试焊盘（101）与两个第二测试焊盘（111）之间间隔的区域正对，且第一个第二测试焊盘（111）邻近第一端（200），第二个第二测试焊盘（111）邻近第二端（201）；其中，第一个第二测试焊盘（111）与第一端（200）之间的最小距离为第一长度，第二个第二测试焊盘（111）与第二端（201）之间的最小距离为第二长度，第一长度等于第二长度，且第一长度与第二长度均大于零且小于预设值。

Description

半导体结构及测量方法
交叉引用
本公开要求于2022年08月01日递交的名称为“半导体结构及测量方法”、申请号为202210918369.5的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉半导体技术领域，特别涉及一种半导体结构及一种测量方法。
背景技术
晶圆键合技术是指通过化学和物理作用将两片已抛光的同质晶圆或异质晶圆紧密地接合起来，晶圆接合后，相接合界面的原子受到外力的作用而产生反应形成共价键结合成一体，使接合界面达到特定的键合强度。
晶圆键合需控制晶圆与晶圆对准的准确度，通常需要在两片晶圆的接合界面设计对准标记，但是利用目前的对准标记对相键合的两个晶圆进行对准的过程，无法准确的得知相键合的两个晶圆之间发生偏移的位移量，如此，会导致相键合的两个晶圆的对准精度差，进而影响键合后的半导体结构的性能。
发明内容
本公开实施例一方面提供一种半导体结构，包括：第一晶圆，第一晶圆具有第一键合面；第二晶圆，第二晶圆具有与第一键合面相键合的第二键合面；至少一组测试结构，测试结构包括：第一测试焊盘，第一键合面暴露出第一测试焊盘表面，且第一测试焊盘在第一方向具有露出于第一键合面的相对的第一端和第二端；至少两个第二测试焊盘，两个第二测试焊盘沿第一方向间隔排布于第二晶圆内，且第二键合面暴露出第二测试焊盘表面，第一测试焊盘与两个第二测试焊盘之间间隔的区域正对，且第一个第二测试焊盘邻近第一端，第二个第二测试焊盘邻近第二端；其中，第一个第二测试焊盘与第一端之间的最小距离为第一长度，第二个第二测试焊盘与第二端之间的最小距离为第二长度，第一长度等于第二长度，且第一长度与第二长度均大于零且小于预设值。
在一些实施例中，第二键合面露出的每一第二测试焊盘的形状相同。
在一些实施例中，第一测试焊盘还包括沿第二方向排布的第三端和第四端，测试结构还包括沿第二方向间隔排布的两个第二测试焊盘，第一方向与第二方向不同；其中，第三 个第二测试焊盘邻近第三端，第四个第二测试焊盘邻近第四端，第三个第二测试焊盘与第三端之间的最小距离为第三长度，第四个第二测试焊盘与第四端之间的最小距离为第四长度，第三长度等于第四长度，且第三长度与第四长度均大于零且小于预设值。
在一些实施例中，第三长度等于第一长度。
在一些实施例中，半导体结构具有至少两组测试结构，其中，至少一组测试结构中的第一方向为X方向，至少另一种测试结构中的第一方向为Y方向。
在一些实施例中，第一晶圆具有第一中部区域以及第一边缘区域，第二晶圆具有第二中部区域以及第二边缘区域，第一中部区域与第二中部区域正对，第一边缘区域与第二边缘区域正对，第一中部区域和正对的第二中部区域具有相应的测试结构，第一边缘区域和正对的第二边缘区域也具有相应的测试结构。
在一些实施例中，第一晶圆包括多个第一芯片，第二晶圆包括多个第二芯片，每一第一芯片与相应的第二芯片正对；部分第一芯片和正对的第二芯片具有相应的测试结构。
在一些实施例中，第一芯片与第二芯片均具有芯片中部区域和芯片边缘区域，且第一芯片的芯片中部区域和正对的第二芯片的芯片中部区域正对，第一芯片的芯片边缘区域和正对的第二芯片的芯片边缘区域正对，测试结构位于正对的芯片中部区域以及正对的芯片边缘区域。
在一些实施例中，第一芯片与第二芯片均具有芯片中部区域，第一芯片的芯片中部区域和正对的第二芯片的芯片中部区域正对，第一晶圆还包括位于第一芯片边缘的第一切割道，第二晶圆还包括位于第二芯片边缘且与相应的第一切割道正对的第二切割道，测试结构位于正对的芯片中部区域，以及位于第一切割道与正对的第二切割道内。
在一些实施例中，第一测试焊盘的材料与第二测试焊盘的材料相同。
在一些实施例中，半导体结构还包括：第一信号焊盘，第一键合面暴露出第一信号焊盘；第二信号焊盘，第二键合面暴露出第二信号焊盘，且第一信号焊盘与第二信号焊盘正对。
在一些实施例中，沿第一方向上，第一键合面露出的第一信号焊盘的宽度与第二键合面露出的第二信号焊盘的宽度相同。
在一些实施例中，测试结构邻近第一信号焊盘以及相应的第二信号焊盘。
本公开实施例另一方面还提供一种测量方法，包括：提供上述任一项所述的半导体结构中的第一晶圆和第二晶圆；将第一键合面与第二键合面相贴合以进行预对准；在进行预 对准之后，获取第一测试焊盘与第一个第二测试焊盘之间的连接状态，以及获取第一测试焊盘与第二个第二测试焊盘之间的连接状态，其中，若第一测试焊盘与第一个第二测试焊盘处于断开状态，则判断第二晶圆相对于第一晶圆在第二端指向第一端的方向发生了位移，若第一测试焊盘与第二个第二测试焊盘处于断开状态，则判断第二晶圆相对于第一晶圆在第一端指向第二端的方向发生了位移。
在一些实施例中，获取第一测试焊盘与特定的第二测试焊盘的连接状态的方式包括：测量第一测试焊盘与特定的第二测试焊盘的接触电阻；若接触电阻的阻值大于或等于预设值，则判断第一测试焊盘与特定的第二测试焊盘处于断开状态。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种半导体结构的结构示意图；
图2为本公开实施例提供的另一种半导体结构的结构示意图；
图3为本公开实施例提供的一种示出第一测试焊盘的部分第二键合面的结构示意图；
图4为本公开实施例提供的另一种示出第一测试焊盘的部分第二键合面的结构示意图；
图5为本公开实施例提供的又一种示出第一测试焊盘的部分第二键合面的结构示意图；
图6为本公开实施例提供的另一种示出第一测试焊盘的部分第二键合面的结构示意图；
图7为本公开实施例提供的另一种示出第一测试焊盘的部分第二键合面的结构示意图；
图8为本公开实施例提供的一种第一晶圆的结构示意图；
图9为本公开实施例提供的一种第一晶圆上测试结构与第一芯片的位置关系的结构示意图；
图10为本公开实施例提供的另一种第一晶圆上测试结构与第一芯片的位置关系的结构示意图；
图11为本公开实施例提供的一种第二晶圆相对于第一晶圆发生偏移的测试结构的示意图；
图12为本公开实施例提供的另一种第二晶圆相对于第一晶圆发生偏移的测试结构的示意图；
图13为本公开实施例提供的又一种第二晶圆相对于第一晶圆发生偏移的测试结构的示意图。
具体实施方式
由背景技术可知，利用目前的对准标记对相键合的两个晶圆进行对准的过程，无法准确的得知相键合的两个晶圆之间发生偏移的位移量，进而对半导体结构的性能造成了影响。
本公开实施例提供了一种半导体结构及一种测量方法。通过半导体结构中的测试结构即可判断第二晶圆与第一晶圆是否对齐键合，以及获取第二晶圆相对于第一晶圆的位移量，根据位移量，对下一半导体结构中第一晶圆与第二晶圆的键合进行校准，可提高半导体结构中第一晶圆与第二晶圆相键合的对准精度，进而有利于提高半导体结构的性能。
下面将结合附图对本公开各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
图1为本公开实施例提供的一种半导体结构的结构示意图；图2为本公开实施例提供的另一种半导体结构的结构示意图；图3为本公开实施例提供的一种示出第一测试焊盘的部分第二键合面的结构示意图；图4为本公开实施例提供的另一种示出第一测试焊盘的部分第二键合面的结构示意图；图5为本公开实施例提供的又一种示出第一测试焊盘的部分第二键合面的结构示意图；图6为本公开实施例提供的另一种示出第一测试焊盘的部分第二键合面的结构示意图；图7为本公开实施例提供的另一种示出第一测试焊盘的部分第二键合面的结构示意图；图8为本公开实施例提供的一种第一晶圆的结构示意图；图9为本公开实施例提供的一种第一晶圆上测试结构与第一芯片的位置关系的结构示意图；图10为本公开实施例提供的另一种第一晶圆上测试结构与第一芯片的位置关系的结构示意图。
参考图1，半导体结构包括：第一晶圆100，第一晶圆100具有第一键合面；第二晶圆110，第二晶圆110具有与第一键合面相键合的第二键合面；至少一组测试结构120，测 试结构120包括：第一测试焊盘101，第一键合面暴露出第一测试焊盘101表面，且第一测试焊盘101在第一方向具有露出于第一键合面的相对的第一端200和第二端201；至少两个第二测试焊盘111，两个第二测试焊盘111沿第一方向间隔排布于第二晶圆110内，且第二键合面暴露出第二测试焊盘111表面，第一测试焊盘101与两个第二测试焊盘111之间间隔的区域正对，且第一个第二测试焊盘111邻近第一端200，第二个第二测试焊盘111邻近第二端201；其中，第一个第二测试焊盘111与第一端200之间的最小距离为第一长度，第二个第二测试焊盘111与第二端201之间的最小距离为第二长度，第一长度等于第二长度，且第一长度与第二长度均大于零且小于预设值。
参考图1，第一测试焊盘101以及沿第一方向间隔排布的第二测试焊盘111，用于对第二晶圆110相对第一晶圆100在第一方向上发生偏移的位移量进行测量。并且，当第一晶圆100与第二晶圆110对准键合时，第一个第二测试焊盘111相对于第一端200向平行于第一方向的第一偏移方向偏移第一长度，第二个第二测试焊盘111相对于第二端201向第二偏移方向偏移第二长度，第一偏移方向和第二偏移方向为相反的方向，第一偏移方向也是第二个第二测试焊盘111指向第一个第二测试焊盘111的方向。且第一端200和第一个第二测试焊盘111为断开状态，第一测试焊盘101的第二端201和第二个第二测试焊盘111为连接状态。
因此，以第一方向为X方向，第一偏移方向为-X方向，且第二偏移方向为+X方向为例，若第二晶圆110相对于第一晶圆100在+X方向上发生了位移，则第一个第二测试焊盘111相对于第一端200向+X方向发生偏移，第一个第二测试焊盘111与第一端200相互连接，第二个第二测试焊盘111与第二端201仍相互断开。参考图2，若第二晶圆110相对于第一晶圆100在-X方向上发生了位移，则第一个第二测试焊盘111相对于第一端200向-X方向发生偏移，第一个第二测试焊盘111与第一端200相互断开，第二个第二测试焊盘111与第二端201相互连接。明显的，第一晶圆100与第二晶圆110之间在X方向上的不同偏移，使第二测试焊盘111与第一测试焊盘101的连接状态呈现不同的变化趋势。如此，根据测试结构120中第二测试焊盘111与第一测试焊盘101的连接状态即可判断第二晶圆110与第一晶圆100是否对齐键合，以及判断第二晶圆110与第一晶圆100发生偏移时的偏移方向。并且根据第一测试焊盘101与第二测试焊盘111在第一方向上重合部分的宽度，即可得出第二晶圆110相对于第一晶圆100发生偏移的位移量，根据位移量，对下一半导体结构中第一晶圆100与第二晶圆110的键合进行校准，可提高半导体结构中第一晶圆100与第二晶圆110相键合的对准精度，进而有利于提高半导体结构的性能。
另外，预设值可以为量测设备可测量出的最小尺寸，第一晶圆100与第二晶圆110对准键合时，第一长度与第二长度为大于零且小于预设值的相同长度，保证了对准键合时， 第一端200与第一个第二测试焊盘111为断开状态，第二端201与第二个第二测试焊盘111也为断开状态，并且，无论第二晶圆110相对于第二晶圆110在平行于第一方向的哪个方向上发生偏移，由于第一长度与第二长度相同，相对于对准键合时第一晶圆100与第二晶圆110的位置关系，量测出的第一晶圆100与第二晶圆110的位置关系均为较精准的位移关系，这是因为，若第一长度较长，第二长度较短，第一端200向第一个第二测试焊盘111偏移较大的位移量，才能使第一端200与第一个第二测试焊盘111相连接，而第二端201向第二个第二测试焊盘111偏移较小的位移量，就可使第二端201与第二个第二测试焊盘111相连接，使测试结构120量测出的第一晶圆100与第二晶圆110的位置关系具有误差。因此，对准键合时，第一长度与第二长度相同，有利于提高测试结构120的测试准确性。
第一晶圆100和第二晶圆110为制造有半导体器件或电路的晶圆，在一些实施例中，晶圆可以为以硅为衬底制作有半导体器件或电路的晶片。在另一些实施例中，晶圆的衬底也可以为其它半导体材料或其它可用于作为衬底的材料。
第一晶圆100与第二晶圆110键合，以使第一晶圆100中的半导体器件或电路与第二晶圆110中的半导体器件或电路电连接。第一晶圆100的第一键合面与第二晶圆110的第二键合面相对设置且相互键合，第一键合面可以露出引出第一晶圆100中的半导体器件或电路的焊盘，第二键合面可以露出引出第二晶圆110中的半导体器件或电路的焊盘，将第一晶圆100与第二晶圆110键合，第一键合面与第二键合面相接触，第一键合面上的焊盘与相应的第二键合面上的焊盘相接触，利用焊盘与焊盘的连接实现第一晶圆100内的半导体器件或电路与第二晶圆110内的半导体器件或电路的连接。
本公开实施例提供的半导体结构中的测试结构120为用于提高第一晶圆100与第二晶圆110对准精度的结构。测试结构120包括第一测试焊盘101以及沿第一方向间隔排布的至少两个第二测试焊盘111，第一方向可以为平行于第一晶圆100或第二晶圆110表面的任意方向，若第一方向为X方向，第一测试焊盘101在第一方向的两端、以及相应的在第一方向排布的两个第二测试焊盘111即可对第二晶圆110相对于第一晶圆100在X方向发生的偏移进行测量。因此，可以根据测试需求，对第一方向进行定义，以实现在任意的平行于第一晶圆100表面或平行于第二晶圆110表面的方向上，对第二晶圆110相对于第一晶圆100的位移进行测量。
以第一方向为X方向为例，第二晶圆110相对于第一晶圆100在X方向发生偏移包括两种情况，一种情况为第二晶圆110相对于第一晶圆100在+X方向发生了位移，另一种情况为第二晶圆110相对于第一晶圆100在-X方向发生了位移，本公开实施例提供的半导体结构中，在X方向上设置一组测试结构120，即可对上述第二晶圆110相对于第一晶圆100在X方向上的两种位移情况进行测量，如此，无需在第一晶圆100以及第二晶圆110内设置 较多的测试结构120以对更多的偏移方向进行测量，避免了在第一晶圆100以及第二晶圆110内为测试结构120预留较大的设置区域，有利于降低测试结构120制造难度。
在一些实施例中，参考图1，第一晶圆100和第二晶圆110均包括绝缘层130，绝缘层130的材料可以为氧化硅或氮化硅。并且，第一键合面露出第一晶圆100的绝缘层130，第一测试焊盘101位于绝缘层130内，第一测试焊盘101的材料为导电材料，例如可以为铜、钨或铝。第二键合面露出第二晶圆110的绝缘层130，第二测试焊盘111位于第二晶圆110的绝缘层130内，第二测试焊盘111的材料也为导电材料，例如可以为铜、钨或铝。
在一些实施例中，第一测试焊盘101的材料与第二测试焊盘111的材料相同。如此，有利于利用同种制备工艺以及利用同种源材料形成第一测试焊盘101和第二测试焊盘111，有利于降低第一测试焊盘101与第二测试焊盘111的制备难度。
参考图3至图5，在一些实施例中，第二键合面露出的每一第二测试焊盘111的形状相同。形成第二测试焊盘111通常需要采用光刻工艺与刻蚀工艺，光刻工艺用于定义第二测试焊盘111的形貌尺寸，但光刻工艺的光刻胶曝光时，曝光采用的入射光线会产生不期望的反射光或折射光，不期望的反射光或折射光可能使得不希望曝光的光刻胶被曝光，显影后，形成的光刻胶图案与预设形成的光刻胶图案具有误差。并且，反射光或折射光的强度和方向也与预设形成的光刻胶图案相关，若预设形成的光刻胶图案不同，光刻工艺的误差也不相同，因此，若每一第二测试焊盘111的形状不同，则与第二测试焊盘111相关的预设形成的光刻胶图案也不相同，预设形成的光刻胶图案不同可能导致不同的第二测试焊盘111具有不同的光刻误差，进而导致不同的第二测试焊盘111之间存在不同的设置误差，对第二测试焊盘111的测试准确性造成影响。因此，将第二键合面露出的每一第二测试焊盘111设置为形状相同的结构，即可避免不同形状的第二测试焊盘111之间由于光刻误差的不同而导致尺寸误差不同，有利于降低不同的第二测试焊盘111之间的尺寸误差，进而有利于利用尺寸误差较小的第二测试焊盘111对晶圆键合的对准精度进行更加准确的测量。
在一些实施例中，参考图3，第一键合面露出的第一测试焊盘101的形状为方形；第二键合面露出的第二测试焊盘111的形状也为方形，且方形的第一测试焊盘101的长度方向平行于第一方向、宽度方向垂直于第一方向，方形的第二测试焊盘111的长度方向平行于第一方向、宽度方向垂直于第一方向。如此，若第二晶圆110相对于第一晶圆100在第一方向上发生偏移，则一第二测试焊盘111与第一测试焊盘101重合部分的图形为方形，且第二测试焊盘111与第一测试焊盘101重合部分的方形的面积与第二测试焊盘111相对于第一测试焊盘101在第一方向发生的位移量呈线性关系，如此，较易根据第二测试焊盘111与第一测试焊盘101重合部分的方形的面积推出第二晶圆110相对于第一晶圆100发生偏移的位移量，有利于降低位移量的测量难度。
在一些实施例中，参考图4，以第一方向为X方向为例，在垂直于第一方向上，第一键合面露出的第一测试焊盘101的宽度小于第二键合面露出的第二测试焊盘111的宽度。垂直于第一方向的方向可以为Y方向，在Y方向上，若第一测试焊盘101的宽度与第二测试焊盘111的宽度相同，当第一测试焊盘101相对于第二测试焊盘111在X方向发生偏移，且第一测试焊盘101相对于第二测试焊盘111在Y方向也发生了位移时，第一测试焊盘101与第二测试焊盘111的重合面积与第二测试焊盘111相对于第一测试焊盘101在第一方向发生的位移量则不具有较为简单的线性关系，只能根据第一测试焊盘101与第二测试焊盘111在第一方向上重合的宽度获取位移量，因此，在垂直于第一方向上，设置第一测试焊盘101的宽度小于第二测试焊盘111的宽度，有利于根据第一测试焊盘101与第二测试焊盘111的重合面积判断第一晶圆100相对于第二晶圆110发生偏移的位移量，进而有利于降低位移量的测试难度。
可以理解的是，在一些实施例中，参考图5，在垂直于第一方向上，第一键合面露出的第一测试焊盘101的宽度也可以大于第二键合面露出的第二测试焊盘111的宽度，如此，根据第一测试焊盘101与第二测试焊盘111的重合面积也可判断第一晶圆100相对于第二晶圆110发生偏移的位移量，有利于降低位移量的测试难度。
在一些实施例中，第一键合面露出的第一测试焊盘101的形状或第二键合面露出的第二测试焊盘111的形状也可以为圆形或其它形状。
在一些实施例中，参考图3至图5，半导体结构可以具有至少两组测试结构120，其中，至少一组测试结构120中的第一方向为X方向，至少另一种测试结构120中的第一方向为Y方向。
需要说明的是，Y方向和X方向为不同的方向，在半导体结构内设置至少两组测试结构120，且一组测试结构120中的第一方向为X方向，另一组测试结构120中的第一方向为Y方向，利用第一方向为X方向的测试结构120测量第二晶圆110相对于第一晶圆100在X方向的位移情况，利用第一方向为Y方向的测试结构120测量第二晶圆110相对于第一晶圆100在Y方向的位移情况，即可在多个方向上对第二晶圆110相对于第一晶圆100的位移情况进行测量，进而有利于在多个方向上利用测试结构120提高第一晶圆100与第二晶圆110的对准精度。
在一些实施例中，Y方向垂直于X方向，结合半导体结构中设置的两组测试结构120量测出的位移量，即可对第一晶圆100与第二晶圆110在所有平行于第一晶圆100表面方向上发生的位移进行测量，如此，有利于利用测试结构120提高第一晶圆100与第二晶圆110的对准精度。
在一些实施例中，参考图6和图7，第一测试焊盘101还包括沿第二方向排布的第三端202和第四端203，测试结构120还包括沿第二方向间隔排布的两个第二测试焊盘111，第一方向与第二方向不同；其中，第三个第二测试焊盘111邻近第三端202，第四个第二测试焊盘111邻近第四端203，第三个第二测试焊盘111与第三端202之间的最小距离为第三长度，第四个第二测试焊盘111与第四端203之间的最小距离为第四长度，第三长度等于第四长度，且第三长度与第四长度均大于零且小于预设值。
如此，根据第三端202、第四端203、在第二方向间隔排布的第三个第二测试焊盘111以及第四个第二测试焊盘111的连接状态，即可判断第二晶圆110相对于第一晶圆100在第二方向发生偏移的状态，以及判断第二晶圆110相对于第一晶圆100在第二方向发生偏移的位移量，利用一组测试结构120即可在多个方向上对第二晶圆110相对于第一晶圆100的位移情况进行测量，无需在第一晶圆100以及第二晶圆110内设置较多的测试结构120，避免了在第一晶圆100以及第二晶圆110内为测试结构120预留较大的设置区域，有利于降低测试结构120制造难度。
在一些实施例中，Y方向垂直于X方向，通过一组测试结构120，即可对第一晶圆100与第二晶圆110在所有平行于第一晶圆100表面方向上发生的位移进行测量，如此，避免了在第一晶圆100以及第二晶圆110内设置较多的测试结构120，有利于降低测试结构120制造难度。
在一些实施例中，第三长度等于第一长度。若第三长度较长，第一长度较短，第二晶圆110相对于第一晶圆100在第一方向发生较大位移量的偏移时，测试结构120才可量测出位移量，而第二晶圆110相对于第一晶圆100在第二方向发生较小位移量的偏移时，测试结构120就可量测出位移量，导致测试结构120在不同的方向上量测出的第一晶圆100与第二晶圆110的位置关系具有误差。同理，若第一长度较长，第三长度较短，测试结构120在不同的方向上量测出的第一晶圆100与第二晶圆110的位置关系也具有误差，因此，第一晶圆100与第二晶圆110对准键合时，第一长度与第二长度相同，有利于提高测试结构120的测试准确性。
在一些实施例中，参考图6和图7，第一端200至第二端201的最大长度与第三端202至第四端203的最大长度相同。如此，有利于降低第一测试焊盘101与第二测试焊盘111的设置难度。
在一些实施例中，参考图1，以第一方向为X方向为例，沿第一方向上，第一测试焊盘101的宽度可以为100nm～10000nm，例如可以为250nm、450nm、500nm、5400nm、8900nm等。第二测试焊盘111的宽度可以为100nm～10000nm，例如可以为100nm、1500nm、2500nm、 4500nm、9500nm等。在一些实施例中，可以根据第一晶圆100和第二晶圆110在第一方向上的尺寸，合理的设置第一测试焊盘101与第二测试焊盘111在第一方向上的宽度。
在一些实施例中，参考图1，以第一方向为X方向为例，沿垂直于第一方向上，第一测试焊盘101的长度为100nm～1000nm，例如可以为250nm、300nm、450nm、500nm、800nm等。第二测试焊盘111的长度为100nm～1000nm，例如可以为450nm、360nm、480nm、550nm、760nm等。同理，可以根据第一晶圆100和第二晶圆110在垂直于第一方向上的尺寸，合理的设置第一测试焊盘101与第二测试焊盘111在第一方向上的宽度。
在一些实施例中，参考图1，半导体结构还包括：第一信号焊盘102，第一键合面暴露出第一信号焊盘102；第二信号焊盘112，第二键合面暴露出第二信号焊盘112，且第一信号焊盘102与第二信号焊盘112正对。
第一信号焊盘102可以为用于为第一晶圆100内的半导体器件或电路提供测试信号的焊盘，第二信号焊盘112可以为用于为第二晶圆110内的半导体器件或电路提供测试信号的焊盘，正对的第一信号焊盘102与第二信号焊盘112相互连接，使第一晶圆100内的半导体器件或电路与第二晶圆110内的半导体器件或电路共用一条信号引线，有利于降低半导体结构中引线布局的复杂度，以及有利于降低半导体结构的制造难度。
在一些实施例中，参考图1，沿第一方向上，第一键合面露出的第一信号焊盘102的宽度与第二键合面露出的第二信号焊盘112的宽度相同。以第一方向为X方向为例，在第一方向上宽度相同且正对的第一信号焊盘102和第二信号焊盘112可作为第一测试焊盘101以及第二测试焊盘111设置过程中的定位标记，如此有利于利用半导体结构中现有的焊盘准确地在第一晶圆100内设置第一测试焊盘101，以及准确地在第二晶圆110内设置第二测试焊盘111，避免了设置额外的定位标记，有利于降低第一测试焊盘101以及第二测试焊盘111的制造难度。
在一些实施例中，参考图1，测试结构120邻近第一信号焊盘102以及相应的第二信号焊盘112。第一信号焊盘102以及第二信号焊盘112也可以是为半导体结构内的器件或电路提供工作信号的焊盘，将测试结构120设置在邻近第一信号焊盘102与正对第一信号焊盘102的位置，即可利用测试结构120对第一信号焊盘102与第二信号焊盘112的对准状态进行测量，以及利用测试结构120获取第二信号焊盘112相对于第一信号焊盘102发生偏移的位移量，并根据位移量，对第一信号焊盘102以及正对的第二信号焊盘112进行精确的对准键合，对准的第一信号焊盘102以及第二信号焊盘112相连接的面积更大，有利于提高测试信号或工作信号通过第一测试焊盘101与第二测试焊盘111的导通速度，进而有利于提高半导体结构内测试信号的传输速度，提高测试效率，或者有利于提高半导体结构中的器件或电 路的运行速度，提高半导体结构的性能。
在一些实施例中，参考图1，第一信号焊盘102也设置在第一晶圆100的绝缘层130内，第二信号焊盘112也设置在第二晶圆110的绝缘层130内，第一信号焊盘102与第二信号焊盘112的材料相同，第一信号焊盘102或第二信号焊盘112的材料可以包括铜、钨或铝。并且，第一晶圆100的与第一键合面相对的表面也露出第一信号焊盘102，第二晶圆110的与第二键合面相对的表面也露出第二信号焊盘112，如此，有利于利用露出的第一信号焊盘102为第一信号焊盘102提供电信号，以及有利于利用露出的第二信号焊盘112为第二信号焊盘112提供电信号。
在一些实施例中，参考图8，第一晶圆100具有第一中部区域103以及第一边缘区域104，第二晶圆110具有第二中部区域以及第二边缘区域，第一中部区域103与第二中部区域正对，第一边缘区域104与第二边缘区域正对，第一中部区域103和正对的第二中部区域具有相应的测试结构120，第一边缘区域104和正对的第二边缘区域也具有相应的测试结构。其中，第一中部区域103为位于第一晶圆100中心附近的区域，第一边缘区域104为靠近第一晶圆100边缘的区域。第二中部区域为位于第二晶圆110中心附近的区域，第二边缘区域为靠近第二晶圆110边缘的区域。
如此，利用第一晶圆100和第二晶圆110的中部的测试结构120，对第一晶圆100的中心与第二晶圆110的中心进行对准量测，利用第一晶圆100和第二晶圆110的边缘的测试结构120，对第一晶圆100的边缘与第二晶圆110边缘进行对准量测，对中心以及边缘进行对准即可实现对第一晶圆100和第二晶圆110的整体进行对准量测，如此有利于利用有限数量的测试结构120对第一晶圆100与第二晶圆110的键合进行精准的量测。需要说明的是，第二晶圆110的第二中部区域以及第二边缘区域与第一晶圆100类似，第二晶圆110的第二中部区域以及第二边缘区域未示出。
在一些实施例中，第一中部区域103和相对的第二中部区域设置有多组测试结构120，第一边缘区域104和相对的第二边缘区域也设置有多组测试结构120。较多的测试结构120有利于提高第一晶圆100与第二晶圆110的对准精度。
在一些实施例中，参考图9和图10，第一晶圆100包括多个第一芯片105，第二晶圆110包括多个第二芯片，每一第一芯片105与相应的第二芯片正对；部分第一芯片105和正对的第二芯片具有相应的测试结构120。
如此，不仅可以利用测试结构120对第二晶圆110相对于第一晶圆100整体的位移进行测量，还可以对第二芯片相对于相应的第一芯片105的位移进行测量，有利于利用测试结构120准确的获取第二芯片与第一芯片105之间的位移量，进而实现第二芯片与第一芯片 105的准确对准键合，对准精度更高的第一芯片105和第二芯片有利于提高半导体结构的性能。需要说明的是，第二晶圆110的第二芯片与第一晶圆100内第一芯片105的排布类似，因此，未示出第二晶圆110内第二芯片的结构。
在一些实施例中，参考图9，第一芯片105与第二芯片均具有芯片中部区域和芯片边缘区域，且第一芯片105的芯片中部区域和正对的第二芯片的芯片中部区域正对，第一芯片105的芯片边缘区域和正对的第二芯片的芯片边缘区域正对，测试结构120位于正对的芯片中部区域以及正对的芯片边缘区域。
芯片中部区域为位于第一芯片105或第二芯片的中心附近的区域，芯片边缘区域为靠近第一芯片105或第二芯片的边缘的区域。为了提高对第一芯片105与正对的第二芯片的对准精度的测量，可以在一第一芯片105与正对的第二芯片内设置至少两组相应的测试结构120，两组测试结构120可以分别位于芯片中部区域以及芯片边缘区域。如此，即可利用芯片中部区域的测试结构120对第一芯片105的中部与第二芯片的中部的对准状态进行测量，再利用芯片边缘区域的测试结构120对第一芯片105的边缘与第二芯片的边缘的对准状态进行测量，进而有利于利用测试结构120对第一芯片105与正对的第二芯片键合的对准情况进行准确的测量。
在一些实施例中，参考图10，，第一芯片105与第二芯片均具有芯片中部区域，第一芯片105的芯片中部区域和正对的第二芯片的芯片中部区域正对，第一晶圆100还包括位于第一芯片105边缘的第一切割道106，第二晶圆110还包括位于第二芯片边缘且与相应的第一切割道106正对的第二切割道，测试结构120位于正对的芯片中部区域，以及位于第一切割道106与正对的第二切割道内。其中，芯片中部区域为位于第一芯片105或第二芯片的中心附近的区域。
如此，即可利用芯片中部区域的测试结构120对第一芯片105的中部与第二芯片的中部的对准状态进行测量，再利用芯片边缘的第一切割道106以及第二切割道内的测试结构120对第一芯片105的边缘与第二芯片的边缘的对准状态进行测量。
可以理解的是，在一些实施例中，测试结构120为图3至图5所示的测试结构120，即一组测试结构120仅对第二晶圆110相对于第一晶圆100在第一方向的偏移进行测试，若以对第一芯片105和正对的第二芯片的中部进行键合的对准情况进行测量为例，可以在第一芯片105的中部和正对的第二芯片的中部设置至少两组测试结构120，两组测试结构120中的第一方向可以分别为相互垂直的X方向和Y方向。如此，可对第一芯片105的中部与正对的第二芯片的中部在各个方向的位移进行测量。同理，对第一芯片105的边缘与正对的第二芯片的边缘在各个方向的位移进行测量的测试结构120也类似，可以在第一芯片105的边 缘和正对的第二芯片的边缘设置至少两组第一方向不同的测试结构120，两组测试结构120中的第一方向可以分别为相互垂直的X方向和Y方向。
在一些实施例中，相邻测试结构120之间的间隔距离可以较小，在一个例子中，一第一芯片105与正对的第二芯片具有邻近的多组测试结构120。在另一些实施例中，相邻测试结构120之间的间隔距离也可以较远，在一个例子中，一第一芯片105与正对的第二芯片仅具有一组邻近的测试结构120。
上述实施例提供的半导体结构中，半导体结构包括相互键合的第一晶圆100和第二晶圆110，且第一晶圆100的第一键合面和第二晶圆110的第二键合面相键合，相互键合的第一晶圆100和第二晶圆110具有用于量测第一晶圆100与第二晶圆110对准偏差的测试结构120，测试结构120包括一个露出于第一键合面的第一测试焊盘101以及至少两个露出于第二键合面的第二测试焊盘111，第一测试焊盘101的两端以及两个第二测试焊盘111均沿第一方向间隔排布，用于对第二晶圆110相对第一晶圆100在第一方向上发生偏移的位移量进行测量。另外，第一测试焊盘101与两个第二测试焊盘111之间间隔的区域正对，第一测试焊盘101的第一端200与第一个第二测试焊盘111对应，第一测试焊盘101的第二端201与第二个第二测试焊盘111对应，第一个第二测试焊盘111相对于第一端200向平行于第一方向的第一偏移方向偏移第一长度，第二个第二测试焊盘111相对于第二端201向第二偏移方向偏移第二长度，第一偏移方向和第二偏移方向为相反的方向，第一偏移方向也是第二个第二测试焊盘111指向第一个第二测试焊盘111的方向。其中，第一长度与第二长度均小于预设值，预设值可以为量测设备可测量出的最小尺寸，如此，若第一端200与第一个第二测试焊盘111相连接，则判断第二晶圆110相对于第一晶圆100在第二偏移方向上发生了位移，若第二端201与第二个第二测试焊盘111相连接，则判断第二晶圆110相对于第一晶圆100在第一偏移方向上发生了位移，且根据第一测试焊盘101与第二测试焊盘111在第一方向上重合的部分宽度，即可得出第二晶圆110相对于第一晶圆100发生偏移的位移量。如此，通过测试结构120即可判断第二晶圆110与第一晶圆100是否对齐键合，以及获取第二晶圆110相对于第一晶圆100的位移量，根据位移量，对下一半导体结构中第一晶圆100与第二晶圆110的键合进行校准，可提高半导体结构中第一晶圆100与第二晶圆110相键合的对准精度，进而有利于提高半导体结构的性能。
相应的，本公开实施例另一方面还提供一种测量方法，该测量方法可以对上述实施例提供的半导体结构进行测量。需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的详细说明，以下将不做赘述。
图11为本公开实施例提供的一种第二晶圆相对于第一晶圆发生偏移的测试结构的示意图；图12为本公开实施例提供的另一种第二晶圆相对于第一晶圆发生偏移的测试结构的 示意图；图13为本公开实施例提供的又一种第二晶圆相对于第一晶圆发生偏移的测试结构的示意图。
参考图1、图7、图11至图13，测量方法包括：提供上述任一项所述的半导体结构中的第一晶圆100和第二晶圆110；将第一键合面与第二键合面相贴合以进行预对准；在进行预对准之后，获取第一测试焊盘101与第一个第二测试焊盘111之间的连接状态，以及获取第一测试焊盘101与第二个第二测试焊盘111之间的连接状态，其中，若第一测试焊盘101与第一个第二测试焊盘111处于断开状态，则判断第二晶圆110相对于第一晶圆100在第二端201指向第一端200的方向发生了位移，若第一测试焊盘101与第二个第二测试焊盘111处于断开状态，则判断第二晶圆110相对于第一晶圆100在第一端200指向第二端201的方向发生了位移。
在一些实施例中，参考图1和图11，以第一方向为X方向，第一偏移方向为-X方向，第二偏移方向为+X方向为例，若第一端200与第一个第二测试焊盘111为断开状态，第二端201与第二个第二测试焊盘111为连接状态，则判断第二晶圆110相对于第一晶圆100在-X方向上发生了偏移。
参考图1和图12，以第一方向为X方向，第一偏移方向为-X方向，第二偏移方向为+X方向为例，若第一端200与第一个第二测试焊盘111为连接状态，第二端201与第二个第二测试焊盘111为断开状态，则判断第二晶圆110相对于第一晶圆100在+X方向上发生了偏移。
在一些实施例中，测试结构120中的第一测试焊盘101还包括第三端202和第四端203，参考图1和图13，以第一方向为X方向，第一偏移方向为-X方向，第二偏移方向为+X方向，第二方向为Y方向，第三偏移方向为-Y方向，第四偏移方向为+Y方向为例，第三偏移方向和第四偏移方向为平行于第二方向的相反方向，第三偏移方向也是第四个第二测试焊盘111指向第三个第二测试焊盘111的方向。若第一端200与第一个第二测试焊盘111为连接状态，第二端201与第二个第二测试焊盘111为断开状态，且第四端203与第四个第二测试焊盘111为连接状态，第三端202与第三个第二测试焊盘111为断开状态，则判断第二晶圆110相对于第一晶圆100在+X方向上发生了偏移，并且，第二晶圆110相对于第一晶圆100在-Y方向上也发生了偏移。
另外，根据第一测试焊盘101与相应的第二测试焊盘111的重合面积，分析获得第二晶圆110相对于第一晶圆100发生偏移的位移量，进而有利于根据位移量对下一第一晶圆100与相键合的第二晶圆110的键合进行校准，以使第一晶圆100与第二晶圆110具有较小的偏移，有利于提高半导体结构的性能。
在一些实施例中，获取第一测试焊盘101与特定的第二测试焊盘111的连接状态的方式包括：测量第一测试焊盘101与特定的第二测试焊盘111的接触电阻；若接触电阻的阻值大于或等于预设值，则判断第一测试焊盘101与特定的第二测试焊盘111处于断开状态。
在一些实施例中，可以设置引线将第一测试焊盘101以及第二测试焊盘111引出，并通过引线向第一测试焊盘101以及第二测试焊盘111提供测试电流，以图7所示实施例为例，第一晶圆100与第二晶圆110对准键合时，第一测试焊盘101与四个第二测试焊盘111的接触电阻的阻值均为无限大，则第一测试焊盘101与四个第二测试焊盘111均为断开状态。
以图13所示实施例为例，若测试结构120中的第一测试焊盘101与第一个第二测试焊盘111的接触电阻为一可量测出的具体阻值，第一测试焊盘101与第四个第二测试焊盘111的接触电阻也为一可量测出的具体阻值，且第一测试焊盘101与剩余两个第二测试焊盘111的接触电阻均为无限大，则第一测试焊盘101与第一个第二测试焊盘111为连接状态，第一测试焊盘101与第四个第二测试焊盘111也为连接状态，第一测试焊盘101与第二个第二测试焊盘111为断开状态，第一测试焊盘101与第三个第二测试焊盘111也为断开状态。
另外，第一测试焊盘101与相应的第二测试焊盘111的接触电阻越大，第一测试焊盘101与相应的第二测试焊盘111的重合面积越小。
在一些实施例中，也可以通过红外线量测的方式，对第一测试焊盘101与相应的第二测试焊盘111的正对面积进行测量。
上述实施例提供的测量方法中，通过测量第一测试焊盘101与相应的第二测试焊盘111的连接状态，即可判断第二晶圆110相对于第一晶圆100的位移状态，以及通过测量第一测试焊盘101与相应的第二测试焊盘111的重合面积，即可判断第二晶圆110相对于第一晶圆100的位移量，进而利用测量获得的位移量对下一第一晶圆100与相键合的第二晶圆110的键合进行校准，使第一晶圆100与第二晶圆110具有较小的偏移，有利于提高半导体结构的性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自变动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种半导体结构，包括：
    第一晶圆，所述第一晶圆具有第一键合面；
    第二晶圆，所述第二晶圆具有与所述第一键合面相键合的第二键合面；
    至少一组测试结构，所述测试结构包括：
    第一测试焊盘，所述第一键合面暴露出所述第一测试焊盘表面，且所述第一测试焊盘在第一方向具有露出于所述第一键合面的相对的第一端和第二端；
    至少两个第二测试焊盘，两个所述第二测试焊盘沿所述第一方向间隔排布于所述第二晶圆内，且所述第二键合面暴露出所述第二测试焊盘表面，所述第一测试焊盘与两个所述第二测试焊盘之间间隔的区域正对，且第一个所述第二测试焊盘邻近所述第一端，第二个所述第二测试焊盘邻近所述第二端；
    其中，第一个所述第二测试焊盘与所述第一端之间的最小距离为第一长度，第二个所述第二测试焊盘与所述第二端之间的最小距离为第二长度，所述第一长度等于所述第二长度，且所述第一长度与所述第二长度均大于零且小于预设值。
  2. 如权利要求1所述半导体结构，其中，所述第二键合面露出的每一所述第二测试焊盘的形状相同。
  3. 如权利要求1所述半导体结构，其中，所述第一测试焊盘还包括沿第二方向排布的第三端和第四端，所述测试结构还包括沿所述第二方向间隔排布的两个第二测试焊盘，所述第一方向与所述第二方向不同；
    其中，第三个所述第二测试焊盘邻近所述第三端，第四个所述第二测试焊盘邻近所述第四端，第三个所述第二测试焊盘与所述第三端之间的最小距离为第三长度，第四个所述第二测试焊盘与所述第四端之间的最小距离为第四长度，所述第三长度等于所述第四长度，且所述第三长度与所述第四长度均大于零且小于预设值。
  4. 如权利要求3所述半导体结构，其中，所述第三长度等于所述第一长度。
  5. 如权利要求1所述半导体结构，其中，所述半导体结构具有至少两组所述测试结构，其中，至少一组所述测试结构中的所述第一方向为X方向，至少另一种所述测试结构中的所述第一方向为Y方向。
  6. 如权利要求1所述半导体结构，其中，所述第一晶圆具有第一中部区域以及第一边缘区 域，所述第二晶圆具有第二中部区域以及第二边缘区域，所述第一中部区域与所述第二中部区域正对，所述第一边缘区域与所述第二边缘区域正对，所述第一中部区域和正对的所述第二中部区域具有相应的所述测试结构，所述第一边缘区域和正对的所述第二边缘区域也具有相应的所述测试结构。
  7. 如权利要求1所述半导体结构，其中，所述第一晶圆包括多个第一芯片，所述第二晶圆包括多个第二芯片，每一所述第一芯片与相应的所述第二芯片正对；部分所述第一芯片和正对的所述第二芯片具有相应的所述测试结构。
  8. 如权利要求7所述半导体结构，其中，所述第一芯片与所述第二芯片均具有芯片中部区域和芯片边缘区域，且所述第一芯片的所述芯片中部区域和正对的所述第二芯片的所述芯片中部区域正对，所述第一芯片的所述芯片边缘区域和正对的所述第二芯片的所述芯片边缘区域正对，所述测试结构位于正对的所述芯片中部区域以及正对的所述芯片边缘区域。
  9. 如权利要求7所述半导体结构，其中，所述第一芯片与所述第二芯片均具有芯片中部区域，所述第一芯片的所述芯片中部区域和正对的所述第二芯片的所述芯片中部区域正对，所述第一晶圆还包括位于所述第一芯片边缘的第一切割道，所述第二晶圆还包括位于所述第二芯片边缘且与相应的所述第一切割道正对的第二切割道，所述测试结构位于正对的所述芯片中部区域，以及位于所述第一切割道与正对的所述第二切割道内。
  10. 如权利要求1所述半导体结构，其中，所述第一测试焊盘的材料与所述第二测试焊盘的材料相同。
  11. 如权利要求1所述半导体结构，其中，所述半导体结构还包括：第一信号焊盘，所述第一键合面暴露出所述第一信号焊盘；第二信号焊盘，所述第二键合面暴露出所述第二信号焊盘，且所述第一信号焊盘与所述第二信号焊盘正对。
  12. 如权利要求11所述半导体结构，其中，沿所述第一方向上，所述第一键合面露出的所述第一信号焊盘的宽度与所述第二键合面露出的所述第二信号焊盘的宽度相同。
  13. 如权利要求11所述半导体结构，其中，所述测试结构邻近所述第一信号焊盘以及相应的所述第二信号焊盘。
  14. 一种测量方法，其中，包括：
    提供如权利要求1-13中任一所述的半导体结构中的所述第一晶圆和所述第二晶圆；
    将所述第一键合面与所述第二键合面相贴合以进行预对准；
    在进行所述预对准之后，获取所述第一测试焊盘与第一个所述第二测试焊盘之间的连接状态，以及获取所述第一测试焊盘与第二个所述第二测试焊盘之间的连接状态，其中，若第一测试焊盘与第一个所述第二测试焊盘处于断开状态，则判断所述第二晶圆相对于所述第一晶圆在所述第二端指向所述第一端的方向发生了位移，若第一测试焊盘与第二个所述第二测试焊盘处于断开状态，则判断所述第二晶圆相对于所述第一晶圆在所述第一端指向所述第二端的方向发生了位移。
  15. 如权利要求14所述测量方法，其中，获取所述第一测试焊盘与特定的所述第二测试焊盘的连接状态的方式包括：测量所述第一测试焊盘与特定的所述第二测试焊盘的接触电阻；
    若接触电阻的阻值大于或等于预设值，则判断所述第一测试焊盘与特定的所述第二测试焊盘处于断开状态。
PCT/CN2022/111771 2022-08-01 2022-08-11 半导体结构及测量方法 WO2024026914A1 (zh)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001028464A (ja) * 1999-07-15 2001-01-30 Agency Of Ind Science & Technol フリップチップ接続アライメント精度評価方法
CN203824509U (zh) * 2014-05-05 2014-09-10 中芯国际集成电路制造(北京)有限公司 一种检测键合准确性的测试结构
CN204315526U (zh) * 2015-01-07 2015-05-06 中芯国际集成电路制造(北京)有限公司 金属键合对准监控结构
CN104779238A (zh) * 2014-01-10 2015-07-15 中芯国际集成电路制造(上海)有限公司 一种晶圆接合质量的检测结构及检测方法
US20150233698A1 (en) * 2014-02-19 2015-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for verification of bonding alignment
CN206992074U (zh) * 2017-07-06 2018-02-09 武汉新芯集成电路制造有限公司 一种用于测试键合晶圆对准误差的结构
CN110634809A (zh) * 2018-06-25 2019-12-31 台湾积体电路制造股份有限公司 三维集成电路结构
CN110660766A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 半导体器件和形成半导体器件的方法
CN113889420A (zh) * 2020-07-03 2022-01-04 联华电子股份有限公司 半导体元件结构及接合二基板的方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001028464A (ja) * 1999-07-15 2001-01-30 Agency Of Ind Science & Technol フリップチップ接続アライメント精度評価方法
CN104779238A (zh) * 2014-01-10 2015-07-15 中芯国际集成电路制造(上海)有限公司 一种晶圆接合质量的检测结构及检测方法
US20150233698A1 (en) * 2014-02-19 2015-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for verification of bonding alignment
CN203824509U (zh) * 2014-05-05 2014-09-10 中芯国际集成电路制造(北京)有限公司 一种检测键合准确性的测试结构
CN204315526U (zh) * 2015-01-07 2015-05-06 中芯国际集成电路制造(北京)有限公司 金属键合对准监控结构
CN206992074U (zh) * 2017-07-06 2018-02-09 武汉新芯集成电路制造有限公司 一种用于测试键合晶圆对准误差的结构
CN110634809A (zh) * 2018-06-25 2019-12-31 台湾积体电路制造股份有限公司 三维集成电路结构
CN110660766A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 半导体器件和形成半导体器件的方法
CN113889420A (zh) * 2020-07-03 2022-01-04 联华电子股份有限公司 半导体元件结构及接合二基板的方法

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