TW201714206A - 磊晶層的形成方法 - Google Patents

磊晶層的形成方法 Download PDF

Info

Publication number
TW201714206A
TW201714206A TW105106530A TW105106530A TW201714206A TW 201714206 A TW201714206 A TW 201714206A TW 105106530 A TW105106530 A TW 105106530A TW 105106530 A TW105106530 A TW 105106530A TW 201714206 A TW201714206 A TW 201714206A
Authority
TW
Taiwan
Prior art keywords
epitaxial layer
forming
vapor deposition
helium
layer according
Prior art date
Application number
TW105106530A
Other languages
English (en)
Other versions
TWI619149B (zh
Inventor
肖德元
汝京 張
Original Assignee
上海新昇半導體科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海新昇半導體科技有限公司 filed Critical 上海新昇半導體科技有限公司
Publication of TW201714206A publication Critical patent/TW201714206A/zh
Application granted granted Critical
Publication of TWI619149B publication Critical patent/TWI619149B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02598Microstructure monocrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02634Homoepitaxy

Abstract

本發明提出了一種磊晶層的形成方法,在採用氣相沉積法形成磊晶層時,使用包括氘氣的載氣,由於處於氘氣的環境中,能夠使形成的磊晶層內部存有氘原子,在後續閘氧化層或裝置的形成時,氘原子能夠擴散出,並與介面處等懸鍵進行結合,形成較為穩定的結構,從而避免熱載子效應的發生,提高裝置的性能。

Description

磊晶層的形成方法
本發明係關於半導體製造領域,尤其係關於一種磊晶層的形成方法。
在半導體裝置製造領域,通常會在矽基板上形成一層單晶矽作為磊晶層,磊晶層能夠在後續進行離子注入摻雜,形成注入基區、發射區等等。
隨著現代微電子裝置的尺寸不斷收縮,對磊晶層的品質挑戰逐漸增大。而磊晶層的品質取決於生長在其內部微小缺陷(microdefects)的大小和分佈情況。在磊晶層的形成過程中,大多數微小缺陷會聚集矽內部空隙(silicon-vacancies)或者填在間隙之中。
使用氫氣形成鈍化層在半導體裝置製造領域已經是被廣為所知並且常用的技術手段。在氫鈍化過程中,能夠去除缺陷對半導體裝置的影響。例如,該種缺陷被描述為複合或者半導體裝置中心的活性成分。這些中心是由懸鍵造成,該懸鍵能夠去除電荷載體或者引入不必要的電荷載體,這部分主要取決於偏壓。而懸鍵主要發生在表面或裝置的介面,同時其也能夠發生在空缺、微孔隙等處,其也與雜質相關。
在半導體製造領域中,還存在由熱載子引起的裝置性能下降的問題。該問題在小尺寸裝置及高壓裝置中尤其重要。當使用高壓裝置時,通道內的載子具有較大的能量能夠穿透進入絕緣層,從而使裝置的性能變差。
由於氫氣形成的鈍化層不太穩定,在與懸鍵進行鍵合後,極易被破壞,從而使懸鍵再次暴露出,從而影響裝置的性能。
本發明的目的在于提供一种磊晶層的形成方法,能夠減少後續裝置介面層的懸鍵,提高裝置的性能。
為了實現上述目的,本發明提出了一種磊晶層的形成方法,包括步驟:提供矽基板;在所述矽基板表面形成一層磊晶層,所述磊晶層採用氣相沉積法形成,其中載氣包括氘氣。
在所述的磊晶層的形成方法中,所述氣相沉積法的溫度範圍為800℃~1100℃。
在所述的磊晶層的形成方法中,所述氣相沉積法使用的載氣為氘氣和氫氣的混合氣體。
在所述的磊晶層的形成方法中,所述氘氣占的比例範圍為1%~100%。
在所述的磊晶層的形成方法中,所述氣相沉積法使用的載氣為氘氣。
在所述的磊晶層的形成方法中,所述磊晶層為單晶矽。
在所述的磊晶層的形成方法中,所述氣相沉積法使用的反應氣體為包含矽元素的氣體。
在所述的磊晶層的形成方法中,所述氣相沉積法使用的反應氣體為SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4
在所述的磊晶層的形成方法中,提供所述矽基板之後,在形成磊晶層之前,還包括步驟:去除所述矽基板表面的自然氧化層;對所述矽基板進行清洗。
在所述的磊晶層的形成方法中,採用濕式或者乾式蝕刻去除所述矽基板表面的自然氧化層。
與現有技術相比,本發明的有益效果主要落實於:在採用氣相沉積法形成磊晶層時,使用包括氘氣的載氣,由於處於氘氣的環境中,能夠使形成的磊晶層內部存有氘原子,在後續閘氧化層或裝置的形成時,氘原子能夠擴散出,並與介面處等懸鍵進行結合,形成較為穩定的結構,從而避免載子的穿透,提高裝置的性能。
S100‧‧‧提供矽基板
S200‧‧‧在所述矽基板表面形成一層磊晶層,所述磊晶層採用氣相沉積法形成,其中載氣包括氘氣
第1圖為本發明一實施例中磊晶層的形成方法的流程圖。
下面將結合示意圖對本發明的磊晶層的形成方法進行更詳細的描述,其中表示了本發明的較佳實施例,應理解具本領域通常知識者可以對此處描述之本發明進行修改,而仍然實現本發明的有利效果。因此, 下列描述應該被理解為對於本領域技術人員的廣泛認知,而並非作為對本發明的限制。
為了清楚,不描述實際實施例的全部特徵。在下列描述中,不詳細描述眾所周知的功能和結構,因為它們會使本發明由於不必要的細節而混亂。應當認為在任何實際實施例的開發中,必須做出大量實施細節以實現開發者的特定目標,例如按照有關系統或有關商業的限制,由一個實施例改變為另一個實施例。另外,應當認為這種開發工作可能是複雜和耗費時間的,但是對於具本領域通常知識者來說僅僅是常規工作。
在下列段落中參照圖式以舉例方式更具體地描述本發明。根據下面的說明和申請專利範圍,本發明的優點和特徵將更清楚。需說明的是,圖式均採用非常簡化的形式且均使用非精準的比例,僅用以方便、明晰地輔助說明本發明實施例的目的。
請參考第1圖,在本實施例中,提出了一種磊晶層的形成方法,包括步驟:S100:提供矽基板;S200:在所述矽基板表面形成一層磊晶層,所述磊晶層採用氣相沉積法形成,其中載氣包括氘氣。
具體的,所述矽基板的形成方法包括:形成矽鑄塊(ingot);打磨所述矽鑄塊至所需的尺寸,例如晶圓大小的尺寸;接著,對所述矽鑄塊依次進行切薄(slicing)、表面磨削(surface grinding)、拋光(polishing)、邊緣處理(edge profiling)及清洗處理(cleaning)等製 程,從而形成矽基板。在本實施例中,所述矽基板為單晶矽,採用直拉法(CZ)形成。
提供所述矽基板之後,在形成磊晶層之前,還包括步驟:去除所述矽基板表面的自然氧化層,所述自然氧化層可以採用濕式或者乾式蝕刻去除;通常情況下,矽基板在長期暴露在空氣之中會被空氣中的氧氣氧化,形成一層較薄的自然氧化層,去除所述自然氧化層能夠使後續形成的磊晶層與矽基板之間具有良好的接觸,並且可以提高矽基板的品質;接著,對所述矽基板進行清洗。
在步驟S200中,採用氣相沉積法形成磊晶層,其中,氣相沉積法所使用的載氣包括氘氣。
具體的,所述氣相沉積法的溫度範圍為800℃~1100℃,例如是1000℃。
在本實施例中,所述氣相沉積法使用的載氣為氘氣和氫氣的混合氣體,其中,所述氘氣占的比例範圍為1%~100%,具體的比例可以根據不同的製程需求來決定。
除此之外,所述氣相沉積法使用的載氣也可以是單純的氘氣。
使用氘氣作為載氣,在形成磊晶層時,由於氘原子體積小,能夠暫時貯存在磊晶層的間隙中,在後續形成閘氧化層或裝置時,可以與閘氧化層等的懸鍵進行結合,形成穩定的化學鍵,消除多餘的懸鍵,從而可以提高閘氧化層的性能。此外,氘原子不僅僅與閘氧化層的懸鍵進行結 合,還能夠與半導體裝置的中其他層的懸鍵進行結合,而且形成的化學鍵較其他元素(例如氫原子)形成的化學鍵更為穩定。
在本實施例中,所述磊晶層為單晶矽。所述氣相沉積法使用的反應氣體為包含矽元素的氣體,例如是SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4等氣體均可。磊晶層的厚度等均由不同製程決定,在此不作限定。
綜上,在本發明實施例提供的磊晶層的形成方法中,在採用氣相沉積法形成磊晶層時,使用包括氘氣的載氣,由於處於氘氣的環境中,能夠使形成的磊晶層內部存有氘原子,在後續閘氧化層或裝置的形成時,氘原子能夠擴散出,並與介面處等懸鍵進行結合,形成較為穩定的結構,從而避免載子的穿透,提高裝置的性能。
上述僅為本發明之較佳實施例,其內容係為了詳細說明本發明,但並非意欲限制本發明。熟習本領域之技藝者可理解,在不悖離後附申請專利範圍所界定之範疇下針對本發明所進行之各種變化或修改係落入本發明之一部分。
S100‧‧‧提供矽基板
S200‧‧‧在所述矽基板表面形成一層磊晶層,所述磊晶層採用氣相沉積法形成,其中載氣包括氘氣

Claims (10)

  1. 一種磊晶層的形成方法,其特徵在於,包括步驟:提供矽基板;在所述矽基板表面形成一層磊晶層,所述磊晶層採用氣相沉積法形成,其中載氣包括氘氣。
  2. 如申請專利範圍第1項所述的磊晶層的形成方法,其特徵在於,所述氣相沉積法的溫度範圍為800℃~1100℃。
  3. 如申請專利範圍第1項所述的磊晶層的形成方法,其特徵在於,所述氣相沉積法使用的載氣為氘氣和氫氣的混合氣體。
  4. 如申請專利範圍第3項所述的磊晶層的形成方法,其特徵在於,所述氘氣佔的比例範圍為1%~100%。
  5. 如申請專利範圍第1項所述的磊晶層的形成方法,其特徵在於,所述氣相沉積法使用的載氣為氘氣。
  6. 如申請專利範圍第1項所述的磊晶層的形成方法,其特徵在於,所述磊晶層為單晶矽。
  7. 如申請專利範圍第6項所述的磊晶層的形成方法,其特徵在於,所述氣相沉積法使用的反應氣體為包含矽元素的氣體。
  8. 如申請專利範圍第7項所述的磊晶層的形成方法,其特徵在於,所述氣相沉積法使用的反應氣體為SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4或Si(CH3)4
  9. 如申請專利範圍第1項所述的磊晶層的形成方法,其特徵在於,提供所述矽基板之後,在形成磊晶層之前,還包括步驟:去除所述矽基板表面的自然氧化層;對所述矽基板進行清洗。
  10. 如權利要求9所述的磊晶層的形成方法,其特徵在於,採用濕式蝕刻或乾式蝕刻去除所述矽基板表面的自然氧化層。
TW105106530A 2015-10-12 2016-03-03 磊晶層的形成方法 TWI619149B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510658742.8A CN106571287A (zh) 2015-10-12 2015-10-12 外延层的形成方法
??201510658742.8 2015-10-12

Publications (2)

Publication Number Publication Date
TW201714206A true TW201714206A (zh) 2017-04-16
TWI619149B TWI619149B (zh) 2018-03-21

Family

ID=58405283

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105106530A TWI619149B (zh) 2015-10-12 2016-03-03 磊晶層的形成方法

Country Status (6)

Country Link
US (1) US20170103887A1 (zh)
JP (1) JP2017076774A (zh)
KR (1) KR20170043083A (zh)
CN (1) CN106571287A (zh)
DE (1) DE102016113402A1 (zh)
TW (1) TWI619149B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109306467B (zh) * 2017-07-26 2020-10-16 上海新昇半导体科技有限公司 气相生长装置及气相生长方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126628A (ja) * 1985-11-28 1987-06-08 Fujitsu Ltd 半導体装置の製造方法
JPH02244613A (ja) * 1989-03-16 1990-09-28 Fujitsu Ltd 光cvd方法
JP3194547B2 (ja) * 1992-12-04 2001-07-30 キヤノン株式会社 多結晶シリコン層の製造方法
DE19581590T1 (de) * 1994-03-25 1997-04-17 Amoco Enron Solar Erhöhung eines Stabilitätsverhaltens von Vorrichtungen auf der Grundlage von amorphem Silizium, die durch Plasmaablagerung unter hochgradiger Wasserstoffverdünnung bei niedrigerer Temperatur hergestellt werden
JP3441534B2 (ja) * 1994-11-11 2003-09-02 大阪瓦斯株式会社 結晶性シリコンの形成方法
JP2701793B2 (ja) * 1995-06-15 1998-01-21 日本電気株式会社 半導体装置の製造方法
US5872387A (en) * 1996-01-16 1999-02-16 The Board Of Trustees Of The University Of Illinois Deuterium-treated semiconductor devices
KR20000057747A (ko) * 1999-01-14 2000-09-25 루센트 테크놀러지스 인크 실리콘 집적 회로의 제조 방법
US20040007733A1 (en) * 2002-06-26 2004-01-15 Macronix International Co., Ltd. Floating gate memory cell and forming method
EP1643544A4 (en) * 2003-06-26 2009-07-01 Shinetsu Handotai Kk METHOD FOR MANUFACTURING EPITAXIAL SILICON WAFER AND EPITAXIAL SILICON WAFER
CN100452319C (zh) * 2006-07-14 2009-01-14 上海华虹Nec电子有限公司 低等离子体诱生损伤的硅化物制备方法
CN100468693C (zh) * 2006-09-04 2009-03-11 中芯国际集成电路制造(上海)有限公司 接触孔的填充方法
WO2011078399A1 (ja) * 2009-12-25 2011-06-30 独立行政法人科学技術振興機構 結晶性コバルトシリサイド膜の形成方法
US8809168B2 (en) * 2011-02-14 2014-08-19 International Business Machines Corporation Growing compressively strained silicon directly on silicon at low temperatures
US9178042B2 (en) * 2013-01-08 2015-11-03 Globalfoundries Inc Crystalline thin-film transistor
CN103928319A (zh) * 2014-04-08 2014-07-16 上海华力微电子有限公司 锗硅外延生长方法

Also Published As

Publication number Publication date
KR20170043083A (ko) 2017-04-20
TWI619149B (zh) 2018-03-21
US20170103887A1 (en) 2017-04-13
DE102016113402A1 (de) 2017-04-13
CN106571287A (zh) 2017-04-19
JP2017076774A (ja) 2017-04-20

Similar Documents

Publication Publication Date Title
JP2007123875A (ja) 多孔質層を用いてゲルマニウム・オン・インシュレータ半導体構造を形成するための方法及びこれらの方法によって形成される半導体構造
CN102386067A (zh) 有效抑制自掺杂效应的外延生长方法
JP2008153545A (ja) 歪Si基板の製造方法
CN105448914B (zh) 半导体结构及其形成方法
TWI728798B (zh) 一種半導體薄膜平坦度改善的方法
JP3454033B2 (ja) シリコンウェーハおよびその製造方法
TWI593023B (zh) 晶圓的形成方法
US20060138540A1 (en) Semiconductor wafer having a semiconductor layer and an electrically insulating layer beneath it, and process for producing it
TW201714206A (zh) 磊晶層的形成方法
JP2005210071A (ja) 半導体基板ならびにその製造方法
JP2007300115A (ja) 層構造の製造方法
TW201715652A (zh) Cmos結構其製備方法
Wang et al. Homoepitaxy of Ge on ozone-treated Ge (1 0 0) substrate by ultra-high vacuum chemical vapor deposition
US9349814B2 (en) Gate height uniformity in semiconductor devices
JP5336070B2 (ja) 選択エピタキシャル成長プロセスの改良方法
JP4120163B2 (ja) Siエピタキシャルウェーハの製造方法及びSiエピタキシャルウェーハ
TW201833996A (zh) 在鰭式場效電晶體(finfet)裝置上形成共形磊晶半導體覆層材料之方法
JP3288675B2 (ja) 半導体基板上に窒化された界面を形成するための方法
JP2013051348A (ja) エピタキシャルウェーハ及びその製造方法
KR100878733B1 (ko) Simox 웨이퍼의 제조 방법
JP2004103688A (ja) 絶縁膜の形成方法およびゲート絶縁膜
JP2007250676A (ja) 異種材料の積層基板の製造方法
EP4213179A1 (en) Method for manufacturing soi wafer, and soi wafer
TWI605524B (zh) 半導體結構及其形成方法
JP2022067962A (ja) Soiウェーハの製造方法及びsoiウェーハ