TW201707111A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TW201707111A
TW201707111A TW105117446A TW105117446A TW201707111A TW 201707111 A TW201707111 A TW 201707111A TW 105117446 A TW105117446 A TW 105117446A TW 105117446 A TW105117446 A TW 105117446A TW 201707111 A TW201707111 A TW 201707111A
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Taiwan
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insulating film
forming
semiconductor device
trench
manufacturing
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TW105117446A
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English (en)
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篠原正昭
德光成太
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瑞薩電子股份有限公司
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Publication of TW201707111A publication Critical patent/TW201707111A/zh

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Abstract

本發明提供一種能夠利用簡單之製程抑制電晶體特性不均之半導體裝置之製造方法。 本發明係半導體裝置之製造方法，其具備：形成複數個閘極電極之步驟；以埋入於複數個閘極電極間之方式於複數個閘極電極上形成第1絕緣膜之步驟；於第1絕緣膜上形成第2絕緣膜之步驟；於第2絕緣膜上形成第3絕緣膜之步驟；於第3絕緣膜上形成感光體圖案之步驟；藉由將感光體圖案作為遮罩進行蝕刻，而形成貫通第1至第3絕緣膜並到達半導體基板之溝槽之步驟；去除感光體圖案之步驟；藉由將露出之第3絕緣膜作為遮罩進行蝕刻，而使溝槽延伸至半導體基板之內部之步驟；去除第3絕緣膜與第2絕緣膜之步驟；及於溝槽內與第1絕緣膜上形成第4絕緣膜之步驟。

Description

半導體裝置之製造方法
本發明係關於一種半導體裝置之製造方法，尤其是關於一種具有溝槽之半導體裝置之製造方法。
於高縱橫比之溝槽內填充有絕緣膜之元件隔離(Deep Trench Isolation：DTI，深溝槽隔離)構造，例如揭示於日本專利特開2011-151121號公報。
於該公報所記載之技術中，完成於半導體基板之表面具有源極區域及汲極區域之高耐受電壓MOS(Metal Oxide Semiconductor，金屬氧化物半導體)電晶體。於半導體基板之表面形成有俯視下包圍該電晶體之溝槽。以覆蓋於該電晶體上之方式，且以於溝槽內形成中空之方式於電晶體上及溝槽形成有絕緣膜。
如上所述，於形成DTI構造後，於半導體基板形成MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金屬氧化物半導體場效應電晶體)等電子元件。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2011-151121號公報
另一方面，於形成溝槽時，於電晶體之閘極上形成氧化膜，且將該氧化膜作為遮罩，藉由各向異性蝕刻而形成溝槽。而且，其後以於溝槽內部形成中空之方式形成絕緣膜。
於該各向異性蝕刻時，氧化膜亦被蝕刻去除特定膜厚。該各向異性蝕刻後之氧化膜之膜厚於晶圓面內變得不均。該絕緣膜之膜厚之不均會使於形成接點時產生層間的不均，亦成為電晶體特性之不均之原因。
其他課題與新穎特徵可自本說明書之記載及隨附圖式變得明瞭。
根據一實施例，半導體裝置之製造方法具備：於半導體基板之主表面形成複數個閘極電極之步驟；及以埋入於複數個閘極電極間之方式於複數個閘極電極上形成第1絕緣膜之步驟。進而具備：於第1絕緣膜上形成材質與第1絕緣膜不同之第2絕緣膜之步驟；及於第2絕緣膜上形成材質與第2絕緣膜不同之第3絕緣膜。進而具備如下步驟：於第3絕緣膜上形成感光體圖案之步驟；及藉由將感光體圖案作為遮罩進行蝕刻，而形成貫通第1至第3絕緣膜並到達半導體基板之溝槽之步驟。進而具備：以第3絕緣膜露出之方式去除感光體圖案之步驟；藉由將露出之第3絕緣膜作為遮罩進行蝕刻，而使溝槽延伸至半導體基板之內部之步驟；去除第3絕緣膜與第2絕緣膜之步驟；及以於溝槽內產生中空空間之方式於溝槽內與第1絕緣膜上形成第4絕緣膜之步驟。
根據一實施例，於將第3絕緣膜作為遮罩進行蝕刻後，去除第3絕緣膜與第2絕緣膜，因此能夠去除晶圓面內之絕緣膜之不均部分。藉此，能夠抑制絕緣膜之膜厚之不均而抑制電晶體之特性的不均。
1‧‧‧半導體基板
28‧‧‧抗蝕劑圖案
29‧‧‧開口部
30‧‧‧溝槽
31‧‧‧凹凸部
BIL‧‧‧埋入絕緣膜
CG‧‧‧控制閘極電極層
CH‧‧‧接觸孔
CP‧‧‧半導體晶片
DFR‧‧‧元件形成區域
DR‧‧‧n+汲極區域
DTR‧‧‧溝槽(第1溝槽)
DTRA‧‧‧溝槽
EP1‧‧‧p-磊晶區域
EP2‧‧‧p-磊晶區域
FG‧‧‧浮動閘極電極層
GBI‧‧‧閘極間絕緣膜
GE‧‧‧閘極電極層
GI‧‧‧閘極絕緣膜
HV‧‧‧輸出驅動器部
ICL‧‧‧配線層
II‧‧‧絕緣膜
IL1‧‧‧絕緣膜
IL2‧‧‧絕緣膜
IIA‧‧‧絕緣膜(「第4絕緣膜」)
LG‧‧‧邏輯部
MK‧‧‧遮罩材
MK1‧‧‧遮罩材(「第1絕緣膜」)
MK2‧‧‧遮罩材(「第3絕緣膜」)
NBR‧‧‧n型埋入區域
NCR‧‧‧n+接點區域
NDR‧‧‧n型沈降區域
NOR‧‧‧n型偏移區域
NR‧‧‧絕緣膜(「第2絕緣膜」)
NR1‧‧‧絕緣膜(「第2絕緣膜」)
NR2‧‧‧絕緣膜(「第5絕緣膜」)
NWR‧‧‧n型井區域
PBR‧‧‧p型埋入區域
PCR‧‧‧p+接點區域
PDR‧‧‧p型沈降區域
PL‧‧‧插頭導電層
POR‧‧‧p型偏移區域
PR‧‧‧p型區域
PRE‧‧‧抗蝕劑圖案(「感光體圖案」)
PWR‧‧‧p型井區域
SC‧‧‧矽化物層
SO‧‧‧n+源極區域
SP‧‧‧中空(空隙)
STR‧‧‧溝槽(第2溝槽)
SUB‧‧‧半導體基板
SW‧‧‧側壁絕緣層
S/D‧‧‧源極/汲極區域
W‧‧‧寬度
圖1係說明基於實施形態1之晶片狀態之半導體裝置之構成的概略俯視圖。
圖2係表示圖1所示之元件形成區域於俯視下被溝槽包圍之情況之局部切開立體圖。
圖3係表示圖2中被溝槽包圍之元件、且為實施形態1中之半導體裝置之構成之概略剖視圖。
圖4係表示基於實施形態1之半導體裝置之製造方法之第1步驟的概略剖視圖。
圖5係表示基於實施形態1之半導體裝置之製造方法之第2步驟的概略剖視圖。
圖6係表示基於實施形態1之半導體裝置之製造方法之第3步驟的概略剖視圖。
圖7係表示基於實施形態1之半導體裝置之製造方法之第4步驟的概略剖視圖。
圖8係表示基於實施形態1之半導體裝置之製造方法之第5步驟的概略剖視圖。
圖9係表示基於實施形態1之半導體裝置之製造方法之第6步驟的概略剖視圖。
圖10係表示基於實施形態1之半導體裝置之製造方法之第7步驟的概略剖視圖。
圖11係表示基於實施形態1之半導體裝置之製造方法之第8步驟的概略剖視圖。
圖12係表示基於實施形態1之半導體裝置之製造方法之第9步驟的概略剖視圖。
圖13係表示基於實施形態1之半導體裝置之製造方法之第10步驟的概略剖視圖。
圖14係模式性地表示作為比較例而於先前例之半導體基板之上表面形成有抗蝕劑圖案之狀態的剖視圖。
圖15係模式性地表示將抗蝕劑圖案作為遮罩進行蝕刻之狀態之剖視圖。
圖16係表示基於實施形態2之半導體裝置之製造方法之第2步驟的概略剖視圖。
圖17係模式性地說明基於實施形態2之半導體裝置之製造方法之第2步驟的圖。
圖18係表示基於實施形態2之半導體裝置之製造方法之第3步驟的概略剖視圖。
圖19係模式性地說明基於實施形態2之半導體裝置之製造方法之第3步驟的圖。
圖20係表示基於實施形態2之半導體裝置之製造方法之第4步驟的概略剖視圖。
圖21係模式性地說明基於實施形態2之半導體裝置之製造方法之第4步驟的圖。
圖22係表示基於實施形態2之半導體裝置之製造方法之第5步驟的概略剖視圖。
圖23係模式性地說明基於實施形態2之半導體裝置之製造方法之第5步驟的圖。
圖24係表示基於實施形態2之半導體裝置之製造方法之第6步驟的概略剖視圖。
圖25係模式性地說明基於實施形態2之半導體裝置之製造方法之第6步驟的圖。
圖26係表示基於實施形態3之半導體裝置之製造方法之第2步驟的概略剖視圖。
圖27係模式性地說明基於實施形態3之半導體裝置之製造方法之第2步驟的圖。
圖28係表示基於實施形態3之半導體裝置之製造方法之第3步驟的概略剖視圖。
圖29係模式性地說明基於實施形態3之半導體裝置之製造方法之第3步驟的圖。
圖30係表示基於實施形態3之半導體裝置之製造方法之第4步驟的概略剖視圖。
圖31係模式性地說明基於實施形態3之半導體裝置之製造方法之第4步驟的圖。
圖32係表示基於實施形態3之半導體裝置之製造方法之第5步驟的概略剖視圖。
圖33係模式性地說明基於實施形態3之半導體裝置之製造方法之第5步驟的圖。
圖34係表示基於實施形態3之半導體裝置之製造方法之第6步驟的概略剖視圖。
圖35係模式性地說明基於實施形態3之半導體裝置之製造方法之第6步驟的圖。
圖36係表示基於實施形態4之半導體裝置之製造方法之第2步驟的概略剖視圖。
圖37係表示基於實施形態4之半導體裝置之製造方法之第3步驟的概略剖視圖。
圖38係表示基於實施形態4之半導體裝置之製造方法之第4步驟的概略剖視圖。
圖39係表示基於實施形態6之半導體裝置之製造方法之追加步驟的概略剖視圖。
一面參照圖式一面對實施形態進行詳細說明。再者，對圖中相同或相當部分標註相同符號，不重複其之說明。
(實施形態1)
圖1係說明基於實施形態1之晶片狀態之半導體裝置之構成的概略俯視圖。
參照圖1，BiC-DMOS(Bipolar Complementary Double-diffused Metal Oxide Semiconductor，雙極互補雙擴散金屬氧化物半導體)之半導體晶片CP例如具有：邏輯部LG，其係將低耐受電壓之CMOS(Complementary MOS，互補金氧半導體)電晶體積體而成；及輸出驅動器部HV，其使用有高耐受電壓元件。於上述邏輯部LG中，該邏輯部LG之形成區域於俯視下被形成DTI構造之溝槽DTR包圍。又，於輸出驅動器部HV中，元件之一個個形成區域於俯視下被形成DTI構造之溝槽DTR包圍。
圖2係表示圖1所示之元件形成區域於俯視下被溝槽包圍之情況的局部切開立體圖。
參照圖2，例如於輸出驅動器部HV中，一個個高耐受電壓元件之元件形成區域DFR於俯視下被形成DTI構造之溝槽DTR包圍。該溝槽DTR形成於半導體基板SUB之表面。
其次，對使用高耐受電壓之橫置式MOS電晶體作為上述高耐受電壓元件之情形進行說明。
圖3係表示圖2中被溝槽包圍之元件、且為實施形態1中之半導體裝置之構成之概略剖視圖。
參照圖3，半導體基板SUB例如包含矽，於主表面選擇性地具有溝槽STR。於該溝槽STR內形成有埋入絕緣膜BIL。藉由該溝槽STR與埋入絕緣膜BIL而形成STI(Shallow Trench Isolation，淺溝隔離)構造。
於半導體基板SUB之p型區域PR上形成有p-磊晶區域EP1、及n型埋入區域NBR。於n型埋入區域NBR上選擇性地形成有p型埋入區域PBR。於該等n型埋入區域NBR及p型埋入區域PBR上形成有p-磊晶區域EP2。
於上述p-磊晶區域EP2內且半導體基板SUB之表面形成有高耐受電壓之橫置式MOS電晶體。該高耐受電壓之橫置式MOS電晶體主要具有n型偏移區域NOR、n型井區域NWR、p型井區域PWR、n+汲極區域DR、n+源極區域SO、閘極絕緣膜GI、及閘極電極層GE。
n型偏移區域NOR係以與p-磊晶區域EP2構成pn接面之方式形成於半導體基板SUB之表面。n型井區域NWR係以與n型偏移區域NOR相接之方式形成，n+汲極區域DR係以與n型井區域NWR相接之方式形成於半導體基板SUB之表面。
p型井區域PWR形成於p-磊晶區域EP2內且半導體基板SUB之表面。n+源極區域SO係以與p型井區域PWR構成pn接面之方式形成於半導體基板SUB之表面。於n+源極區域SO與n型偏移區域NOR之間，沿半導體基板SUB之表面隔著p型井區域PWR與p-磊晶區域EP2。
閘極電極層GE係以如下方式形成於半導體基板SUB上，即介隔閘極絕緣膜GI而和介於n+源極區域SO與n型偏移區域NOR之間之p型井區域PWR及p-磊晶區域EP2對向。又，閘極電極層GE之一端部接觸於形成於n型偏移區域NOR內之STI構造上。以沿著閘極電極層GE之側壁之方式形成有側壁絕緣層SW。
於實施形態中，較佳為於n+源極區域SO、n+汲極區域DR及閘極電極層GE之各者之表面上形成有矽化物層SC，亦可省略矽化物層SC。
又，於p-磊晶區域EP2內，以相接於p型埋入區域PBR之方式形成有p型沈降(sinker)區域PDR，且於該p型沈降區域PDR之半導體基板 SUB之表面側形成有p型井區域PWR與p+接點區域PCR。為了使p+接點區域PCR與n+源極區域SO電性分離，而於p+接點區域PCR與n+源極區域SO之間之半導體基板SUB的表面形成有STI構造。
又，於p-磊晶區域EP2內，以相接於n型埋入區域NBR之方式形成有n型沈降區域NDR，且於該n型沈降區域NDR之半導體基板SUB之表面側形成有n型井區域NWR與n+接點區域NCR。較佳為於n+接點區域NCR與p+接點區域PCR之各者之表面上形成有矽化物層SC，亦可省略矽化物層SC。
以覆蓋於上述高耐受電壓橫置式MOS電晶體上之方式，依序積層絕緣膜IL1、絕緣膜IL2、遮罩材MK及絕緣膜II。絕緣膜IL1例如為氧化矽膜，絕緣膜IL2例如為氮化矽膜。遮罩材MK例如為氧化矽膜。絕緣膜IL1、絕緣膜IL2、遮罩材MK係以埋入複數個閘極電極層GE之閘極電極間之方式形成於閘極電極層GE上。絕緣膜II係以覆蓋遮罩材MK之方式形成。
絕緣膜II例如由BP-TEOS(Boro-Phospho-Tetra-Ethyl-Ortho-Silicate，硼磷正矽酸乙酯)與利用電漿CVD(Chemical Vapor Deposition，化學氣相沈積)法而形成於其上之氧化矽膜之積層構造構成。再者，絕緣膜II所含之BP-TEOS(BPSG：Boro-Phosphate Silicate Glass，硼磷矽玻璃)只要為含有如P-TEOS(PSG：Phosphorus Silicon Glass，磷矽玻璃)、B-TEOS(BSG：Boro Silicata Glass，硼矽玻璃)之III族元素及V族元素之至少任一雜質之絕緣膜即可。
於絕緣膜IL1、絕緣膜IL2、遮罩材MK及絕緣膜II形成有接觸孔CH，於接觸孔CH內形成有插頭導電層PL。於絕緣膜II上形成有配線層ICL。配線層ICL經由接觸孔CH內之插頭導電層PL而與高耐受電壓橫置式MOS電晶體之導電部分(例如源極區域SO、n+汲極區域DR、接點區域NCR、PCR、閘極電極層GE等)電性連接。
以於俯視下包圍上述高耐受電壓橫置式MOS電晶體之形成區域之方式形成DTI構造。該DTI構造具有自半導體基板SUB之表面延伸至內部之溝槽(第1溝槽)DTR、及形成於該溝槽DTR內之絕緣膜II。溝槽DTR係以自半導體基板SUB之表面貫通p-磊晶區域EP2、n型埋入區域NBR及p-磊晶區域EP1到達p型區域PR之方式形成。
形成於上述溝槽DTR內之絕緣膜II係形成於高耐受電壓橫置式MOS電晶體上之層間絕緣膜。又，溝槽DTR內未完全被絕緣膜II填埋，於溝槽DTR之內部形成有中空(空隙)SP。
該中空SP較佳為至少形成於n型埋入區域NBR與p-磊晶區域EP1之接合部附近。中空SP亦可具有與溝槽之深度大致相同之高度。溝槽DTR之縱橫比(深度/寬度W)較佳為1以上。又，溝槽DTR之寬度W較佳為以80V之崩潰電壓為基準而為0.3μm以上。
又，溝槽DTR亦可形成於形成有STI構造之部位。於該情形時，溝槽DTR於形成有STI構造之溝槽(第2溝槽)STR之區域較該溝槽STR更深地形成。
其次，使用圖4~圖13，對作為基於實施形態1之半導體裝置之不僅具有高耐受電壓橫置式MOS電晶體，而且具有p通道MOS電晶體(稱為pMOS電晶體)、CMOS電晶體及非揮發性半導體記憶體之半導體裝置之製造方法進行說明。
圖4係表示基於實施形態1之半導體裝置之製造方法之第1步驟的概略剖視圖。
參照圖4，首先於半導體基板SUB之表面完成各元件(高耐受電壓橫置式MOS電晶體、pMOS電晶體、CMOS電晶體、非揮發性半導體記憶元件)。
高耐受電壓橫置式MOS電晶體係以如下方式形成，即，具有n型偏移區域NOR、n型井區域NWR、p型井區域PWR、n+汲極區域DR、 n+源極區域SO、閘極絕緣膜GI、及閘極電極層GE。
又，作為高耐受電壓元件之pMOS電晶體係以如下方式形成，即，具有p型偏移區域POR、n型井區域NWR、p型井區域PWR、p+汲極區域DR、p+源極區域SO、閘極絕緣膜GI、及閘極電極層GE。
又，CMOS電晶體係以完成pMOS電晶體與nMOS電晶體之方式形成。pMOS電晶體係以具有n型井區域NWR、1對LDD(Lightly Doped Drain，輕摻雜汲極)構造之p型源極/汲極區域S/D、閘極絕緣膜GI、閘極電極層GE之方式形成。nMOS電晶體係以具有p型井區域PWR、1對LDD構造之n型源極/汲極區域S/D、閘極絕緣膜GI、及閘極電極層GE之方式形成。
又，非揮發性半導體記憶元件係例如由堆疊閘極型之記憶體電晶體形成。該堆疊閘極型之記憶體電晶體係以具有p型井區域PWR、LDD構造之n型汲極區域DR、n-源極區域SO、閘極絕緣膜GI、浮動閘極電極層FG、閘極間絕緣膜GBI、及控制閘極電極層CG之方式形成。
再者，亦可於各元件之源極區域、汲極區域等雜質區域之表面及閘極電極之表面形成矽化物層SC。又，以覆蓋各元件之閘極電極層GE、FG、CG之側壁之方式形成側壁絕緣層SW。
於本例中，於半導體基板SUB上，於各元件形成有複數個閘極電極。
圖5係表示基於實施形態1之半導體裝置之製造方法之第2步驟的概略剖視圖。
參照圖5，以覆蓋於各元件上之方式，依序積層絕緣膜IL1、絕緣膜IL2及遮罩材MK1(「第1絕緣膜」)、絕緣膜NR(「第2絕緣膜」)、遮罩材MK2(「第3絕緣膜」)。絕緣膜IL1例如由20nm之厚度之非摻雜之氧化矽膜形成。又，絕緣膜IL2例如由50nm之厚度之氮化矽膜形 成。遮罩材MK1例如由200nm之厚度之非摻雜之氧化矽膜形成。絕緣膜NR例如由50nm之厚度之氮化矽膜形成。又，遮罩材MK2例如由800nm之厚度之非摻雜之氧化矽膜形成。遮罩材MK1與遮罩材MK2可為相同材質之氧化矽膜，亦可設為互不相同之氧化矽膜。
於該遮罩材MK2上塗佈抗蝕劑圖案PRE(「感光體圖案」)。再者，於本例中，作為絕緣膜列舉氮化矽膜之例進行說明，但除氮化矽膜以外，亦可使用氮化氧化矽膜、含碳之氮化矽膜、碳氮化矽膜。
遮罩材MK1係以埋入複數個閘極電極間之方式形成於複數個閘極電極上。
因此，成為於遮罩材MK1與遮罩材MK2之間隔著絕緣膜NR之構造。
再者，於積層遮罩材MK2(「第3絕緣膜」)之後，於本例中，例如利用(Chemical Mechanical Polishing)法研磨去除上表面而使之平坦化。
藉由平坦化而能夠使抗蝕劑圖案PRE之形狀穩定化。再者，於本例中，對藉由CMP(Chemical Mechanical Polishing，化學機械研磨)法進行研磨去除之情形進行說明，但亦可不進行研磨去除。
圖6係表示基於實施形態1之半導體裝置之製造方法之第3步驟的概略剖視圖。
參照圖6，抗蝕劑圖案PRE係藉由通常之照相製版技術而圖案化。將該圖案化之抗蝕劑圖案PRE作為遮罩，依序對遮罩材MK2、絕緣膜NR、遮罩材MK1、絕緣膜IL2、絕緣膜IL1及STI構造進行各向異性蝕刻。藉此於半導體基板SUB之表面形成溝槽DTRA。
圖7係表示基於實施形態1之半導體裝置之製造方法之第4步驟的概略剖視圖。
參照圖7，藉由灰化等去除抗蝕劑圖案PRE(「感光體圖案」)。 藉此使形成於抗蝕劑圖案PRE之下之遮罩材MK2露出。
圖8係表示基於實施形態1之半導體裝置之製造方法之第5步驟的概略剖視圖。
參照圖8，繼而將遮罩材MK2(「第3絕緣膜」)作為遮罩對半導體基板SUB實施各向異性蝕刻。藉此，形成自半導體基板SUB之表面貫通p-磊晶區域EP2、n型埋入區域NBR及p-磊晶區域EP1而到達p型區域PR之溝槽DTR。
於該各向異性蝕刻時，遮罩材MK2亦被蝕刻去除特定膜厚而成為最初之厚度之300nm之厚度。
圖9係表示實施形態1之半導體裝置之製造方法之第6步驟的概略剖視圖。
參照圖9，藉由各向異性蝕刻去除遮罩材MK2，又，藉由各向同性蝕刻或各向異性蝕刻而去除絕緣膜NR。再者，各向異性蝕刻係藉由乾式蝕刻而進行。再者，各向同性蝕刻係藉由乾式或濕式蝕刻而進行。
遮罩材MK2(「第3絕緣膜」)之去除係將絕緣膜NR(「第2絕緣膜」)作為終止層而進行去除。又，絕緣膜NR之去除係將遮罩材MK1作為終止層而進行去除。
藉由去除該遮罩材MK2及絕緣膜NR，能夠清除上述第5步驟中為形成溝槽DTR而將遮罩材MK2作為遮罩進行蝕刻時之硬質遮罩之殘膜不均。
藉由去除上述遮罩材MK2及絕緣膜NR，而使遮罩材MK1之上表面露出，由於藉由各向異性蝕刻去除遮罩材MK2，故而不會出現於溝槽DTR之壁面露出之STI構造之埋入絕緣膜BIL於圖中橫方向上發生膜減少的情況(不後退)。
圖10係表示基於實施形態1之半導體裝置之製造方法之第7步驟 的概略剖視圖。
參照圖10，以覆蓋於各元件上之方式，且以於溝槽DTR內形成中空SP之方式，於各元件上及溝槽DTR內形成絕緣膜IIA(「第4絕緣膜」)。該絕緣膜IIA例如由1450nm之厚度之BP-TEOS形成。藉由CMP(Chemical Mechanical Polishing)法而使該絕緣膜IIA之上表面平坦化。藉此絕緣膜IIA之厚度例如成為750nm。
圖11係表示基於實施形態1之半導體裝置之製造方法之第8步驟的概略剖視圖。
參照圖11，藉由電漿CVD法而於上述絕緣膜IIA上形成氧化矽膜。藉由該絕緣膜IIA與利用電漿CVD法所得之氧化矽膜而形成絕緣膜II。
圖12係表示基於實施形態1之半導體裝置之製造方法之第9步驟的概略剖視圖。
參照圖12，藉由通常之照相製版技術及蝕刻技術而形成貫通絕緣膜II、絕緣膜IL2及絕緣膜IL1並到達半導體基板SUB之表面之接觸孔CH。自該接觸孔CH露出例如形成於源極區域或汲極區域等之表面之矽化物層SC之表面。
圖13係表示基於實施形態1之半導體裝置之製造方法之第10步驟的概略剖視圖。
參照圖13，於接觸孔CH內形成插頭導電層PL。其後，以經由插頭導電層PL而與各元件之導電部分電性連接之方式於絕緣膜II上形成配線層ICL。
藉由以上步驟而製造出實施形態之半導體裝置。
對實施形態1之作用效果進行說明。
於上述實施形態1中，於遮罩材MK1之上形成絕緣膜NR。然後，於該絕緣膜NR之上形成遮罩材MK2。形成溝槽DTR時利用遮罩材 MK2作為硬質遮罩，但可藉由將絕緣膜NR作為終止層進行蝕刻處理而清除此時產生之殘膜不均。然後，藉由去除絕緣膜NR而使遮罩材MK1露出。由於遮罩材MK1之膜厚之不均較小，故而能夠降低形成接點時之層間之不均。藉此，能夠抑制電晶體特性之不均。
(實施形態2)
於實施形態2中，對未設置斜面保護機構之情形時之半導體裝置之製造方法進行說明。
所謂半導體基板中之斜面部係形成於半導體基板(半導體晶圓)之主表面之周緣的傾斜部。傾斜部包含自基板之中央側朝向外端而剖面形狀中之主表面以直線狀傾斜之狀態、及以曲線狀傾斜之狀態。
圖14係模式性地表示作為比較例而於先前例之半導體基板之上表面形成有抗蝕劑圖案之狀態的剖視圖。
如圖14所示，於圖案化於半導體基板1之上表面之抗蝕劑圖案28形成有開口部29。抗蝕劑圖案28由於係對流動體進行旋轉塗佈而形成，故而難以形成於半導體基板1之斜面部。
圖15係模式性地表示將抗蝕劑圖案作為遮罩進行蝕刻之狀態之剖視圖。
如圖15所示，位於抗蝕劑圖案28之開口部29之正下方之半導體基板1藉由蝕刻而形成有溝槽30。此時，半導體基板1之斜面部因未被抗蝕劑圖案28覆蓋而被蝕刻，藉此形成有較大地凹陷之凹凸部31。該凹凸部31存在以具有鋸狀之形狀之方式，或者以具有銳利之面之方式形成的情況。於該情形時，存在如下情況，即於其後之步驟中對半導體基板1進行處理時、或搬送時，該具有鋸狀或銳利之面之凹凸部31自半導體基板1脫落而成為數10μm的大小之異物。於該異物附著於半導體元件之情形時，存在使該半導體元件之功能下降之可能性。
於實施形態2中，對即便於未設置斜面保護機構之情形時亦能夠 以簡單之製程保護斜面部之半導體裝置的製造方法進行說明。
其次，利用圖16~圖25對基於實施形態2之半導體裝置之製造方法進行說明。
由於基於實施形態2之半導體裝置之製造方法之第1步驟與實施形態1之圖4中說明的第1步驟相同，故而不重複對其進行說明。
圖16係表示基於實施形態2之半導體裝置之製造方法之第2步驟的概略剖視圖。
參照圖16，以覆蓋於各元件上之方式，依序積層絕緣膜IL1、絕緣膜IL2及遮罩材MK(「第1絕緣膜」)、絕緣膜NR1(「第2絕緣膜」)。絕緣膜IL1例如由20nm之厚度之非摻雜之氧化矽膜形成。又，絕緣膜IL2例如由50nm之厚度之氮化矽膜形成。遮罩材MK例如由1000nm之厚度之非摻雜之氧化矽膜形成。絕緣膜NR1例如由100nm之厚度之氮化矽膜形成。再者，於本例中，作為絕緣膜列舉氮化矽膜之例進行說明，但除氮化矽膜以外，亦可使用氮化氧化矽膜、含碳之氮化矽膜、碳氮化矽膜。
再者，遮罩材MK包含藉由於含臭氧之氣體氛圍中使有機材料反應而形成之氧化矽膜(臭氧TEOS(Tetra-Ethyl-Ortho-Silicate))、及藉由於電漿中使有機材料反應而形成之氧化矽膜(電漿TEOS)。
圖17係模式性地說明基於實施形態2之半導體裝置之製造方法之第2步驟的圖。
參照圖17，於第2步驟中，於半導體基板SUB之斜面部形成有遮罩材MK。又，絕緣膜NR1係以於斜面部上之遮罩材MK之上進一步覆蓋斜面部之方式形成。
圖18係表示基於實施形態2之半導體裝置之製造方法之第3步驟的概略剖視圖。
參照圖18，例如利用(Chemical Mechanical Polishing)法，研磨去 除絕緣膜NR1及遮罩材MK之上表面而使之平坦化。
圖19係模式性地說明基於實施形態2之半導體裝置之製造方法之第3步驟的圖。
參照圖19，於第3步驟中，利用CMP法研磨去除絕緣膜NR1及遮罩材MK之上表面，藉此使遮罩材MK1之上表面露出，並且於半導體基板SUB之斜面部殘留絕緣膜NR1。
圖20係表示基於實施形態2之半導體裝置之製造方法之第4步驟的概略剖視圖。
參照圖20，抗蝕劑圖案PRE(「感光體圖案」)係藉由通常之照相製版技術而圖案化。將該圖案化之抗蝕劑圖案PRE作為遮罩，依序對遮罩材MK、絕緣膜IL2、絕緣膜IL1及STI構造進行各向異性蝕刻。藉此於半導體基板SUB之表面形成溝槽DTRA。
圖21係模式性地說明基於實施形態2之半導體裝置之製造方法之第4步驟的圖。
參照圖21，於第3步驟中形成抗蝕劑圖案PRE。不於斜面部形成該抗蝕劑圖案PRE。
圖22係表示基於實施形態2之半導體裝置之製造方法之第5步驟的概略剖視圖。
參照圖22，藉由灰化等去除抗蝕劑圖案PRE。藉此使形成於抗蝕劑圖案PRE之下之遮罩材MK露出。
繼而，將遮罩材MK作為遮罩對半導體基板SUB實施各向異性蝕刻。藉此，形成自半導體基板SUB之表面貫通p-磊晶區域EP2、n型埋入區域NBR及p-磊晶區域EP1並到達p型區域PR之溝槽DTR。
圖23係模式性地說明基於實施形態2之半導體裝置之製造方法之第5步驟的圖。
參照圖23，藉由灰化等使遮罩材MK露出，並且亦將殘留於斜面 部之絕緣膜NR1去除。與斜面部對應之區域由於未形成抗蝕劑圖案PRE，故而藉由各向異性蝕刻而被除去，但由於係將殘留於半導體基板SUB之斜面部之絕緣膜NR1除去，故而半導體基板SUB受到保護。
圖24係表示基於實施形態2之半導體裝置之製造方法之第6步驟的概略剖視圖。
參照圖24，以覆蓋於各元件上之方式，且以於溝槽DTR內形成中空SP之方式於各元件上及溝槽DTR內形成有絕緣膜IIA。該絕緣膜IIA例如由1450nm之厚度之BP-TEOS形成。該絕緣膜IIA之上表面例如藉由CMP(Chemical Mechanical Polishing)法而平坦化。藉此絕緣膜IIA之厚度例如成為750nm。
圖25係模式性地說明基於實施形態2之半導體裝置之製造方法之第6步驟的圖。
參照圖25，於遮罩材MK之上形成有絕緣膜IIA。
關於其後之處理，與圖11~13中說明之步驟相同，因此不重複對其進行詳細說明。
根據以上，製造實施形態之半導體裝置。
對實施形態2之作用效果進行說明。
於上述實施形態2中，以覆蓋半導體基板SUB之斜面部之方式於遮罩材MK之上形成絕緣膜NR1。藉由各向異性蝕刻時殘留於斜面部之絕緣膜NR1而保護半導體基板SUB，從而能夠不蝕刻半導體基板SUB之斜面部。
藉此，能夠防止半導體基板SUB之斜面部以具有鋸狀之形狀之方式，或者以具有銳利之面之方式形成，從而能夠抑制產生異物，存在降低使半導體元件之功能下降之可能性之情況。
又，無需設置斜面保護機構，亦對成本有利。
(實施形態3)
於上述實施形態2中，對未設置斜面保護機構之情況之半導體裝置之製造方法進行了說明，如上所述，對第5步驟中藉由各向異性蝕刻而形成溝槽之情形進行了說明。於該步驟中，遮罩材MK亦被蝕刻去除特定膜厚，遮罩材MK之膜厚有於晶圓面內產生不均之可能性。
於實施形態3中，對如下半導體裝置之製造方法進行說明：即便於未設置斜面保護機構之情形時亦能夠利用簡單之製程保護斜面部，並且能夠抑制電晶體特性之不均。
其次，利用圖26~圖35，對基於實施形態3之半導體裝置之製造方法進行說明。
由於基於實施形態3之半導體裝置之製造方法之第1步驟與實施形態1之圖4中說明的第1步驟相同，故而不重複對其進行詳細說明。
圖26係表示基於實施形態3之半導體裝置之製造方法之第2步驟的概略剖視圖。
參照圖26，以覆蓋於各元件上之方式，依序積層絕緣膜IL1、絕緣膜IL2及遮罩材MK1、絕緣膜NR1、遮罩材MK2(「第3絕緣膜」)、絕緣膜NR2(「第5絕緣膜」)。絕緣膜IL1例如由20nm之厚度之非摻雜之氧化矽膜形成。又，絕緣膜IL2例如由50nm之厚度之氮化矽膜形成。
遮罩材MK1例如由200nm之厚度之非摻雜之氧化矽膜形成。絕緣膜NR1例如由50nm之厚度之氮化矽膜形成。又，遮罩材MK2例如由800nm之厚度之非摻雜之氧化矽膜形成。絕緣膜NR2例如由100nm之厚度之氮化矽膜形成。
再者，於本例中，作為絕緣膜列舉氮化矽膜之例進行說明，但除氮化矽膜以外，亦可使用氮化氧化矽膜、含碳氮化矽膜、碳氮化矽膜。
圖27係模式性地說明基於實施形態3之半導體裝置之製造方法之 第2步驟的圖。
參照圖27，於第2步驟中，於半導體基板SUB之斜面部形成有遮罩材MK1、絕緣膜NR1、遮罩材MK2。又，絕緣膜NR2係以於斜面部上之遮罩材MK2之上進一步覆蓋斜面部之方式形成。再者，此處，為了簡化說明，示出遮罩材MK2及設置於其上之絕緣膜NR2。
圖28係表示基於實施形態3之半導體裝置之製造方法之第3步驟的概略剖視圖。
參照圖28，例如藉由(Chemical Mechanical Polishing)法研磨去除絕緣膜NR2及遮罩材MK2之上表面而使之平坦化。
圖29係模式性地說明基於實施形態3之半導體裝置之製造方法之第3步驟的圖。
參照圖29，於第3步驟中，藉由利用CMP法研磨去除絕緣膜NR2及遮罩材MK2之上表面，而使遮罩材MK2之上表面露出，並且於半導體基板SUB之斜面部殘留絕緣膜NR2。
圖30係表示基於實施形態3之半導體裝置之製造方法之第4步驟的概略剖視圖。
參照圖30，抗蝕劑圖案PRE係藉由通常之照相製版技術而圖案化。將該圖案化之抗蝕劑圖案(感光體圖案)PRE作為遮罩，依序對遮罩材MK2、絕緣膜NR1、遮罩材MK1、絕緣膜IL2、絕緣膜IL1及STI構造進行各向異性蝕刻。藉此貫通遮罩材MK2、絕緣膜NR1、絕緣膜IL2、絕緣膜IL1而於半導體基板SUB之表面形成溝槽DTRA。
圖31係模式性地說明基於實施形態3之半導體裝置之製造方法之第4步驟的圖。
參照圖31，於第3步驟中，形成抗蝕劑圖案PRE。於斜面部未形成該抗蝕劑圖案PRE。
圖32係表示基於實施形態3之半導體裝置之製造方法之第5步驟 的概略剖視圖。
參照圖32，藉由灰化等去除抗蝕劑圖案PRE。藉此使形成於抗蝕劑圖案PRE之下之遮罩材MK2露出。
繼而，將遮罩材MK2作為遮罩對半導體基板SUB實施各向異性蝕刻。藉此，形成自半導體基板SUB之表面貫通p-磊晶區域EP2、n型埋入區域NBR及p-磊晶區域EP1並到達p型區域PR之溝槽DTR。
圖33係模式性地說明基於實施形態3之半導體裝置之製造方法之第5步驟的圖。
參照圖33，藉由灰化等使遮罩材MK2露出，並且亦將殘留於斜面部之絕緣膜NR1去除。與斜面部對應之區域由於未形成抗蝕劑圖案PRE，故而藉由各向異性蝕刻而被除去，但由於係將殘留於半導體基板SUB之斜面部之絕緣膜NR1除去，故而半導體基板SUB受到保護。
圖34係表示基於實施形態3之半導體裝置之製造方法之第6步驟的概略剖視圖。
參照圖34，藉由各向異性蝕刻而去除遮罩材MK2，又，藉由各向同性蝕刻或各向異性蝕刻而去除絕緣膜NR1。再者，各向異性蝕刻係藉由乾式蝕刻進行。再者，各向同性蝕刻係藉由乾式或濕式蝕刻進行。
遮罩材MK2之去除係將絕緣膜NR1作為終止層而進行去除。又，絕緣膜NR1之去除係將遮罩材MK1作為終止層而進行去除。
藉由去除該遮罩材MK2及絕緣膜NR1，能夠清除上述第5步驟中為形成溝槽DTR而將遮罩材MK2作為遮罩進行蝕刻時之硬質遮罩之殘膜不均。
藉由去除上述遮罩材MK2及絕緣膜NR1，而使遮罩材MK1之上表面露出，由於利用各向異性蝕刻去除遮罩材MK2，故而不會有於溝槽DTR之壁面露出之STI構造之埋入絕緣膜BIL於圖中橫方向上產生膜減 少的情況(不後退)。
圖35係模式性地說明基於實施形態3之半導體裝置之製造方法之第6步驟的圖。
參照圖35，藉由去除遮罩材MK2及絕緣膜NR1，而使遮罩材MK1於半導體基板SUB上露出。
關於其後之處理，與圖10~13中說明之步驟相同，因此不重複對其進行詳細說明。
根據以上，製造實施形態之半導體裝置。
對實施形態3之作用效果進行說明。
於上述實施形態3中，於半導體基板SUB之斜面部形成遮罩材MK2。而且，以覆蓋斜面部之方式於遮罩材MK2之上形成絕緣膜NR2。於絕緣膜NR2之上形成抗蝕劑圖案。將抗蝕劑圖案作為遮罩形成溝槽。於形成溝槽之各向異性蝕刻時殘留於斜面部之絕緣膜NR2能夠保護斜面部，從而不蝕刻半導體基板SUB之斜面部。
藉此，能夠防止半導體基板SUB之斜面部以具有鋸狀之形狀之方式，或者以具有銳利之面之方式形成的情況，從而抑制產生異物，存在降低使半導體元件之功能下降之可能性之情況。
又，無需設置斜面保護機構，亦對成本有利。
於上述實施形態3中，於遮罩材MK1之上形成絕緣膜NR1。而且，於該絕緣膜NR1之上形成遮罩材MK2。形成溝槽DTR時，利用遮罩材MK2作為硬質遮罩，但可藉由將絕緣膜NR1作為終止層進行蝕刻處理而清除此時產生之殘膜不均。而且，藉由去除絕緣膜NR1而使遮罩材MK1露出。由於遮罩材MK1之膜厚之不均較小，故而能夠降低形成接點時之層間之不均。藉此，能夠抑制電晶體特性之不均。
(實施形態4)
於上述實施形態1中，對於將遮罩材作為硬質遮罩之情形時減少 殘膜不均之方式進行了說明。
於實施形態4中，對藉由更簡單之方式抑制電晶體之特性不均的方式進行說明。
其次，利用圖36~圖38，對基於實施形態4之半導體裝置之製造方法進行說明。
基於實施形態4之半導體裝置之製造方法之第1步驟與實施形態1之圖4中說明的第1步驟相同，因此不重複對其進行詳細說明。
圖36係表示基於實施形態4之半導體裝置之製造方法之第2步驟的概略剖視圖。
參照圖36，以覆蓋於各元件上之方式，依序積層絕緣膜IL1、絕緣膜IL2及遮罩材MK(「第1絕緣膜」)、抗蝕劑圖案PRE(「感光體圖案」)。絕緣膜IL1例如由20nm之厚度之非摻雜之氧化矽膜形成。又，絕緣膜IL2例如由50nm之厚度之氮化矽膜形成。
遮罩材MK例如由200nm之厚度之非摻雜之氧化矽膜形成。
圖37係表示基於實施形態4之半導體裝置之製造方法之第3步驟的概略剖視圖。
參照圖37，抗蝕劑圖案PRE係藉由通常之照相製版技術而圖案化。將該圖案化之抗蝕劑圖案(感光體圖案)PRE作為遮罩，依序對遮罩材MK、絕緣膜IL2、絕緣膜IL1、STI構造、及半導體基板SUB進行各向異性蝕刻。藉此，形成自半導體基板SUB之表面貫通基盤內部之p-磊晶區域EP2、n型埋入區域NBR及p-磊晶區域EP1並延伸至p型區域PR之溝槽DTR。再者，於形成深度相對於寬度之比即縱橫比較大之溝槽DTR的情形時，實施利用所謂之波希法(bosch process)之蝕刻處理。重複進行如下步驟：例如，使用含六氟化硫(SF6)氣體之氣體蝕刻半導體基板SUB；例如，使用含C4F8氣體等氟碳(fluorocarbon)氣體之氣體被覆溝槽DTR之側面。
圖38係表示基於實施形態4之半導體裝置之製造方法之第4步驟的概略剖視圖。
參照圖38，藉由灰化等去除抗蝕劑圖案PRE。藉此使形成於抗蝕劑圖案PRE之下之遮罩材MK露出。
關於其後之處理，與圖10~13中說明之步驟相同，因此不重複對其進行詳細說明。
根據以上，製造實施形態之半導體裝置。
對實施形態4之作用效果進行說明。
於上述實施形態4中，將抗蝕劑圖案PRE作為遮罩形成溝槽DTR。
因此，由於不執行將遮罩材MK作為硬質遮罩之蝕刻處理，故而不會產生此時所產生之殘膜不均而能夠降低形成接點時之層間之不均。藉此，能夠抑制電晶體特性之不均。
又，由於能夠利用較上述實施形態更簡單之製程製造半導體裝置，因此能夠減少與製造製程相關之成本。
再者，於上述第2步驟中，亦可於將抗蝕劑圖案PRE積層於遮罩材MK之上之前藉由CMP法進行平坦化，然後製成抗蝕劑圖案PRE。藉此，能夠使底層平坦化，能夠使抗蝕劑圖案PRE之形狀穩定。
(實施形態5)
於實施形態5中，連同上述實施形態4中說明之簡單之製造製程一起，對即便於不設置斜面保護機構之情形時亦能夠利用簡單之製程保護斜面部的半導體裝置之製造方法進行說明。
基於實施形態5之半導體裝置之製造方法之第1步驟至第3步驟與實施形態2說明之圖16~圖19之步驟相同。
而且，基於實施形態5之半導體裝置之製造方法之第4步驟於實施形態2中說明之圖20之第4步驟時，如實施形態4說明般，將抗蝕劑 圖案PRE作為遮罩，依序對遮罩材MK、絕緣膜IL2、絕緣膜IL1、STI構造、及半導體基板SUB進行各向異性蝕刻。藉此，形成自半導體基板SUB之表面貫通p-磊晶區域EP2、n型埋入區域NBR及p-磊晶區域EP1並到達p型區域PR之溝槽DTR。
於形成深度相對於寬度之比之縱橫比較大之溝槽DTR的情形時，執行利用所謂之波希法之蝕刻處理。重複進行如下步驟：例如，使用含六氟化硫(SF6)氣體之氣體蝕刻半導體基板SUB；例如，使用含C4F8氣體等氟碳(fluorocarbon)氣體之氣體被覆溝槽DTR之側面。
對於其後之第5步驟之後的處理，係與實施形態中2說明之圖22~25中說明之步驟基本相同之步驟，因此不重複對其進行詳細說明。再者，於實施形態5中，將抗蝕劑圖案PRE作為遮罩形成溝槽DTR，因此不執行實施形態2之將第5步驟中之遮罩材MK作為硬質遮罩之蝕刻處理。
根據以上，製造實施形態5之半導體裝置。
對實施形態5之作用效果進行說明。
於上述實施形態5中，將抗蝕劑圖案PRE作為遮罩形成溝槽DTR。
因此，由於不執行將遮罩材MK作為硬質遮罩之蝕刻處理，故而不會產生此時所產生之殘膜不均而能夠降低形成接點時之層間之不均。藉此，能夠抑制電晶體特性之不均。
又，以覆蓋半導體基板SUB之斜面部之方式於遮罩材MK之上形成絕緣膜NR1。藉由各向異性蝕刻時殘留於斜面部之絕緣膜NR1能夠保護半導體基板SUB，從而不蝕刻半導體基板SUB之斜面部。
藉此，能夠防止半導體基板SUB之斜面部以具有鋸狀之形狀之方式，或者以具有銳利之面之方式形成的情況，從而抑制產生異物，存在降低使半導體元件之功能下降之可能性之情況。
又，無需設置斜面保護機構，亦對成本有利。
(實施形態6)
於上述實施形態中，對將遮罩材MK作為上端於溝槽DTR內形成中空SP之情形進行了說明。
另一方面，藉由使中空SP之位置降低而能夠使接點層間膜變薄。藉此，藉由防止接點形成不良而能夠降低電晶體特性之不均。
於實施形態6中，對進一步提高電晶體特性之半導體裝置之製造方法進行說明。
實施形態6之製造方法係於形成中空SP前，追加進一步去除遮罩材MK1之步驟。
圖39係表示基於實施形態6之半導體裝置之製造方法之追加步驟的概略剖視圖。
基於實施形態6之半導體裝置之製造方法之第1步驟至第6步驟，與實施形態1中說明之圖4~圖9之步驟相同。
參照圖39，藉由各向異性蝕刻而去除遮罩材MK1。具體而言，一方面殘留位於閘極電極層GE之側壁之遮罩材MK1及閘極電極間之遮罩材MK1，一方面將剩餘之區域之遮罩材MK1去除。藉此，去除溝槽DTR周圍之遮罩材MK1。
藉此，能夠使形成於溝槽DTR之中空SP之上端位置降低。
再者，各向異性蝕刻係藉由乾式蝕刻進行。理想的是進行至殘留於閘極電極層GE之側壁之遮罩材MK1之上端的位置位於較閘極電極層GE之上端更下側為止。
關於其後之第7步驟之後的處理，係與實施形態1中說明之圖10~13中說明之步驟基本相同之步驟，因此不重複對其進行詳細說明。
對實施形態6之作用效果進行說明。
於上述實施形態6中，於去除遮罩材MK2及絕緣膜NR之後，對遮 罩材MK1進行乾式蝕刻，藉此一方面殘留位於閘極電極層GE之側壁之遮罩材MK1之絕緣膜，一方面去除溝槽周圍之遮罩材MK1。而且，以覆蓋於各元件上之方式，且以於溝槽DTR內形成中空SP之方式於各元件上及溝槽DTR內形成絕緣膜IIA。
藉此能夠使形成於溝槽DTR之中空SP之上端位置降低，如上所述能夠提高半導體裝置之電晶體特性。
再者，該步驟亦可同樣地應用於其他實施形態2~5。
以上，基於實施形態對本發明進行了具體說明，但本發明當然不限定於實施形態，可於不脫離其要旨之範圍進行各種變更。
BIL‧‧‧埋入絕緣膜
CG‧‧‧控制閘極電極層
DR‧‧‧n+汲極區域
EP1‧‧‧p-磊晶區域
EP2‧‧‧p-磊晶區域
FG‧‧‧浮動閘極電極層
GBI‧‧‧閘極間絕緣膜
GE‧‧‧閘極電極層
GI‧‧‧閘極絕緣膜
IL1‧‧‧絕緣膜
IL2‧‧‧絕緣膜
MK1‧‧‧遮罩材(「第1絕緣膜」)
MK2‧‧‧遮罩材(「第3絕緣膜」)
NBR‧‧‧n型埋入區域
NCR‧‧‧n+接點區域
NDR‧‧‧n型沈降區域
NOR‧‧‧n型偏移區域
NR‧‧‧絕緣膜(「第2絕緣膜」)
NWR‧‧‧n型井區域
PBR‧‧‧p型埋入區域
PCR‧‧‧p+接點區域
PDR‧‧‧p型沈降區域
POR‧‧‧p型偏移區域
PR‧‧‧p型區域
PRE‧‧‧抗蝕劑圖案(「感光體圖案」)
PWR‧‧‧p型井區域
SC‧‧‧矽化物層
SO‧‧‧n+源極區域
STR‧‧‧溝槽(第2溝槽)
SUB‧‧‧半導體基板
SW‧‧‧側壁絕緣層
S/D‧‧‧源極/汲極區域

Claims (13)

  1. 一種半導體裝置之製造方法，其具備：於半導體基板之主表面形成複數個閘極電極之步驟；以埋入上述複數個閘極電極間之方式於上述複數個閘極電極上形成第1絕緣膜之步驟；於上述第1絕緣膜上形成材質與上述第1絕緣膜不同之第2絕緣膜之步驟；於上述第2絕緣膜上形成材質與上述第2絕緣膜不同之第3絕緣膜之步驟；於上述第3絕緣膜上形成感光體圖案之步驟；藉由將上述感光體圖案作為遮罩進行蝕刻，而形成貫通上述第1至第3絕緣膜並到達上述半導體基板之溝槽之步驟；以上述第3絕緣膜露出之方式去除上述感光體圖案之步驟；藉由將露出之上述第3絕緣膜作為遮罩進行蝕刻，而使上述溝槽延伸至上述半導體基板之內部之步驟；去除上述第3絕緣膜與上述第2絕緣膜之步驟；及以於上述溝槽內產生中空空間之方式於上述溝槽內與上述第1絕緣膜上形成第4絕緣膜之步驟。
  2. 如請求項1之半導體裝置之製造方法，其中上述第3絕緣膜係以覆蓋位於上述半導體基板之上述主表面之周緣之斜面部的方式形成，且於形成上述第3絕緣膜之後，進而具備於上述斜面部以覆蓋上述第3絕緣膜之方式形成材質與上述第3絕緣膜不同之第5絕緣膜的步驟，於上述第5絕緣膜於上述斜面部上覆蓋上述第3絕緣膜之狀態 下，形成貫通上述第1至第3絕緣膜並到達上述半導體基板之上述溝槽。
  3. 如請求項2之半導體裝置之製造方法，其中於上述斜面部以覆蓋上述第3絕緣膜之方式形成上述第5絕緣膜之步驟包括：於上述第3絕緣膜上形成上述第5絕緣膜之步驟；及藉由將上述第5絕緣膜去除直至上述第3絕緣膜露出為止而使上述第5絕緣膜殘留於上述斜面部之步驟。
  4. 如請求項1或2之半導體裝置之製造方法，其中於去除上述第3絕緣膜與上述第2絕緣膜之後，進而具備如下步驟：藉由對上述第1絕緣膜進行各向異性乾式蝕刻，而一方面殘留位於上述閘極電極之側壁之上述第1絕緣膜，一方面去除上述溝槽周圍之上述第1絕緣膜，於對上述第1絕緣膜進行各向異性乾式蝕刻後，以於上述溝槽內產生中空空間之方式於上述溝槽內與上述第1絕緣膜上形成上述第4絕緣膜。
  5. 如請求項4之半導體裝置之製造方法，其中對上述第1絕緣膜進行各向異性乾式蝕刻之步驟，係進行至殘留於上述閘極電極之側壁之上述第1絕緣膜之上端的位置位於較上述閘極電極之上端更下側為止。
  6. 如請求項1之半導體裝置之製造方法，其中於形成上述第3絕緣膜後，進而具備使上述第3絕緣膜平坦化之步驟，且使上述第3絕緣膜平坦化之後，於上述第3絕緣膜上形成上述感光體圖案。
  7. 一種半導體裝置之製造方法，其具備：於半導體基板之主表面形成複數個閘極電極之步驟；以埋入上述複數個閘極電極間之方式於上述複數個閘極電極 上形成第1絕緣膜之步驟；於位於上述半導體基板之上述主表面之周緣之斜面部，以覆蓋上述第1絕緣膜之方式形成材質與上述第1絕緣膜不同的第2絕緣膜之步驟；於上述第1絕緣膜上形成感光體圖案之步驟；於上述第2絕緣膜於上述斜面部上覆蓋上述第1絕緣膜之狀態下，將上述感光體圖案作為遮罩進行蝕刻，藉此形成貫通上述第1絕緣膜到達上述半導體基板之溝槽之步驟；以上述第1絕緣膜露出之方式去除上述感光體圖案之步驟；藉由將露出之上述第1絕緣膜作為遮罩進行蝕刻，而使上述溝槽延伸至上述半導體基板之內部之步驟；及以於上述溝槽內產生中空空間之方式於上述溝槽內與上述第1絕緣膜上形成第3絕緣膜之步驟。
  8. 如請求項7之半導體裝置之製造方法，其中於上述斜面部以覆蓋上述第1絕緣膜之方式形成上述第2絕緣膜之步驟包括：於上述第1絕緣膜上形成上述第2絕緣膜之步驟；及藉由將上述第2絕緣膜去除直至上述第1絕緣膜露出為止而使上述第2絕緣膜殘留於上述斜面部之步驟。
  9. 如請求項7之半導體裝置之製造方法，其中上述第1絕緣膜包含藉由於含有臭氧之氣體氛圍中使有機材料反應而形成之氧化矽膜、及藉由於電漿中使有機材料反應而形成之氧化矽膜。
  10. 一種半導體裝置之製造方法，其具備：於半導體基板之主表面形成複數個閘極電極之步驟；以埋入上述複數個閘極電極間之方式於上述複數個閘極電極上形成第1絕緣膜之步驟；於上述第1絕緣膜上形成感光體圖案之步驟； 藉由將上述感光體圖案作為遮罩進行蝕刻，而形成貫通上述第1絕緣膜並延伸至上述半導體基板內部之溝槽之步驟；以上述第1絕緣膜露出之方式去除上述感光體圖案之步驟；及以於上述溝槽內產生中空空間之方式於上述溝槽內與上述第1絕緣膜上形成第2絕緣膜之步驟。
  11. 如請求項10之半導體裝置之製造方法，其中上述第1絕緣膜係以覆蓋位於上述半導體基板之上述主表面之周緣之斜面部的方式形成，於形成上述第1絕緣膜後，進而具備於上述斜面部以覆蓋上述第1絕緣膜之方式形成材質與上述第1絕緣膜不同之第3絕緣膜之步驟；於上述第3絕緣膜於上述斜面部上覆蓋上述第1絕緣膜之狀態下，形成貫通上述第1及第3絕緣膜並延伸至上述半導體基板內部之上述溝槽。
  12. 如請求項11之半導體裝置之製造方法，其中於上述斜面部以覆蓋上述第1絕緣膜之方式形成上述第3絕緣膜之步驟包括：於上述第1絕緣膜上形成上述第3絕緣膜之步驟；及藉由將上述第3絕緣膜去除直至上述第1絕緣膜露出為止而使上述第3絕緣膜殘留於上述斜面部之步驟。
  13. 如請求項10之半導體裝置之製造方法，其中於形成上述第1絕緣膜之後，進而具備使上述第1絕緣膜平坦化之步驟，於使上述第1絕緣膜平坦化之後，於上述第1絕緣膜上形成上述感光體圖案。
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US10593773B2 (en) * 2017-09-29 2020-03-17 Texas Instruments Incorporated LDMOS with high-k drain STI dielectric
KR20190087786A (ko) * 2018-01-17 2019-07-25 주식회사 디비하이텍 반도체 소자 및 그 제조 방법
US11201122B2 (en) 2018-09-27 2021-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating semiconductor device with reduced warpage and better trench filling performance
US20200194581A1 (en) * 2018-12-18 2020-06-18 Vanguard International Semiconductor Corporation Semiconductor device and method for forming the same
CN111509044B (zh) * 2019-01-31 2023-09-19 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112926173B (zh) * 2019-12-06 2024-03-01 上海梅山钢铁股份有限公司 一种热轧高强钢板成形极限图的计算方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258510A (ja) * 2006-03-24 2007-10-04 Toshiba Corp 半導体装置の製造方法
JP2010171074A (ja) * 2009-01-20 2010-08-05 Renesas Technology Corp 半導体装置
JP5729745B2 (ja) * 2009-09-15 2015-06-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5669251B2 (ja) * 2010-01-20 2015-02-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN103515286B (zh) * 2012-06-29 2017-03-01 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的制造方法
CN103794557B (zh) * 2012-10-26 2016-04-06 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
JP6062269B2 (ja) * 2013-01-31 2017-01-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6200818B2 (ja) * 2014-01-21 2017-09-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

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