US10074556B2 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
US10074556B2
US10074556B2 US15/180,484 US201615180484A US10074556B2 US 10074556 B2 US10074556 B2 US 10074556B2 US 201615180484 A US201615180484 A US 201615180484A US 10074556 B2 US10074556 B2 US 10074556B2
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insulating film
over
semiconductor device
manufacturing
trench
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US20170047338A1 (en
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Masaaki Shinohara
Shigeo Tokumitsu
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Renesas Electronics Corp
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Renesas Electronics Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHINOHARA, MASAAKI, TOKUMITSU, SHIGEO
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    • H—ELECTRICITY
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L27/11546—
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a trench.
  • DTI Deep Trench Isolation
  • a high-breakdown-voltage MOS transistor having a source region and a drain region in a surface of a semiconductor substrate is completed.
  • a trench is formed to surround the transistor in plan view.
  • an insulating film is formed so as to cover the transistor from above and form a hollow in the trench.
  • an electronic element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed in the semiconductor substrate.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • an oxide film is formed over the gate of the transistor and the trench is formed by anisotropic etching using the oxide film as a mask. Then, an insulating film is formed so as to form the hollow in the trench.
  • the oxide film corresponding to a predetermined film thickness is also removed by etching.
  • the film thickness of the oxide film after the anisotropic etching varies in a wafer plane.
  • the variations in the film thickness of the insulating film causes layer-to-layer variations when contacts are formed to also cause variations in transistor characteristic.
  • a method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes over a main surface of a semiconductor substrate and forming a first insulating film over the plurality of gate electrodes so as to be embedded in a space between the plurality of gate electrodes.
  • the method further includes the steps of forming a second insulating film made of a material different from that of the first insulating film over the first insulating film and forming a third insulating film made of a material different from that of the second insulating film over the second insulating film.
  • the method further includes the steps of forming a photosensitive pattern over the third insulating film and performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching the semiconductor substrate.
  • the method further includes the steps of removing the photosensitive pattern so as to expose the third insulating film, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film so as to form a hollow space in the trench.
  • the third and second insulating films are removed. Accordingly, it is possible to remove the varying portions of the insulating film in a wafer plane. This can suppress variations in the film thickness of the insulating film and variations in transistor characteristic.
  • FIG. 1 is a schematic plan view illustrating a configuration of a semiconductor device in a chip state based on Embodiment 1;
  • FIG. 2 is a partially broken perspective view showing the element formation region shown in FIG. 1 which is surrounded by a trench in plan view;
  • FIG. 3 is a schematic cross-sectional view showing the configuration of the semiconductor device in Embodiment 1, which is the element surrounded by the trench in FIG. 2 ;
  • FIG. 4 is a schematic cross-sectional view showing a first step of a method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 5 is a schematic cross-sectional view showing a second step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 6 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 7 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 8 is a schematic cross-sectional view showing a fifth step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 9 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 10 is a schematic cross-sectional view showing a seventh step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 11 is a schematic cross-sectional view showing an eighth step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 12 is a schematic cross-sectional view showing a ninth step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 13 is a schematic cross-sectional view showing a tenth step of the method of manufacturing the semiconductor device based on Embodiment 1;
  • FIG. 14 is a cross-sectional view diagrammatically showing a state where a resist pattern is formed over the upper surface of a semiconductor substrate in a related art example as a comparative example;
  • FIG. 15 is a cross-sectional view diagrammatically showing a state where etching has been performed using the resist pattern as a mask
  • FIG. 16 is a schematic cross-sectional view showing a second step of a method of manufacturing a semiconductor device based on Embodiment 2;
  • FIG. 17 is a view diagrammatically illustrating the second step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 18 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 19 is a view diagrammatically illustrating the third step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 20 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 21 is a view diagrammatically illustrating the fourth step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 22 is a schematic cross-sectional view showing a fifth step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 23 is a view diagrammatically illustrating the fifth step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 24 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 25 is a view diagrammatically illustrating the sixth step of the method of manufacturing the semiconductor device based on Embodiment 2;
  • FIG. 26 is a schematic cross-sectional view showing a second step of a method of manufacturing a semiconductor device based on Embodiment 3;
  • FIG. 27 is a view diagrammatically illustrating the second step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 28 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 29 is a view diagrammatically illustrating the third step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 30 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 31 is a view diagrammatically illustrating the fourth step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 32 is a schematic cross-sectional view showing a fifth step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 33 is a view diagrammatically illustrating the fifth step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 34 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 35 is a view diagrammatically illustrating the sixth step of the method of manufacturing the semiconductor device based on Embodiment 3;
  • FIG. 36 is a schematic cross-sectional view showing a second step of a method of manufacturing a semiconductor device based on Embodiment 4;
  • FIG. 37 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device based on Embodiment 4;
  • FIG. 38 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device based on Embodiment 4.
  • FIG. 39 is a schematic cross-sectional view showing an additional step of a method of manufacturing the semiconductor device based on Embodiment 6.
  • FIG. 1 is a schematic plan view illustrating a configuration of a semiconductor device in a chip state based on Embodiment 1.
  • a semiconductor chip CP of a BiC-DMOS (Bipolar Complementary Metal Oxide Semiconductor Double-diffused Metal Oxide Semiconductor) has a logic portion LG in which, e.g., low-breakdown-voltage CMOS (Complementary MOS) transistors are integrated and output driver portions HV using high-breakdown-voltage elements.
  • CMOS Complementary MOS
  • the region where the low-breakdown-voltage CMOS transistors are formed is surrounded by a trench DTR having a DTI structure in plan view.
  • the output driver portions HV the respective regions where the individual elements are formed are surrounded by the trenches DTR each having the DTI structure in plan view.
  • FIG. 2 is a partially broken perspective view showing each of the element formation regions shown in FIG. 1 which is surrounded by the trench in plan view.
  • the respective element formation regions DFR for the individual high-breakdown-voltage elements are two-dimensionally surrounded by the trenches DTR each having the DTI structure.
  • the trenches DTR are formed in a surface of a semiconductor substrate SUB.
  • FIG. 3 is a schematic cross-sectional view showing a configuration of the semiconductor device in Embodiment 1, which is each of the elements surrounded by the trenches in FIG. 2 .
  • the semiconductor substrate SUB is made of, e.g., silicon and selectively has trenches STR in the main surface thereof.
  • the trenches STR embedded insulating films BIL are formed.
  • the trenches STR and the embedded insulating film BIL form STI (Shallow Trench Isolation) structures.
  • a p ⁇ epitaxial region EP 1 and an n-type embedded region NBR are formed.
  • a p-type embedded region PBR is selectively formed.
  • a p ⁇ epitaxial region EP 2 is formed.
  • the high-breakdown-voltage lateral MOS transistor has an n-type offset region NOR, n-type well regions NWR, p-type well regions PWR, an n + drain region DR, n + source regions SO, gate insulating films 31 , and gate electrode layers GE as main components.
  • the n-type offset region NOR is formed in the surface of the semiconductor substrate SUB so as to form a pn junction with the p ⁇ epitaxial region EP 2 .
  • the n-type well region NWR is formed so as to come in contact with the n-type offset region NOR.
  • the n + drain region DR is formed in the surface of the semiconductor substrate SUB so as to come in contact with the n-type well region NWR.
  • the p-type well regions PWR are formed in the p ⁇ epitaxial region EP 2 and in the surface of the semiconductor substrate SUB.
  • the n + source regions SO are formed in the surface of the semiconductor substrate SUB so as to form pn junctions with the p-type well regions PWR.
  • the p-type well regions PWR and the p ⁇ epitaxial region EP 2 are interposed along the surface of the semiconductor substrate SUB.
  • the gate electrode layers GE are formed over the semiconductor substrate SUB so as to face the p-type well regions PWR and the p ⁇ epitaxial region EP 2 which are interposed between the n + source regions SO and the n-type offset region NOR via the gate insulating films GI.
  • One end portion of each of the gate electrode layers GE is located over the STI structure formed in the n-type offset region NOR.
  • Sidewall insulating layers SW are formed so as to cover the side walls of the gate electrodes GE.
  • silicide layers SC are preferably formed over the respective surfaces of the n + source regions SO, the n + drain region DR, and the gate electrode layers GE. However, the silicide layers SC may also be omitted.
  • p-type sinker regions PDR are formed so as to come in contact with the p-type embedded region PBR.
  • the p-type well regions PWR and p + contact regions PCR are formed closer to the surface of the semiconductor substrate SUB.
  • the STI structures are formed in the surface of the semiconductor substrate SUB located between the p + -type contact regions PCR and the n + source regions SO.
  • n-type sinker regions NDR are formed so as to come in contact with the n-type embedded region NBR.
  • the n-type well regions NWR and n + contact regions NCR are formed closer to the surface of the semiconductor substrate SUB.
  • the silicide layers SC are formed in the respective surfaces of the n + -type contact region NCR and the p + -type contact regions PCR.
  • the silicide layers SC may also be omitted.
  • Insulating films IL 1 and IL 2 , a mask material MK, and an insulating film II are stacked successively so as to cover the high-breakdown-voltage lateral MOS transistor.
  • the insulating film IL 1 is, e.g., a silicon dioxide film and the insulating film IL 2 is, e.g., a silicon nitride film.
  • the mask material MK is, e.g., a silicon dioxide film.
  • the insulating films IL 1 and IL 2 and the mask material MK are formed over the gate electrode layers GE so as to be embedded in the spaces between the gate electrodes of the plurality of gate electrode layers GE.
  • the insulating film II is formed so as to cover the mask material MK.
  • the insulating film II is made of a stacked structure including, e.g., BP-TEOS (Boro-Phospho-Tetra-Ethyl-Ortho-Silicate) and a silicon dioxide film formed thereover by a plasma CVD (Chemical Vapor Deposition) method.
  • BP-TEOS Bo-Phospho-Tetra-Ethyl-Ortho-Silicate
  • silicon dioxide film formed thereover by a plasma CVD (Chemical Vapor Deposition) method e.g., BP-TEOS (Boro-Phospho-Tetra-Ethyl-Ortho-Silicate) and a silicon dioxide film formed thereover by a plasma CVD (Chemical Vapor Deposition) method.
  • the BP-TEOS BPSG standing for Boro-Phosphate Silicate Glass
  • the insulating film II may appropriately be an insulating film containing an impurity which is at least either one of a group
  • contact holes CH are formed and, in the contact holes CH, plug conductive layers PL are formed.
  • a wiring layer ICL is formed over the insulating film II.
  • the wiring layer ICL is electrically coupled to the conductive portions (such as, e.g., the source regions SO, the n + drain regions DR, the contact regions NCR and PCR, and the gate electrode layers GE) of the high-breakdown-voltage lateral MOS transistor via the plug conductive layers PL in the contact holes CH.
  • the DTI structure is formed so as to surround the region where the high-breakdown-voltage lateral MOS transistor described above is formed in plan view.
  • the DTI structure has the trench (first trench) DTR extending from the surface of the semiconductor substrate SUB into the semiconductor substrate SUB and the insulating film II formed in the trench DTR.
  • the trench DTR is formed so as to extend from the surface of the semiconductor substrate SUB through the p epitaxial region EP 2 , the n-type embedded region NBR, and the p epitaxial region EP 1 and reach the p-type region PR.
  • the insulating film II formed in the trench DTR mentioned above is an interlayer insulating film formed over the high-breakdown-voltage lateral MOS transistor.
  • the trench DTR is not completely filled with the insulating film II and a hollow (void) SP is formed in the trench DTR.
  • the hollow SP is formed at least in the vicinity of the junction portion between the n-type embedded region NBR and the p epitaxial region EP 1 .
  • the hollow SP may also have a height substantially equal to the depth of the trench.
  • the aspect ratio (Depth/Width W) of the trench DTR is not less than 1.
  • the width W of the trench DTR is not less than 0.3 ⁇ m on the basis of a breakdown voltage of 80 V.
  • the trench DTR may also be formed in the portion where the STI structure is formed. In this case, the trench DTR is formed deeper than each of the trenches STR in the region where the trench (second trench) STR of the STI structure is formed.
  • FIG. 4 is a schematic cross-sectional view showing a first step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • the high-breakdown-voltage lateral MOS transistor is formed so as to have the n-type offset region NOR, the n-type well regions NWR, the p-type well regions PWR, the n + drain region DR, the n + source regions SO, the gate insulating films GI, and the gate electrode layers GE.
  • the pMOS transistor as the high-breakdown-voltage element is formed so as to have a p-type offset region POR, the n-type well regions NWR, the p-type well regions PWR, the p + drain region DR, the p + source regions SO, the gate insulating films GI, and the gate electrode layers GE.
  • the CMOS transistor is formed so as to complete a pMOS transistor and an nMOS transistor.
  • the pMOS transistor is formed so as to have the n-type well region NWR, a pair of p-type source/drain regions S/D each having an LDD (Lightly Doped Drain) structure, the gate insulating film GI, and the gate electrode layers GE.
  • the nMOS transistor is formed so as to have the p-type well region PWR, a pair of n-type source/drain region S/D each having the LDD structure, the gate insulating film GI, and the gate electrode layer GE.
  • the nonvolatile semiconductor storage element is formed of, e.g., a stacked-gate memory transistor.
  • the stacked-gate memory transistor is formed so as to have the p-type well region PWR, the n-type drain regions DR each having the LDD structure, the n source regions SO, the gate insulating films GI, floating gate electrode layers FG, gate-to-gate insulating films GBI, and control gate electrode layers CG.
  • the silicide layers SC may also be formed.
  • the sidewall insulating layers SW are formed so as to cover the respective side walls of the gate electrode layers GE, FG, and CG of the individual elements.
  • the plurality of gate electrodes of the individual elements are formed over the semiconductor substrate SUB.
  • FIG. 5 is a schematic cross-sectional view showing a second step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • the insulating films IL 1 and IL 2 , a mask material MK 1 (“first insulating film”), an insulating film NR (“second insulating film”), and a mask material MK 2 (“third insulating film”) are successively stacked so as to cover the individual elements.
  • the insulating film IL 1 is formed of, e.g., a non-doped silicon dioxide film having a thickness of 20 nm.
  • the insulating film IL 2 is formed of, e.g., a silicon nitride film having a thickness of 50 nm.
  • the mask material MK 1 is formed of, e.g., a non-doped silicon dioxide film having a thickness of 200 nm.
  • the insulating film NR is formed of, e.g., a silicon nitride film having a thickness of 50 nm.
  • the mask material MK 2 is formed of, e.g., a non-doped silicon dioxide film having a thickness of 800 nm.
  • the mask materials MK 1 and MK 2 may be silicon dioxide films made of the same material or can also be silicon dioxide films made of different materials.
  • a resist pattern PRE (“photosensitive pattern”) is applied.
  • the silicon nitride film is described as an example of an insulating film. However, it is also possible to use a silicon oxynitride film, a carbon-containing silicon nitride film, or a silicon carbonitride film instead of the silicon nitride film.
  • the mask material MK 1 is formed over the plurality of gate electrodes so as to be embedded in the spaces between the plurality of gate electrodes.
  • This provides a structure in which the insulating film NR is interposed between the mask materials MK 1 and MK 2 .
  • the upper surface thereof is polished and removed by, e.g., a CMP (Chemical Mechanical Polishing) method to be planarized.
  • CMP Chemical Mechanical Polishing
  • planarization allows the shape of the resist pattern PRE to be stabilized.
  • the upper surface of the mask material MK 2 is polished and removed by the CMP method, but the upper surface of the mask material MK 2 need not necessarily be removed by polishing.
  • FIG. 6 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • the resist pattern PRE is formed by patterning using a typical photomechanical technique.
  • the mask material MK 2 , the insulating film NR, the mask material MK 1 , the insulating film IL 2 , the insulating film IL 1 , and the STI structure are successively anisotropically etched.
  • trenches DTRA are formed in the surface of the semiconductor substrate SUB.
  • FIG. 7 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • the resist pattern PRE (“photosensitive pattern”) is removed by ashing or the like. As a result, the mask material MK 2 formed under the resist pattern PRE is exposed.
  • FIG. 8 is a schematic cross-sectional view showing a fifth step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • the semiconductor substrate SUB is subjected to anisotropic etching continuously using the mask material MK 2 (“third insulating film”) as a mask.
  • the trenches DTR are formed to extend from the surface of the semiconductor substrate SUB through the p epitaxial region EP 2 , the n-type embedded region NBR, and the p epitaxial region EP 1 and reach the p-type region PR.
  • the mask material MK 2 corresponding to a predetermined film thickness is also removed by etching so that the remaining mask material MK 2 has the initial thickness of 300 nm.
  • FIG. 9 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • the mask material MK 2 is removed by anisotropic etching, while the insulating film NR is removed by isotropic etching or anisotropic etching.
  • anisotropic etching is performed by dry etching.
  • isotropic etching is performed by dry or wet etching.
  • the removal of the mask material MK 2 (“third insulating film”) is performed using the insulating film NR (“second insulating film”) as a stopper.
  • the removal of the insulating film NR is performed using the mask material MK 1 as a stopper.
  • the upper surface of the mask material MK 1 is exposed.
  • the mask material MK 2 is removed by anisotropic etching, the embedded insulating films BIL of the STI structure exposed at the wall surfaces of the trenches DTR are not reduced in a lateral direction in the drawing (do not recede).
  • FIG. 10 is a schematic cross-sectional view showing a seventh step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • an insulating film IIA (“fourth insulating film”) is formed over the individual elements and in the trenches DTR so as to cover the individual elements and form the hollows SP in the trenches DTR.
  • the insulating film IIA is formed of, e.g., BP-TEOS having a thickness of 1450 nm.
  • the upper surface of the insulating film IIA is planarized by, e.g., a CMP (Chemical Mechanical Polishing) method. As a result, the thickness of the insulating film IIA is reduced to, e.g., 750 nm.
  • FIG. 11 is a schematic cross-sectional view showing an eighth step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • a silicon dioxide film is formed over the insulating film IIA described above by a plasma CVD method.
  • the insulating film IIA and the silicon dioxide film formed by the plasma CVD method form the insulating film II.
  • FIG. 12 is a schematic cross-sectional view showing a ninth step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • the contact holes CH are formed to extend through the insulating films II, IL 2 , and IL 1 and reach the surface of the semiconductor substrate SUB. From the contact holes CH, e.g., the surfaces of the silicide layers SC formed in the respective surfaces of the source regions, the drain regions, and the like are exposed.
  • FIG. 13 is a schematic cross-sectional view showing a tenth step of the method of manufacturing the semiconductor device based on Embodiment 1.
  • the plug conductive layers PL are formed in the contact holes CH. Then, over the insulating film II, the wiring layer ICL is formed so as to be electrically coupled to the respective conductive portions of the individual elements via the plug conductive layers PL.
  • the semiconductor device in the embodiment is manufactured.
  • the insulating film NR is formed over the mask material MK 1 . Then, over the insulating film NR, the mask material MK 2 is formed. When the trenches DTR are formed, the mask material MK 2 is used as the hard mask. However, variations in residual film produced at that time can be reset by performing an etching process using the insulating film NR as a stopper. Then, by removing the insulating film NR, the mask material MK 1 is exposed. Since variations in the film thickness of the mask material MK 1 are small, it is possible to reduce layer-to-layer variations when the contacts are formed. This can suppress variations in transistor characteristic.
  • Embodiment 2 a description will be given of a method of manufacturing a semiconductor device in the case where a bevel protection mechanism is not provided.
  • a bevel portion in a semiconductor substrate indicates an inclined portion formed in the peripheral edge of a main surface of a semiconductor substrate (semiconductor wafer).
  • the inclined portion involves a state where the main surface is linearly inclined from the center of the substrate toward the outer end thereof in a cross-sectional shape and a state where the main surface is curvedly inclined from the center of the substrate toward the outer end thereof in a cross-sectional shape.
  • FIG. 14 is a cross-sectional view diagrammatically showing a state where a resist pattern is formed over the upper surface of a semiconductor substrate in a related art example as a comparative example.
  • openings 29 are formed in a resist pattern 28 formed by patterning over the upper surface of the semiconductor substrate 1 . Since the resist pattern 28 is formed by applying a fluent material by spin coating, the resist pattern 28 is less likely to be formed over the bevel portions of the semiconductor substrate 1 .
  • FIG. 15 is a cross-sectional view diagrammatically showing a state where etching has been performed using the resist pattern as a mask.
  • trenches 30 are formed by etching the semiconductor substrate 1 located immediately under the openings 29 of the resist pattern 28 .
  • the bevel portions of the semiconductor substrate 1 are not covered with the resist pattern 28 and are etched so that significantly protruding/depressed portions 31 are formed.
  • the protruding/depressed portions 31 may be formed to have indented shapes or sharply inclined surfaces. In this case, when the semiconductor substrate 1 is processed in the subsequent step or transported, the protruding/depressed portions 31 having the indented shapes or the sharply inclined surfaces may come off the semiconductor substrate 1 to result in foreign materials having sizes of several tens of micrometers. When the foreign materials adhere to a semiconductor device, the function of the semiconductor device may be degraded thereby.
  • Embodiment 2 a description will be given of a method of manufacturing the semiconductor device in which, even when the bevel protection mechanism is not provided, the bevel portions can be protected using a simple and easy process.
  • a first step of the method of manufacturing the semiconductor device based on Embodiment 2 is the same as the first step illustrated in FIG. 4 in Embodiment 1 so that the detailed description thereof is not repeated.
  • FIG. 16 is a schematic cross-sectional view showing a second step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the insulating films IL 1 and IL 2 , the mask material MK (“first insulating film”), and an insulating film NR 1 (“second insulating film”) are successively stacked.
  • the insulating film IL 1 is formed of, e.g., a non-doped silicon dioxide film having a thickness of 20 nm.
  • the insulating film IL 2 is formed of, e.g., a silicon nitride film having a thickness of 50 cm.
  • the mask material MK is formed of, e.g., a non-doped silicon dioxide film having a thickness of 1000 nm.
  • the insulating film NR 1 is formed of, e.g., a silicon nitride film having a thickness of 100 nm.
  • the silicon nitride film is described as an example of the insulating film.
  • the mask material MK includes a silicon dioxide film (ozone TEOS (Tetra-Ethyl-Ortho-Silicate)) formed by causing an organic material to react in an atmosphere containing ozone and a silicon dioxide film (plasma TEOS) formed by causing an organic material to react in a plasma.
  • ozone TEOS Tetra-Ethyl-Ortho-Silicate
  • plasma TEOS silicon dioxide film
  • FIG. 17 is a view diagrammatically illustrating a second step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the mask material MK is formed over the bevel portions of the semiconductor substrate SUB.
  • the insulating film NR 1 is formed over the mask material MK over the bevel portions so as to further cover the bevel portions.
  • FIG. 18 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the upper surfaces of the insulating film NR 1 and the mask MK are polished and removed by, e.g., a CMP (Chemical Mechanical Polishing) method to be planarized.
  • CMP Chemical Mechanical Polishing
  • FIG. 19 is view diagrammatically illustrating a third step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the upper surfaces of the insulating film NR 1 and the mask material MK are polished and removed by a CMP method. As a result, the upper surface of the mask material MK 1 is exposed, while the insulating film NR 1 remains over the bevel portions of the semiconductor substrate SUB.
  • FIG. 20 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the resist pattern PRE (“photosensitive pattern”) is formed by patterning using a typical photomechanical technique. Using the resist pattern PRE formed by the patterning as a mask, the mask material MK, the insulating films IL 2 and IL 1 , and the STI structure are successively anisotropically etched. Thus, the trenches DTRA are formed in the surface of the semiconductor substrate SUB.
  • FIG. 21 is a view diagrammatically illustrating a fourth step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the resist pattern PRE is formed.
  • the resist pattern PRE is not formed over the bevel portions.
  • FIG. 22 is a schematic cross-sectional view showing a fifth step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the resist pattern PRE is removed by ashing or the like. As a result, the mask material MK formed under the resist pattern PRE is exposed.
  • the semiconductor substrate SUB is subjected to anisotropic etching continuously using the mask material UK as a mask.
  • the trenches DTR are formed to extend from the surface of the semiconductor substrate SUB through the p ⁇ epitaxial region EP 2 , the n-type embedded region NBR, and the p ⁇ epitaxial region EP 1 and reach the p-type region PR.
  • FIG. 23 is a view diagrammatically illustrating a fifth step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the mask material MK is exposed and the insulating film NR 1 remaining over the bevel portions is also removed.
  • the regions corresponding to the bevel portions are anisotropically etched away since the resist pattern PRE is not formed thereover.
  • the insulating film NR 1 remaining over the bevel portions of the semiconductor substrate SUB is etched away, the semiconductor substrate SUB is protected.
  • FIG. 24 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the insulating film IIA is formed over the individual elements and in the trenches DTR so as to cover the individual elements and form the hollows SP in the trenches DTR.
  • the insulating film IIA is formed of, e.g., BP-TEOS having a thickness of, e.g., 1450 nm.
  • the upper surface of the insulating film IIA is planarized by, e.g., a CMP (Chemical Mechanical Polishing) method. As a result, the thickness of the insulating film IIA is reduced to, e.g., 750 nm.
  • FIG. 25 is a view diagrammatically illustrating a sixth step of the method of manufacturing the semiconductor device based on Embodiment 2.
  • the insulating film IIA is formed over the mask material MK.
  • the semiconductor device in the embodiment is manufactured.
  • the insulating film NR 1 is formed over the mask material MK so as to cover the bevel portions of the semiconductor substrate SUB.
  • the insulating film NR 1 remaining over the bevel portions protects the semiconductor substrate SUB during the anisotropic etching and can prevent the bevel portions of the semiconductor substrate SUB from being etched.
  • Embodiment 2 the description has been given of the method of manufacturing the semiconductor device when the bevel protection mechanism is not provided and of the case where the trenches are formed by the anisotropic etching in the fifth step, as described above.
  • the mask material MK corresponding to the predetermined thickness is also removed by etching and the film thickness of the mask material MK may vary in a wafer plane.
  • Embodiment 3 a description will be given of a method of manufacturing a semiconductor device which can protect the bevel portions using a simple and easy process even when the bevel protection mechanism is not provided and also suppress variations in transistor characteristic.
  • a first step of the method of manufacturing the semiconductor device based on Embodiment 3 is the same as the first step illustrated in FIG. 4 in Embodiment 1 so that the detailed description thereof is not repeated.
  • FIG. 26 is a schematic cross-sectional view showing a second step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the insulating films IL 1 and IL 2 , the mask material MK 1 , the insulating film NR 1 , the mask material MK 2 (“third insulating film”), and an insulating film NR 2 (“fifth insulating film”) are stacked successively so as to cover the individual elements.
  • the insulating film IL 1 is formed of, e.g., a non-doped silicon dioxide film having a thickness of 20 nm.
  • the insulating film IL 2 is formed of, e.g., a silicon nitride film having a thickness of 50 nm.
  • the mask material MK 1 is formed of, e.g., a non-doped silicon dioxide film having a thickness of 200 nm.
  • the insulating film NR 1 is formed of, e.g., a silicon nitride film having a thickness of 50 nm.
  • the mask material MK 2 is formed of, e.g., a non-doped silicon dioxide film having a thickness of 800 nm.
  • the insulating film NR 2 is formed of, e.g., a silicon nitride film having a thickness of 100 nm.
  • the silicon nitride film will be described as an example of the insulating film.
  • FIG. 27 is a view diagrammatically illustrating a second step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the mask material MK 1 , the insulating film NR 1 , and the mask material MK 2 are formed over the bevel portions of the semiconductor substrate SUB.
  • the insulating film NR 2 is formed over the mask material MK 2 over the bevel portions so as to further cover the bevel portions. Note that, for easier understanding, the mask material MK 2 and the insulating film NR 2 provided thereover are shown herein.
  • FIG. 28 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the upper surfaces of the insulating film NR 2 and the mask material MK 2 are polished and removed by, e.g., a CMP (Chemical Mechanical Polishing) method.
  • CMP Chemical Mechanical Polishing
  • FIG. 29 is a view diagrammatically illustrating the third step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the upper surfaces of the insulating film NR 2 and the mask material MK 2 are polished and removed by a CMP method. As a result, the upper surface of the mask material MK 2 is exposed, while the insulating film NR 2 remains over the bevel portions of the semiconductor substrate SUB.
  • FIG. 30 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the resist pattern PRE is formed by patterning using a typical photomechanical technique.
  • the mask material MK 2 , the insulating film NR 1 , the mask material MK 1 , the insulating films IL 2 and IL 1 , and the STI structure are successively anisotropically etched.
  • the trenches DTRA are formed in the surface of the semiconductor substrate SUB to extend through the mask material MK 2 , the insulating film NR 1 , and the insulating films IL 2 and IL 1 .
  • FIG. 31 is a view diagrammatically illustrating the fourth step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the resist pattern PRE is formed but, over the bevel portions, the resist pattern PRE is not formed.
  • FIG. 32 is a schematic cross-sectional view showing a fifth step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the resist pattern PRE is removed by ashing or the like. As a result, the mask material MK 2 formed under the resist pattern PRE is exposed.
  • the semiconductor substrate SUB is subjected to anisotropic etching continuously using the mask material MK 2 as a mask.
  • the trenches DTR are formed to extend from the surface of the semiconductor substrate SUB through the p epitaxial region EP 2 , the n-type embedded region NBR, and the p epitaxial region EP 1 and reach the p-type region PR.
  • FIG. 33 is a view diagrammatically illustrating a fifth step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the mask material MK 2 is exposed by ashing or the like and the insulating film NR 1 remaining over the bevel portions is also removed.
  • the regions corresponding to the bevel portions are anisotropically etched away since the resist pattern PRE is not formed thereover.
  • the insulating film NR 1 remaining over the bevel portions of the semiconductor substrate SUB is etched away, the semiconductor substrate SUB is protected.
  • FIG. 34 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the mask material MK 2 is removed by anisotropic etching, while the insulating film NR 1 is removed by isotropic etching or anisotropic etching.
  • anisotropic etching is performed by dry etching.
  • isotropic etching is performed by dry or wet etching.
  • the removal of the mask material MK 2 is performed using the insulating film NR 1 as a stopper.
  • the removal of the insulating film NR 1 is performed using the mask material MK 1 as a stopper.
  • the upper surface of the mask material MK 1 is exposed.
  • the mask material MK 2 is removed by anisotropic etching, the embedded insulating film BIL of the STI structure exposed at the wall surfaces of the trenches DTR are not reduced in a lateral direction in the drawing (does not recede).
  • FIG. 35 is a view diagrammatically illustrating a sixth step of the method of manufacturing the semiconductor device based on Embodiment 3.
  • the mask material MK 1 is exposed over the semiconductor substrate SUB.
  • the semiconductor device in the embodiment is manufactured.
  • the mask material MK 2 is formed over the bevel portions of the semiconductor substrate SUB.
  • the insulating film NR 2 is formed so as to cover the bevel portions.
  • the resist pattern is formed over the insulating film NR 2 .
  • the trenches are formed. During the anisotropic etching for forming the trenches, the insulating film NR 2 remaining over the bevel portions protects the bevel portions to be able to prevent the bevel portions of the semiconductor substrate SUB from being etched.
  • the insulating film NR 1 is formed over the mask material MK 1 . Then, over the insulating film NR 1 , the mask material MK 2 is formed. When the trenches DTR are formed, the mask material MK 2 is used as a hard mask, resulting in variations in residual film. However, the variations in residual film can be reset by performing the etching process using the insulating film NR 1 as the stopper. Then, the insulating film NR 1 is removed to expose the mask material MK 1 . Since variations in the film thickness of the mask material MK 1 are small, it is possible to reduce layer-to-layer variations when the contacts are formed. This can suppress variations in transistor characteristic.
  • Embodiment 1 the description has been given of the method of reducing variations in residual, film when the mask material is used as the hard mask.
  • Embodiment 4 a description will be given of a method of suppressing variations in transistor characteristic using a simpler and easier method.
  • a first step of the method of manufacturing the semiconductor device based on Embodiment 4 is the same as the first step illustrated in FIG. 4 in Embodiment 1 so that the detailed description thereof is not repeated.
  • FIG. 36 is a schematic cross-sectional view showing a second step of the method of manufacturing the semiconductor device based on Embodiment 4.
  • the insulating films IL 1 and IL 2 , the mask material MK (“first insulating film”), and the resist pattern PRE (“photosensitive pattern”) are successively stacked so as to cover the individual elements.
  • IL 1 is formed of, e.g. a non-doped silicon dioxide film having a thickness of 20 nm.
  • the insulating film IL 2 is formed of, e.g., a silicon nitride film having a thickness of 50 nm.
  • the mask material MK is formed of, e.g., a non-doped silicon dioxide film having a thickness of 200 nm.
  • FIG. 37 is a schematic cross-sectional view showing a third step of the method of manufacturing the semiconductor device based on Embodiment 4.
  • the resist pattern PRE is formed by patterning using a typical photomechanical technique.
  • the mask material MK, the insulating films IL 2 and IL 1 , the STI structure, and the semiconductor substrate SUB are successively anisotropically etched.
  • the trenches DTR are formed to extend from the surface of the semiconductor substrate SUB through the p ⁇ epitaxial region EP 2 , the n-type embedded region NBR, and the p ⁇ epitaxial region EP 1 in the substrate to the p-type region PR.
  • an etching process using a so-called Bosch process is performed.
  • the step of etching the semiconductor substrate SUB using a gas including a sulfur hexafluoride (SF 6 ) gas and the step of covering the side surfaces of the trenches DTR using a gas including a carbon fluoride (fluorocarbon) gas such as, e.g., a C 4 F 8 gas are repeated.
  • FIG. 38 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device based on Embodiment 4.
  • the resist pattern PRE is removed by ashing or the like. As a result, the mask material MK formed under the resist pattern PRE is exposed.
  • the semiconductor device in the embodiment is manufactured.
  • the trenches DTR are formed using the resist pattern PRE as a mask.
  • the etching process using the mask material MK as a hard mask is not performed. This causes no variation in residual film at that time and can reduce layer-to-layer variations during the formation of the contacts. As a result, it is possible to suppress variations in transistor characteristic.
  • the semiconductor device can be manufactured using a simpler and easier process than in each of the embodiments described above, the cost of a manufacturing process can be reduced.
  • Embodiment 4 a description will be given of the simple and easy manufacturing process described above in Embodiment 4 as well as a method of manufacturing a semiconductor device which allows the bevel portions to be protected using a simple and easy process even when the bevel protection mechanism is not provided.
  • a fourth step of the method of manufacturing the semiconductor device based on Embodiment 5 is such that, in the fourth step in FIG. 20 described in Embodiment 2, using the resist pattern PRE as a mask, the mask material MK, the insulating films IL 2 and IL 1 , the STI structure, and the semiconductor substrate SUB are successively anisotropically etched, as described in Embodiment 4.
  • the trenches DTR are formed to extend from the surface of the semiconductor substrate SUB through the p epitaxial region EP 2 , the n-type embedded region NBR, and the p epitaxial region EP 1 and reach the p-type region PR.
  • an etching process using a so-called Bosch process is performed.
  • the step of etching the semiconductor substrate SUB using a gas including a sulfur hexafluoride (SF 6 ) gas and the step of covering the side surfaces of the trenches DTR using a gas including a carbon fluoride (fluorocarbon) gas such as, e.g., a C 4 F 8 gas are repeated.
  • the process steps including and subsequent to the fifth step are basically the same as the steps illustrated in FIGS. 22 and 25 described in Embodiment 2 so that the detailed description thereof is not repeated.
  • the trenches DTR are formed using the resist pattern PRE as a mask so that the etching process using the mask material MK as the hard mask in the fifth step in Embodiment 2 is not performed.
  • the semiconductor device in Embodiment 5 is manufactured.
  • the trenches DTR are formed.
  • the etching process using the mask material MK as the hard mask is not performed. This causes no variation in residual film at that time and can reduce layer-to-layer variations during the formation of the contacts. As a result, it is possible to suppress variations in transistor characteristic.
  • the insulating film NR 1 is formed over the mask material MK so as to cover the bevel portions of the semiconductor substrate SUB.
  • the insulating film NR 1 remaining over the bevel portions protects the semiconductor substrate SUB during the anisotropic etching and can prevent the bevel portions of the semiconductor substrate SUB from being etched.
  • Embodiment 6 a description will be given of a method of manufacturing a semiconductor device which further enhances a transistor characteristic.
  • the manufacturing method in Embodiment 6 further has an additional step of removing the mask material MK 1 prior to the formation of the hollows SP.
  • FIG. 39 is a schematic cross-sectional view showing the additional step of the method of manufacturing the semiconductor device based on Embodiment 6.
  • First to sixth steps of the method of manufacturing the semiconductor device based on Embodiment 6 are the same as the steps in FIGS. 4 to 9 described in Embodiment 1.
  • the mask material MK 1 is removed by anisotropic etching. Specifically, the mask material MK 1 located over the side walls of the gate electrode layers GE and between the gate electrodes is left, while the mask material MK 1 is removed from the other region. Thus, the mask material MK 1 is removed from around the trenches DTR.
  • anisotropic etching is performed by dry etching.
  • the anisotropic etching is performed until the position of the upper end of the mask material MK 1 remaining over the side walls of the gate electrode layers GE is located below the upper ends of the gate electrode layers GE.
  • the process steps including and subsequent to a seventh step are basically the same as the steps illustrated in FIGS. 10 to 13 described in Embodiment 1 so that the detailed description thereof is not repeated.
  • the mask material MK 1 is dry-etched to be removed from around the trenches, while the insulating film of the mask material MK 1 located over the side walls of the gate electrode layers GE is left. Then, the insulating film IIA is formed over each of the elements and in each of the trenches DTR so as to form the hollow SP in the trench DTR.

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