TW201633469A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
- Publication number
- TW201633469A TW201633469A TW104142200A TW104142200A TW201633469A TW 201633469 A TW201633469 A TW 201633469A TW 104142200 A TW104142200 A TW 104142200A TW 104142200 A TW104142200 A TW 104142200A TW 201633469 A TW201633469 A TW 201633469A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- semiconductor element
- mounting
- layer
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014255310A JP2016115884A (ja) | 2014-12-17 | 2014-12-17 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW201633469A true TW201633469A (zh) | 2016-09-16 |
Family
ID=56126205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104142200A TW201633469A (zh) | 2014-12-17 | 2015-12-16 | 半導體裝置及其製造方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2016115884A (ja) |
TW (1) | TW201633469A (ja) |
WO (1) | WO2016098296A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111403630A (zh) * | 2017-03-08 | 2020-07-10 | 堺显示器制品株式会社 | 有机el设备的制造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021118337A (ja) * | 2020-01-29 | 2021-08-10 | 株式会社ディスコ | デバイスパッケージの製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004327803A (ja) * | 2003-04-25 | 2004-11-18 | Hitachi Chem Co Ltd | 多層回路基板、半導体チップ搭載基板及び半導体パッケージ、並びにそれらの製造方法 |
JP2007019394A (ja) * | 2005-07-11 | 2007-01-25 | Toshiba Corp | 半導体パッケージの製造方法及びこの製造方法により形成された半導体パッケージ |
JP2008130701A (ja) * | 2006-11-20 | 2008-06-05 | Matsushita Electric Ind Co Ltd | 配線基板とそれを用いた半導体装置及び半導体装置の製造方法 |
JP2010016291A (ja) * | 2008-07-07 | 2010-01-21 | Shinko Electric Ind Co Ltd | 配線基板及び半導体装置の製造方法 |
JP5481724B2 (ja) * | 2009-12-24 | 2014-04-23 | 新光電気工業株式会社 | 半導体素子内蔵基板 |
JP2013016763A (ja) * | 2011-07-06 | 2013-01-24 | Hitachi Chem Co Ltd | 半導体素子搭載用部材及び半導体装置 |
JP6056386B2 (ja) * | 2012-11-02 | 2017-01-11 | 凸版印刷株式会社 | 貫通電極付き配線基板及びその製造方法 |
-
2014
- 2014-12-17 JP JP2014255310A patent/JP2016115884A/ja active Pending
-
2015
- 2015-12-01 WO PCT/JP2015/005974 patent/WO2016098296A1/ja active Application Filing
- 2015-12-16 TW TW104142200A patent/TW201633469A/zh unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111403630A (zh) * | 2017-03-08 | 2020-07-10 | 堺显示器制品株式会社 | 有机el设备的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2016098296A1 (ja) | 2016-06-23 |
JP2016115884A (ja) | 2016-06-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8324740B2 (en) | Semiconductor device, and method of manufacturing multilayer wiring board and semiconductor device | |
KR102450822B1 (ko) | 반도체 장치의 제조 방법 | |
TWI446465B (zh) | Manufacturing method of semiconductor device | |
US8450848B2 (en) | Semiconductor device and method for fabricating the same | |
US20150214207A1 (en) | Chip stack, semiconductor devices having the same, and manufacturing methods for chip stack | |
US10679916B2 (en) | Circuit module and manufacturing method thereof | |
TWI627689B (zh) | 半導體裝置 | |
JPWO2020090601A1 (ja) | 半導体パッケージ用配線基板及び半導体パッケージ用配線基板の製造方法 | |
JP2009252942A (ja) | 部品内蔵配線板、部品内蔵配線板の製造方法 | |
TW201429328A (zh) | 印刷電路板及其製造方法 | |
JP6656836B2 (ja) | 実装構造体及びその製造方法 | |
TW201633469A (zh) | 半導體裝置及其製造方法 | |
JP2009111307A (ja) | 部品内蔵配線板 | |
JP2008028135A (ja) | 半導体装置およびその製造方法 | |
JP7196936B2 (ja) | 半導体装置用配線基板の製造方法、及び半導体装置用配線基板 | |
JP7089453B2 (ja) | 配線基板及びその製造方法 | |
JP2012033692A (ja) | 半導体装置および半導体装置の製造方法 | |
JP6069960B2 (ja) | 半導体パッケージの製造方法 | |
JP2021097104A (ja) | 複合配線基板及び複合配線基板の製造方法 | |
JP2013102020A (ja) | 半導体パッケージ基板 | |
JP2013062472A (ja) | 半導体パッケージおよびその製造方法 | |
JP5509295B2 (ja) | 半導体装置 | |
JP5649771B2 (ja) | 部品内蔵配線板 | |
JP6007956B2 (ja) | 部品内蔵配線板 | |
JP2010040891A (ja) | 部品内蔵配線板 |