TW201618257A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW201618257A
TW201618257A TW104113351A TW104113351A TW201618257A TW 201618257 A TW201618257 A TW 201618257A TW 104113351 A TW104113351 A TW 104113351A TW 104113351 A TW104113351 A TW 104113351A TW 201618257 A TW201618257 A TW 201618257A
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Taiwan
Prior art keywords
conductive
semiconductor package
solder ball
conductive via
pedestal
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TW104113351A
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English (en)
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TWI636536B (zh
Inventor
黃清流
于達人
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聯發科技股份有限公司
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Publication of TW201618257A publication Critical patent/TW201618257A/zh
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Publication of TWI636536B publication Critical patent/TWI636536B/zh

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Abstract

本發明提供一種半導體封裝。半導體封裝包括一基座，基座具有一元件貼附面和相對於上述元件貼附面的一焊球貼附面；一導電介層孔插塞，穿過上述基座；上述導電介層孔插塞的一第一末端表面對齊於上述基座的上述元件貼附面；一半導體晶片，藉由一導電結構固著於上述基座上，上述導電結構係接觸上述導電介層孔插塞的第一末端表面。

Description

半導體封裝
本發明係有關於一種半導體封裝，特別是有關於一種用於高密度半導體封裝的基座設計。
對於半導體晶片設計而言，會要求用於多功能晶片的增加的輸入/輸出(I/O)引腳數。上述需求會要求印刷電路板(PCB)製造商縮小線寬或線距或發展出晶片直接接觸(direct chip attach，DCA)半導體。因此，多功能晶片封裝因增加了輸入/輸出(I/O)連接數量會導致熱電特性問題，舉例來說，散熱問題、串音(cross talk)、訊號傳輸延遲(signal propagation delay)或射頻(RF)電路的電磁干擾等問題。上述熱電特性問題會影響產品的可靠度和品質。
因此，在此技術領域中，有需要一種半導體封裝，以改善上述缺點。
本發明之一實施例係提供一種半導體封裝。上述半導體封裝包括一基座，具有一元件貼附面和相對於上述元件貼附面的一焊球貼附面；一導電介層孔插塞，穿過上述基座；一半導體晶片，藉由一導電結構固著於上述基座上，其中上述導電結構係接觸上述導電介層孔插塞的一第一末端表面。
本發明之另一實施例係提供一種半導體封裝。上述半導體封裝包括一基座，具有一元件貼附面；一導電介層孔插塞，穿過上述基座；一半導體晶片，固著於上述基座上，其中上述半導體晶片藉由一導電結構接觸上述導電介層孔插塞。
本發明之又一實施例係提供半導體封裝。上述半導體封裝包括一導電介層孔插塞，穿過一基座，上述導電介層孔插塞具有一第一末端表面和相對於上述第一末端表面的一第二末端表面；一半導體晶片，藉由一導電結構接觸上述導電介層孔插塞的上述第一末端表面；一焊球，接觸上述導電介層孔插塞的上述第二末端表面。
200、200-1、200-2‧‧‧基座
222、224、226、228、242a~242c、244a~244c、246a~246c、248a~248c‧‧‧導電結構
201、201-1、201-2‧‧‧元件貼附面
203、203-1、203-2‧‧‧焊球貼附面
202a、204a、206a、208a、202a-1、204a-1、206a-1、208a-1、202a-2、204a-2、206a-2、208a-2‧‧‧第一末端表面
202b、204b、206b、208b、202b-1、204b-1、206b-1、208b-1、202b-2、204b-2、206b-2、208b-2‧‧‧第二末端表面
202、204、206、208、202-1、202-2、204-1、204-2、206-1、206-2、208-1、208-2、232a~232c、234a~234c、236a~236c、238a~238c‧‧‧導電介層孔插塞
212、214、216、218、252a~252c、254a~254c、256a~256c、258a~258c‧‧‧焊球
222a、224a、226a、228a‧‧‧導電柱
222b、224b、226b、228b‧‧‧導電阻障層
222c、224c、226c、228c‧‧‧焊錫蓋層
230‧‧‧阻焊層
232‧‧‧覆晶填充材質
234‧‧‧成型材質
300‧‧‧半導體晶片
302、304、306、308‧‧‧焊墊
310‧‧‧第一保護層
312‧‧‧第二保護層
314、316、318、320‧‧‧凸塊下金屬層圖案
400‧‧‧載板
401‧‧‧頂面
403‧‧‧底面
402a、402b‧‧‧導電種晶層
406a、406b‧‧‧基座材料層
500‧‧‧半導體封裝
第1圖顯示本發明一些實施例之一半導體封裝之剖面示意圖。
第2圖顯示本發明一些實施例之一半導體封裝之平面示意圖，其顯示半導體晶粒的導電結構和半導體封裝的基座的導電介層孔插塞之間的關係。
第3A、3B圖顯示本發明一些實施例之一半導體封裝之一基座的製造方法的剖面示意圖。
為了讓本發明之目的、特徵、及優點能更明顯易懂，下文特舉實施例，並配合所附圖示，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非 用以限制本發明。且實施例中圖式標號之部分重複，係為了簡化說明，並非意指不同實施例之間的關聯性。
第1圖顯示本發明一些實施例之一半導體封裝500之剖面示意圖。在本發明一些實施例中，上述半導體封裝500可為一覆晶封裝體(flip chip package)，其使用例如一銅柱狀凸塊(copper pillar bump)的一導電結構將一半導體裝置連接至一基板。如第1圖所示，在本發明一些實施例中，上述半導體封裝500包括一基座200、一半導體晶粒300和導電結構222、224、226、228。
如第1圖所示之本發明一些實施例中，上述基座200包括一元件貼附面(device attach surface)201和相對於上述元件貼附面201的一焊球貼附面203。在本發明一些實施例中，例如為一印刷電路板(print circuit board，PCB)的上述基座200，可為由例如聚丙烯(polypropylene，PP)來形成的一基板。在本發明一些實施例中，複數個導電介層孔插塞202、204、206、208係設置穿過基座200。如第1圖所示，上述導電介層孔插塞202包括一第一末端表面202a相對於第一末端表面202a的一第二末端表面202b。
在本發明一些實施例中，上述導電介層孔插塞202的第一末端表面202a係對齊於基座200的元件貼附面201。上述導電介層孔插塞202的第二末端表面202b與基座200的焊球貼附面203不共平面。類似地，上述導電介層孔插塞204、206、208的第一末端表面204a、206a、208a係分別對齊於基座200的元件貼附面201。上述導電介層孔插塞204、206、208的第二末 端表面204b、206b、208b與基座200的焊球貼附面203不共平面。在本發明一些其他實施例中，可分別於上述導電介層孔插塞202、204、206、208的第一末端表面202a、204a、206a、208a上電鍍額外的金屬薄膜。上述額外的金屬薄膜可視為上述導電介層孔插塞202、204、206、208的凸出部分。因此，上述導電介層孔插塞202、204、206、208的第一末端表面202a、204a、206a、208a可凸出於基座200的元件貼附面201。
第3A、3B圖顯示本發明一些實施例之用於半導體封裝500之基座200(基座200包括基座200-1和200-2)的製造方法的剖面示意圖。第3A、3B圖也顯示導電介層孔插塞的第一末端表面是如何能夠對齊基座的元件貼附面。在本發明一些實施例中，用於半導體封裝500之基座的製造方法也可稱為一雙側基座製程(double-sided base fabricating process)。上述圖式中的各元件如有與第1圖所示相同或相似的部分，則可參考前面的相關敍述，在此不做重複說明。如第3A圖所示，提供一載板400，上述載板400的一頂面401和一底面403上具有導電種晶層402a和402b。在本發明一些實施例中，載板400可包括FR4玻璃樹脂(FR4 glass epoxy)或無應力鋼板(stainless steel)。並且，導電種晶層402a和402b係做為後續形成之位於上述載板400的頂面401和底面403上的基座的內連線導線的種晶層。在本發明一實施例中，導電種晶層402a和402b可包括銅。
接著，如第3A圖所示，進行一堆疊製程，將一基座材料層406a和一基座材料層406b分別堆疊於載板400的頂面401和底面403上，其中基座材料層406a和406b分別覆蓋導電種 晶層402a和402b。在本發明一些實施例中，同時於上述載板400的頂面401和底面403上進行基座材料層406a和406b的堆疊製程。在本發明一實施例中，基座材料層406a和406b可包括聚丙烯(polypropylene，PP)。在本發明一些實施例中，基座材料層406a包括一元件貼附面201-1和一焊球貼附面203-1。類似地，基座材料層406b包括一元件貼附面201-2和一焊球貼附面203-2。如第3A圖所示，元件貼附面201-1和201-2分別接觸導電種晶層402a和402b。焊球貼附面203-1和203-2分別相對於元件貼附面201-1和201-2。在本發明一些實施例中，焊球貼附面203-1和203-2分別遠離於導電種晶層402a和402b。
接著，請再參考第3A圖，進行一鑽孔製程，以形成穿過基座材料層406a和406b的開口(圖未顯示)，以定義後續形成的導電介層孔插塞202-1、202-2、204-1、204-2、206-1、206-2、208-1和208-2的位置。在本發明一些實施例中，上述鑽孔製程包括一雷射鑽孔製程、一蝕刻鑽孔製程或一機械鑽孔製程。接著，進行一電鍍製程和一非等向性蝕製程，將一導電材料填入上述開口中，以形成穿過基座材料層406a的導電介層孔插塞202-1、204-1、206-1和208-1，且形成穿過基座材料層406b的導電介層孔插塞202-2、204-2、206-2和208-2。在本發明一些實施例中，同時分別於上述基座材料層406a和406b上進行上述鑽孔製程、電鍍製程和非等向性蝕製程。在本發明一些實施例中，上述電鍍製程可包括一有電電鍍製程。
如第3A圖所示，導電介層孔插塞202-1、204-1、206-1和208-1分別具有第一末端表面202a-1、204a-1、206a-1 和208a-1和第二末端表面202b-1、204b-1、206b-1和208b-1。第二末端表面202b-1、204b-1、206b-1和208b-1分別相對於第一末端表面202a-1、204a-1、206a-1和208a-1。類似地，導電介層孔插塞202-2、204-2、206-2和208-2分別具有第一末端表面202a-2、204a-2、206a-2和208a-2和第二末端表面202b-2、204b-2、206b-2和208b-2。第二末端表面202b-2、204b-2、206b-2和208b-2分別相對於第一末端表面202a-2、204a-2、206a-2和208a-2。
如第3A圖所示，基座材料層406a的元件貼附面201-1和基座材料層406b的元件貼附面201-2分別接觸導電種晶層402a和402b。因此，進行上述電鍍製程和非等向性蝕製程之後，導電介層孔插塞202-1、204-1、206-1和208-1的第一末端表面202a-1、204a-1、206a-1和208a-1係對齊於基座材料層406a的元件貼附面201-1。第二末端表面202b-1、204b-1、206b-1和208b-1則不需與基座材料層406a的焊球貼附面203-1共平面。類似地，導電介層孔插塞202-2、204-2、206-2和208-2的第一末端表面202a-2、204a-2、206a-2和208a-2係對齊於基座材料層406b的元件貼附面201-2。第二末端表面202b-2、204b-2、206b-2和208b-2則不需與基座材料層406b的焊球貼附面203-2共平面。
接著，如第3B圖所示，將基座材料層406a和基座材料層406b分別從上述載板400的頂面401和底面403分離，以形成彼此分離的基座200-1和200-2。接著，請再參考第3B圖，分別從基座200-1和200-2移除導電種晶層402a和402b。
請再參考第1圖，因為上述導電介層孔插塞202、 204、206、208的第一末端表面202a、204a、206a、208a係對齊基座200的元件貼附面201。上述導電介層孔插塞202、204、206、208的第一末端表面202a、204a、206a、208a可提供例如銅柱狀凸塊的導電結構222、224、226、228直接設置於其上。在本發明一些實施例中，上述導電介層孔插塞202、204、206、208的第二末端表面202b、204b、206b、208b係分別提供焊球212、214、216、218直接設置於其上。
如第1圖所示，在本發明一些實施例中，半導體晶片300係藉由導電結構222、224、226、228固著於基座200的元件貼附面201上。在本發明一些實施例中，半導體晶片300的一主動表面係藉由一接合製程面向基座200。半導體晶片300的電路係設置於上述主動表面上。在本發明一些實施例中，焊墊302、304、306、308係設置於半導體晶片300的電路的頂部上。在本發明一些實施例中，焊墊302、304、306、308係屬於半導體晶片300的內連線結構(interconnection structure)(圖未顯示)的最頂層金屬層。在本發明一些實施例中，焊墊302、304、306、308係配置於半導體晶片300的中間區域內，且用以傳遞半導體晶片300的接地信號或電源信號。並且，為了清楚顯示用於半導體晶片300的電源或接地焊墊302、304、306、308的導電結構222、224、226、228與基座200的導電介層孔插塞202、204、206、208之間的關係，用於半導體晶片的訊號信號焊墊在圖式(第1、2圖)中不予顯示。
如第1圖所示，在本發明一些實施例中，第一保護層310係順應性形成且覆蓋半導體晶片300的焊墊302、304、 306、308。在本發明一些實施例中，可利用沉積製程和圖案化製程形成第一保護層310。在本發明一些實施例中，可由包括但並非限制於氧化物、氮化物或氮氧化物的材料形成第一保護層310。在本發明一些實施例中，第一保護層310具有位於焊墊302、304、306、308上的多個開口，使焊墊302、304、306、308的一部分分別從上述多個開口暴露出來。
在本發明一些實施例中，一第二保護層312係形成第一保護層310上，第二保護層312具有穿過其中的多個開口。在本發明一些實施例中，可利用塗佈製程、圖案化製程和硬化製程形成第二保護層312。在本發明一些實施例中，第二保護層312可包括但並非限制於聚醯亞胺(polyimide)，當半導體晶片300遭受不同類型的環境應力時，第二保護層312可對半導體晶片300提供可靠的絶緣。每一個焊墊302、304、306、308的一部分分別從第二保護層312的上述多個開口暴露出來。
在本發明一些實施例中，半導體封裝500係使用導電結構222、224、226、228分別將半導體晶片300的接地焊墊和電源焊墊連接至基座200，如第1圖所示(第1圖並未顯示用於半導體晶片的訊號信號焊墊的導電結構)。在本發明一些實施例中，每一個導電結構可為一銅柱狀凸塊結構，其可由包括一凸塊下金屬層(under bump metallurgy(UBM)layer)、一導電柱、一導電阻障層和一焊錫蓋層(solder cap)的一金屬堆疊構成。在本發明一些實施例中，導電結構222、224、226、228可為導線上凸塊(bump on trace，BOT)結構，且於如第2圖所示的一平面圖中可為一長方形。在本發明一些其他實施例中，導電 結構222、224、226、228可設計為具180度旋轉對稱的其他形狀，舉例來說，上述導電結構222、224、226、228可為一八角形(octangular shape)或一橢圓形(oval-shape)。
如第1圖所示，在本發明一些實施例中，上述導電結構222、224、226、228的凸塊下金屬層圖案(UBM layer pattern)314、316、318、320係形成於設置於半導體晶片300上的第二保護層312上。在本發明一些實施例中，可利用例如一濺鍍法或電鍍法的一沉積方式和後續的一非等向性蝕刻製程來形成凸塊下金屬層圖案314、316、318、320。係於形成導電柱之後進行上述非等向性蝕刻製程。在本發明一些實施例中，凸塊下金屬層圖案314、316、318、320襯墊於第二保護層312的開口的側壁和底面上。並且，凸塊下金屬層圖案314、316、318、320係延伸第二保護層312的頂面的上方。在本發明一實施例中，凸塊下金屬層314、316、318、320可包括一鈦層和位於鈦層上的一銅層。
如第1圖所示，在本發明一些實施例中，導電柱222a、224a、226a、228a係分別形成於凸塊下金屬層圖案314、316、318、320上。導電柱222a、224a、226a、228a係彼此隔開。在本發明一些實施例中，導電柱222a、224a、226a、228a分別填充設置於半導體晶片300上的第二保護層312的上述多個開口中。注意位於同一開口246a內的導電柱和凸塊下金屬層可形成最終導電結構的一集成插塞(integral plug)。可藉由一乾膜光阻或液態光阻圖案(圖未顯示)定義導電柱222a、224a、226a、228a的形成位置。在本發明一些實施例中，導電柱222a、 224a、226a、228a可作為後續形成之導電結構的焊點(solder joint)，而導電結構係用於傳輸設置於其上的半導體晶片300的接地(ground)信號或電源(power)信號。因此，導電柱222a、224a、226a、228a可幫助增加導電結構的機械強度。在本發明一些實施例中，可由銅形成導電柱222a、224a、226a、228a，以避免在一後續回焊製程期間變形。
如第1圖所示，在本發明一些實施例中，導電阻障層222b、224b、226b、228b係分別形成於相應的導電柱222a、224a、226a、228a上。在本發明一些實施例中，可利用電鍍法形成導電阻障層222b、224b、226b、228b。在本發明一些實施例中，導電阻障層222b、224b、226b、228b可為選擇性的元件，以作為後續形成於其上的焊錫蓋層的一種晶層(seed layer)、一黏著層(adhesion layer)和一阻障層(barrier layer)。在本發明一些實施例中，導電阻障層222b、224b、226b、228b可包括鎳。在本發明一些實施例中，導電阻障層的數量可相應於設計於半導體晶片300上的導電柱的數量。
如第1圖所示，在本發明一些實施例中，焊錫蓋層222c、224c、226c、228c係分別形成於相應的導電阻障層222b、224b、226b、228b上。在本發明一些實施例中，可利用一圖案化光阻層上電鍍一焊錫材料的方式，或利用一網版印刷製程和後續的一回焊製程的方式形成焊錫蓋層222c、224c、226c、228c。如第1圖所示，凸塊下金屬層圖案314、導電柱222a、導電阻障層222b(選擇性元件)、焊錫蓋層222c可共同形成導電結構222。凸塊下金屬層圖案316、導電柱224a、導電阻障層 224b(選擇性元件)、焊錫蓋層224c可共同形成導電結構224。凸塊下金屬層圖案318、導電柱226a、導電阻障層226b(選擇性元件)、焊錫蓋層226c可共同形成導電結構226。凸塊下金屬層圖案320、導電柱228a、導電阻障層228b(選擇性元件)、焊錫蓋層228c可共同形成導電結構228。
如第1圖所示，在本發明一些實施例中，一阻焊層(solder resistance layer)230係設置於基座200上，且遠離於半導體晶片300和基座200的一重疊區域。在本發明一些實施例中，可利用一圖案化光阻層上電鍍一焊錫材料的方式，或利用一網版印刷製程形成阻焊層230。
如第1圖所示，在本發明一些實施例中，可於半導體晶片300和基座200之間的一間隙中導入一覆晶填充材質232。覆晶填充材質232係覆蓋導電結構222、224、226、228，且相鄰於阻焊層230。在本發明一些實施例中，覆晶填充材質232可包括毛細覆晶填充材質(capillary underfill，CUF)、成型覆晶填充材質(molded underfill，MUF)或上述組合。
如第1圖所示，一成型材質(molding compound)234，形成覆蓋半導體晶片300、阻焊層230、覆晶填充材質232和接近於半導體晶片300之基座200的元件貼附面201。在本發明一些實施例中，可由例如樹脂的成型材料形成成型材質234。
第2圖顯示本發明一些實施例之一半導體封裝500之半導體晶片300的平面示意圖。並且，第2圖顯示半導體晶片的導電結構和半導體封裝的基座的導電介層孔插塞之間的關 係。第1圖也為沿第2圖的A-A’切線的剖面示意圖。注意為了清楚顯示用於半導體晶片的電源焊墊或接地焊墊的導電結構與半導體封裝的基座的導電介層孔插塞之間的關係，相應於半導體晶片的訊號信號焊墊的導電結構與導電介層孔插塞在第2圖中不予顯示。並且，半導體封裝500的覆晶填充材質和覆晶填充材質在第2圖中不予顯示。
如第1、2圖所示，在本發明一些實施例中，上述導電介層孔插塞202、204、206、208的第一末端表面202a、204a、206a、208a係對齊基座200的元件貼附面201。上述導電介層孔插塞202、204、206、208的第一末端表面202a、204a、206a、208a可提供例如銅柱狀凸塊的導電結構222、224、226、228直接設置於其上。因此，上述導電介層孔插塞202、204、206、208的第一末端表面202a、204a、206a、208a可分別視為導電結構222、224、226、228和導電介層孔插塞202、204、206、208之間的界面。在本發明一些實施例中，上述導電介層孔插塞202、204、206、208的第二末端表面202b、204b、206b、208b係分別提供焊球212、214、216、218直接設置於其上。因此，上述導電介層孔插塞202、204、206、208的第二末端表面202b、204b、206b、208b可分別視為焊球212、214、216、218和導電介層孔插塞202、204、206、208之間的界面。
如第1、2圖所示，在本發明一些實施例中，基座200的導電介層孔插塞係定義為僅沿著實質上垂直於基座200的元件貼附面201和焊球貼附面的一方向延伸。導電介層孔插塞之接近於基座200的元件貼附面201的末端表面不具有任何 重佈線繞線功能。換句話說，基座200的導電介層孔插塞不具有實質上沿著基座200的元件貼附面201延伸的任何線段部分。在本發明一些實施例中，沒有任何的導電焊墊設置於基座上，且覆蓋導電介層孔插塞之接近於基座200的元件貼附面201的末端表面。換句話說，沒有導電焊墊設置於導電結構和穿過基座200的導電介層孔插塞之間。在本發明一些實施例中，在如第1圖所示的剖面圖和如第2圖所示的平面圖中，上述導電介層孔插塞202、204、206、208的第一末端表面202a、204a、206a、208a分別與導電介層孔插塞202、204、206、208的第二末端表面202b、204b、206b、208b完全重疊。類似地，如第2圖所示之本發明一些實施例中，導電介層孔插塞232a~232c、234a~234c、236a~236c、238a~238c之用以提供導電結構242a~242c、244a~244c、246a~246c、248a~248c直接設置於其上的第一末端表面，係設計分別與導電介層孔插塞232a~232c、234a~234c、236a~236c、238a~238c之用以提供焊球252a~252c、254a~254c、256a~256c、258a~258c直接設置於其上的第二末端表面完全重疊。
在本發明一些實施例中，在如第1圖所示的剖面圖和如第2圖所示的平面圖中，半導體封裝500的導電結構可設計與相應的基座200的導電介層孔插塞完全重疊或部分重疊。導電結構的配置並未被相應的基座的導電介層孔插塞的位置所限制。舉例來說，導電結構不需設置與相應的基座的導電介層孔插塞橫向隔開。因此，可以提昇半導體晶片300的輸入/輸出(I/O)連接數量和基座200的導電介層孔插塞數量，以達到高密 度半導體封裝的目標。舉例來說，可設計導電結構222、226、242a、242b、242c、244b與相應的基座200的導電介層孔插塞202、206、232a、232b、232c、234b完全重疊，如第1和2圖所示。舉例來說，可設計導電結構224、228、244a、244c、246a-246c、248a-248c與相應的基座200的導電介層孔插塞204、208、234a、234c、236a-236c、238a-238c部分重疊，如第1和2圖所示。
在本發明一些實施例中，在如第1圖所示的剖面圖和如第2圖所示的平面圖中，基座200的導電介層孔插塞可設計與位於基座200上之相應的焊球完全重疊或部分重疊。因此，在如第1和2圖所示之實施例中，半導體封裝500的導電結構可設計與相應的焊球完全重疊或部分重疊。舉例來說，可設計導電結構222、226、242a、242b、242c、244b與位於基座200上之相應的焊球212、216、252a、252b、252c、254b完全重疊，如第1和2圖所示。舉例來說，可設計導電結構224、228、244a、244c、246a-246c、248a-248c與位於基座200上之相應的焊球214、218、254a、254c、256a-256c、258a-258c部分重疊，如第1和2圖所示。
本發明實施例係提供一種半導體封裝。上述半導體封裝使用導電結構將半導體晶片連接至基座，上述導電結構接觸穿過基座的相應的導電介層孔插塞。上述導電結構係設計連接至半導體晶片的電源焊墊或接地焊墊。根據基座的設計，導電結構相應的導電介層孔插塞之間的界面係對齊於基座的元件貼附面。上述導電結構接觸可設計不需任何的導電焊墊或 重佈線圖案而接觸至相應的導電介層孔插塞。導電結構的配置並未被相應的基座的導電介層孔插塞的位置所限制。可以提昇半導體晶片的輸入/輸出(I/O)連接數量和基座的導電介層孔插塞數量，以達到高密度半導體封裝的目標。並且，本發明實施例的半導體封裝可改善跨過半導體封裝中的網路電路的電壓降。再者，半導體晶片產生的熱因為經過較短的路徑(上述導電結構接觸可設計不需任何的導電焊墊或重佈線圖案而接觸至相應的導電介層孔插塞)而可以快速地散逸至外界。可以提昇半導體封裝的散熱性能。
雖然本發明已以實施例揭露於上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧基座
222、224、226、228‧‧‧導電結構
201‧‧‧元件貼附面
203‧‧‧焊球貼附面
202a、204a、206a、208a‧‧‧第一末端表面
202b、204b、206b、208b‧‧‧第二末端表面
202、204、206、208‧‧‧導電介層孔插塞
212、214、216、218‧‧‧焊球
222a、224a、226a、228a‧‧‧導電柱
222b、224b、226b、228b‧‧‧導電阻障層
222c、224c、226c、228c‧‧‧焊錫蓋層
230‧‧‧阻焊層
232‧‧‧覆晶填充材質
234‧‧‧成型材質
300‧‧‧半導體晶片
302、304、306、308‧‧‧焊墊
310‧‧‧第一保護層
312‧‧‧第二保護層
314、316、318、320‧‧‧凸塊下金屬層圖案
500‧‧‧半導體封裝

Claims (26)

  1. 一種半導體封裝，包括：一基座，具有一元件貼附面和相對於該元件貼附面的一焊球貼附面；一導電介層孔插塞，穿過該基座；以及一半導體晶片，藉由一導電結構固著於該基座上，其中該導電結構係接觸該導電介層孔插塞的一第一末端表面。
  2. 如申請專利範圍第1項所述之半導體封裝，其中該導電介層孔插塞的第一末端表面對齊於該元件貼附面，且該導電介層孔插塞包括相對於該第一末端表面的一第二末端表面，其中該第二末端表面係遠離於該半導體晶片。
  3. 如申請專利範圍第2項所述之半導體封裝，其中該導電介層孔插塞的該第二末端表面與該基座的該焊球貼附面不共平面。
  4. 如申請專利範圍第2項所述之半導體封裝，其中該導電結構與該導電介層孔插塞完全重疊。
  5. 如申請專利範圍第2項所述之半導體封裝，其中該導電結構與該導電介層孔插塞部分重疊。
  6. 如申請專利範圍第2項所述之半導體封裝，更包括：一焊球，設置於該基座的該焊球貼附面上，且接觸該導電介層孔插塞的該第二末端表面。
  7. 如申請專利範圍第6項所述之半導體封裝，其中該焊球與該半導體晶片的該導電結構重疊。
  8. 如申請專利範圍第6項所述之半導體封裝，其中該焊球與該 半導體晶片的該導電結構完全重疊。
  9. 如申請專利範圍第2項所述之半導體封裝，其中該半導體晶片的該導電結構係耦接至該半導體晶片的一電源焊墊或一接地焊墊。
  10. 如申請專利範圍第2項所述之半導體封裝，其中該半導體晶片的該導電結構為一凸塊接合至導線結構，且於一平面圖中為一長方形。
  11. 一種半導體封裝，包括：一基座，具有一元件貼附面；一導電介層孔插塞，穿過該基座；以及一半導體晶片，固著於該基座上，其中該半導體晶片藉由一導電結構接觸該導電介層孔插塞。
  12. 如申請專利範圍第11項所述之半導體封裝，其中該基座具有相對於該元件貼附面的一焊球貼附面，其中該焊球貼附面係遠離於該半導體晶片。
  13. 如申請專利範圍第12項所述之半導體封裝，更包括：一焊球，設置於該基座的該焊球貼附面上，且接觸該導電介層孔插塞的該第二末端表面。
  14. 如申請專利範圍第13項所述之半導體封裝，其中位於該導電結構和該導電介層孔插塞之間的一第一界面係對齊該基座的該元件貼附面，且位於該導電結構和該焊球之間的一第二界面係相對於該第一界面，其中該第二界面與該基座的該焊球貼附面不共平面。
  15. 如申請專利範圍第11項所述之半導體封裝，其中該導電結 構與該導電介層孔插塞完全重疊。
  16. 如申請專利範圍第11項所述之半導體封裝，其中該導電結構與該導電介層孔插塞部分重疊。
  17. 如申請專利範圍第13項所述之半導體封裝，其中該焊球與該半導體晶片的該導電結構完全重疊。
  18. 如申請專利範圍第11項所述之半導體封裝，其中該焊球與該半導體晶片的該導電結構部分重疊。
  19. 如申請專利範圍第11項所述之半導體封裝，其中該半導體晶片的該導電結構為一凸塊接合至導線結構，且於一平面圖中為一長方形。
  20. 一種半導體封裝，包括：一導電介層孔插塞，穿過一基座，該導電介層孔插塞具有一第一末端表面和相對於該第一末端表面的一第二末端表面；一半導體晶片，藉由一導電結構接觸該導電介層孔插塞的該第一末端表面；以及一焊球，接觸該導電介層孔插塞的該第二末端表面。
  21. 如申請專利範圍第20項所述之半導體封裝，其中該導電介層孔插塞的該第二末端表面係接近該基座之相對於該元件貼附面的一焊球貼附面。
  22. 如申請專利範圍第21項所述之半導體封裝，其中該第一末端表面對齊該基座的一表面，且該第二末端表面與該基座的該焊球貼附面不共平面。
  23. 如申請專利範圍第22項所述之半導體封裝，其中該基座的 該表面為一元件貼附面。
  24. 如申請專利範圍第20項所述之半導體封裝，其中該焊球與該導電結構完全重疊。
  25. 如申請專利範圍第20項所述之半導體封裝，其中該焊球與該半導體晶片的該導電結構部分重疊。
  26. 如申請專利範圍第20項所述之半導體封裝，其中該半導體晶片的該導電結構為一凸塊接合至導線結構，且於一平面圖中為一長方形。
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