TW201606511A - 用於晶片至晶片通信之系統及方法 - Google Patents

用於晶片至晶片通信之系統及方法 Download PDF

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Publication number
TW201606511A
TW201606511A TW104123353A TW104123353A TW201606511A TW 201606511 A TW201606511 A TW 201606511A TW 104123353 A TW104123353 A TW 104123353A TW 104123353 A TW104123353 A TW 104123353A TW 201606511 A TW201606511 A TW 201606511A
Authority
TW
Taiwan
Prior art keywords
master
wafer
slave
control system
receiver
Prior art date
Application number
TW104123353A
Other languages
English (en)
Chinese (zh)
Inventor
傑森 艾倫 瑟斯頓
肯尼斯 路斯 阿爾庫迪亞
Original Assignee
高通公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 高通公司 filed Critical 高通公司
Publication of TW201606511A publication Critical patent/TW201606511A/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Electric Clocks (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
TW104123353A 2014-07-18 2015-07-17 用於晶片至晶片通信之系統及方法 TW201606511A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462026063P 2014-07-18 2014-07-18
US14/801,310 US9792247B2 (en) 2014-07-18 2015-07-16 Systems and methods for chip to chip communication

Publications (1)

Publication Number Publication Date
TW201606511A true TW201606511A (zh) 2016-02-16

Family

ID=55074702

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104123353A TW201606511A (zh) 2014-07-18 2015-07-17 用於晶片至晶片通信之系統及方法

Country Status (7)

Country Link
US (1) US9792247B2 (enExample)
EP (1) EP3170090B1 (enExample)
JP (1) JP2017528946A (enExample)
KR (1) KR20170034888A (enExample)
CN (1) CN106796563B (enExample)
TW (1) TW201606511A (enExample)
WO (1) WO2016011341A1 (enExample)

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US9621339B1 (en) 2016-05-11 2017-04-11 Quanta Computer Inc. Host devices and data transmission methods
TWI665608B (zh) * 2016-10-20 2019-07-11 日商東芝記憶體股份有限公司 介面系統
TWI920136B (zh) 2021-02-24 2026-04-01 台灣積體電路製造股份有限公司 產生方法、非時變機器可讀取媒體及積體電路設計系統

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US10218391B1 (en) * 2017-08-02 2019-02-26 Qualcomm Incorporated Systems and methods providing a low-power mode for serial links
KR102450521B1 (ko) * 2018-01-09 2022-10-05 삼성전자주식회사 모바일 장치 및 그것의 인터페이싱 방법
DE102019106030A1 (de) * 2018-03-22 2019-09-26 Infineon Technologies Ag Radar-system mit mehreren radar-chips
US10382190B1 (en) * 2018-07-13 2019-08-13 Qualcomm Incorporated Optimizing clock/data recovery power while maintaining link stability in source synchronous applications
US10727838B2 (en) 2018-07-13 2020-07-28 Qualcomm Incorporated Systems and methods for power conservation in a phase locked loop (PLL)
US11824009B2 (en) 2018-12-10 2023-11-21 Preferred Networks, Inc. Semiconductor device and data transferring method for semiconductor device
US11469781B2 (en) * 2019-03-07 2022-10-11 Mediatek Inc. Method for transferring signals via transmission interface and communications apparatus utilizing the same
CN110418247B (zh) * 2019-07-26 2021-03-05 昆腾微电子股份有限公司 一种音频接收芯片和音频接收机
CN112119366A (zh) * 2019-10-30 2020-12-22 深圳市大疆创新科技有限公司 时间同步方法、装置、系统和可移动平台
US11449453B2 (en) * 2020-04-16 2022-09-20 Mediatek Inc. Multi-package system using configurable input/output interface circuits for single-ended intra-package communication and differential inter-package communication
CN116868177A (zh) * 2021-03-30 2023-10-10 华为技术有限公司 控制芯片的方法和集成电路系统
US11775004B2 (en) 2021-09-10 2023-10-03 International Business Machines Corporation Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module
CN114488772A (zh) * 2022-02-17 2022-05-13 深圳市伟安特电子有限公司 一种用于智能汽车控制总成的主从芯片
CN115640251B (zh) * 2022-09-01 2025-07-22 中国航空工业集团公司洛阳电光设备研究所 一种基于Xilinx FPGA的串行高速电路及自适应配置方法
CN115879399B (zh) * 2023-02-16 2023-05-09 深圳市奇普乐芯片技术有限公司 芯片系统的生成方法、装置、终端及存储介质
US20250348129A1 (en) * 2024-05-09 2025-11-13 Qualcomm Incorporated Enhanced deep sleep operations for multiple chip systems

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JP4484629B2 (ja) * 2004-08-24 2010-06-16 株式会社リコー クロックデータリカバリ回路及び電圧制御発振回路
US7668238B1 (en) * 2005-12-12 2010-02-23 Xilinx, Inc. Method and apparatus for a high speed decision feedback equalizer
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US9621339B1 (en) 2016-05-11 2017-04-11 Quanta Computer Inc. Host devices and data transmission methods
TWI581104B (zh) * 2016-05-11 2017-05-01 廣達電腦股份有限公司 主控元件以及資料傳輸方法
TWI665608B (zh) * 2016-10-20 2019-07-11 日商東芝記憶體股份有限公司 介面系統
TWI735887B (zh) * 2016-10-20 2021-08-11 日商東芝記憶體股份有限公司 記憶體卡
TWI920136B (zh) 2021-02-24 2026-04-01 台灣積體電路製造股份有限公司 產生方法、非時變機器可讀取媒體及積體電路設計系統

Also Published As

Publication number Publication date
EP3170090A1 (en) 2017-05-24
WO2016011341A1 (en) 2016-01-21
CN106796563B (zh) 2020-01-14
JP2017528946A (ja) 2017-09-28
CN106796563A (zh) 2017-05-31
KR20170034888A (ko) 2017-03-29
EP3170090B1 (en) 2019-12-25
US9792247B2 (en) 2017-10-17
US20160019183A1 (en) 2016-01-21

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