KR20170034888A - 칩 대 칩 통신을 위한 시스템들 및 방법들 - Google Patents

칩 대 칩 통신을 위한 시스템들 및 방법들 Download PDF

Info

Publication number
KR20170034888A
KR20170034888A KR1020177001329A KR20177001329A KR20170034888A KR 20170034888 A KR20170034888 A KR 20170034888A KR 1020177001329 A KR1020177001329 A KR 1020177001329A KR 20177001329 A KR20177001329 A KR 20177001329A KR 20170034888 A KR20170034888 A KR 20170034888A
Authority
KR
South Korea
Prior art keywords
control system
chip
master
circuit
slave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020177001329A
Other languages
English (en)
Korean (ko)
Inventor
제이슨 앨런 서스턴
케네스 루이스 아커디아
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20170034888A publication Critical patent/KR20170034888A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • Y02B60/1228—
    • Y02B60/1235—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Electric Clocks (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR1020177001329A 2014-07-18 2015-07-17 칩 대 칩 통신을 위한 시스템들 및 방법들 Withdrawn KR20170034888A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201462026063P 2014-07-18 2014-07-18
US62/026,063 2014-07-18
US14/801,310 2015-07-16
US14/801,310 US9792247B2 (en) 2014-07-18 2015-07-16 Systems and methods for chip to chip communication
PCT/US2015/040887 WO2016011341A1 (en) 2014-07-18 2015-07-17 Systems and methods for chip to chip communication

Publications (1)

Publication Number Publication Date
KR20170034888A true KR20170034888A (ko) 2017-03-29

Family

ID=55074702

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020177001329A Withdrawn KR20170034888A (ko) 2014-07-18 2015-07-17 칩 대 칩 통신을 위한 시스템들 및 방법들

Country Status (7)

Country Link
US (1) US9792247B2 (enExample)
EP (1) EP3170090B1 (enExample)
JP (1) JP2017528946A (enExample)
KR (1) KR20170034888A (enExample)
CN (1) CN106796563B (enExample)
TW (1) TW201606511A (enExample)
WO (1) WO2016011341A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190084755A (ko) * 2018-01-09 2019-07-17 삼성전자주식회사 모바일 장치 및 그것의 인터페이싱 방법

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581104B (zh) * 2016-05-11 2017-05-01 廣達電腦股份有限公司 主控元件以及資料傳輸方法
US9698797B1 (en) 2016-07-14 2017-07-04 Apple Inc. Hierarchical feedback-controlled oscillator techniques
JP6640696B2 (ja) * 2016-10-20 2020-02-05 キオクシア株式会社 インターフェースシステム
CN106533186A (zh) * 2016-10-26 2017-03-22 武汉船舶通信研究所 电磁探测仪器发射机
US10218391B1 (en) * 2017-08-02 2019-02-26 Qualcomm Incorporated Systems and methods providing a low-power mode for serial links
DE102019106030A1 (de) * 2018-03-22 2019-09-26 Infineon Technologies Ag Radar-system mit mehreren radar-chips
US10382190B1 (en) * 2018-07-13 2019-08-13 Qualcomm Incorporated Optimizing clock/data recovery power while maintaining link stability in source synchronous applications
US10727838B2 (en) 2018-07-13 2020-07-28 Qualcomm Incorporated Systems and methods for power conservation in a phase locked loop (PLL)
US11824009B2 (en) 2018-12-10 2023-11-21 Preferred Networks, Inc. Semiconductor device and data transferring method for semiconductor device
US11469781B2 (en) * 2019-03-07 2022-10-11 Mediatek Inc. Method for transferring signals via transmission interface and communications apparatus utilizing the same
CN110418247B (zh) * 2019-07-26 2021-03-05 昆腾微电子股份有限公司 一种音频接收芯片和音频接收机
CN112119366A (zh) * 2019-10-30 2020-12-22 深圳市大疆创新科技有限公司 时间同步方法、装置、系统和可移动平台
US11449453B2 (en) * 2020-04-16 2022-09-20 Mediatek Inc. Multi-package system using configurable input/output interface circuits for single-ended intra-package communication and differential inter-package communication
CN116868177A (zh) * 2021-03-30 2023-10-10 华为技术有限公司 控制芯片的方法和集成电路系统
US11775004B2 (en) 2021-09-10 2023-10-03 International Business Machines Corporation Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module
CN114488772A (zh) * 2022-02-17 2022-05-13 深圳市伟安特电子有限公司 一种用于智能汽车控制总成的主从芯片
CN115640251B (zh) * 2022-09-01 2025-07-22 中国航空工业集团公司洛阳电光设备研究所 一种基于Xilinx FPGA的串行高速电路及自适应配置方法
CN115879399B (zh) * 2023-02-16 2023-05-09 深圳市奇普乐芯片技术有限公司 芯片系统的生成方法、装置、终端及存储介质
US20250348129A1 (en) * 2024-05-09 2025-11-13 Qualcomm Incorporated Enhanced deep sleep operations for multiple chip systems

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5991279A (en) * 1995-12-07 1999-11-23 Vistar Telecommunications Inc. Wireless packet data distributed communications system
US5963609A (en) 1996-04-03 1999-10-05 United Microelectronics Corp. Apparatus and method for serial data communication between plurality of chips in a chip set
US6631144B1 (en) * 1999-12-21 2003-10-07 Intel Corporation Multi-rate transponder system and chip set
JP4484629B2 (ja) * 2004-08-24 2010-06-16 株式会社リコー クロックデータリカバリ回路及び電圧制御発振回路
US7668238B1 (en) * 2005-12-12 2010-02-23 Xilinx, Inc. Method and apparatus for a high speed decision feedback equalizer
JP2007201882A (ja) * 2006-01-27 2007-08-09 Toshiba Corp 半導体集積回路
US7593498B2 (en) 2006-09-29 2009-09-22 Agere Systems Inc. Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications
US8204167B2 (en) 2007-05-21 2012-06-19 Infineon Technologies Ag Master slave interface
US7929919B2 (en) * 2008-05-15 2011-04-19 Hewlett-Packard Development Company, L.P. Systems and methods for a PLL-adjusted reference clock
KR101248453B1 (ko) * 2008-12-09 2013-04-01 도요타지도샤가부시키가이샤 비접촉 전력 전송 장치 및 비접촉 전력 전송 장치에 있어서의 전력 전송 방법
EP2413531A1 (en) * 2009-03-25 2012-02-01 Panasonic Corporation Interface circuit
JP2011041121A (ja) * 2009-08-17 2011-02-24 Renesas Electronics Corp 送受信装置およびその動作方法
US8452908B2 (en) 2009-12-29 2013-05-28 Juniper Networks, Inc. Low latency serial memory interface
KR101124251B1 (ko) 2010-07-07 2012-03-27 주식회사 하이닉스반도체 적층된 칩들에 아이디를 부여하는 시스템, 반도체 장치 및 그 방법
JP2012049863A (ja) * 2010-08-27 2012-03-08 Renesas Electronics Corp 半導体装置
KR101157032B1 (ko) 2010-11-17 2012-06-21 에스케이하이닉스 주식회사 반도체 장치
US9025713B2 (en) * 2013-10-04 2015-05-05 M31 Technology Corporation Method for portable device processing data based on clock extracted from data from host

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190084755A (ko) * 2018-01-09 2019-07-17 삼성전자주식회사 모바일 장치 및 그것의 인터페이싱 방법

Also Published As

Publication number Publication date
EP3170090A1 (en) 2017-05-24
WO2016011341A1 (en) 2016-01-21
TW201606511A (zh) 2016-02-16
CN106796563B (zh) 2020-01-14
JP2017528946A (ja) 2017-09-28
CN106796563A (zh) 2017-05-31
EP3170090B1 (en) 2019-12-25
US9792247B2 (en) 2017-10-17
US20160019183A1 (en) 2016-01-21

Similar Documents

Publication Publication Date Title
US9792247B2 (en) Systems and methods for chip to chip communication
EP3158698B1 (en) Systems and methods for providing power savings and interference mitigation on physical transmission media
US20150220472A1 (en) Increasing throughput on multi-wire and multi-lane interfaces
US9825755B2 (en) Configurable clock tree
US10484164B2 (en) Clock and data recovery for pulse based multi-wire link
CN106998215A (zh) 数据接收装置
US10963035B2 (en) Low power PCIe
US9130817B2 (en) Low power transmitter for generating pulse modulated signals
KR20170137091A (ko) 출력 인에이블 신호를 생성하는 제어 회로 및 관련 시스템 및 방법
US8848850B2 (en) Pulse width modulation receiver circuitry
US10310585B2 (en) Replacement physical layer (PHY) for low-speed peripheral component interconnect (PCI) express (PCIe) systems
WO2023159415A1 (en) Adaptive low-power signaling to enable link signal error recovery without increased link clock rates
KR20170134434A (ko) 멀티-포트 물리 계층 (phy) 에 대한 위상 록킹 루프 (pll) 의 공유된 제어
TW202310651A (zh) 用以提高無線網路訊號品質的顯示通訊介面驅動強度的執行時調節和順序校準

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20170116

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination