TW201546957A - 半導體積體電路與其製作方法 - Google Patents

半導體積體電路與其製作方法 Download PDF

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TW201546957A
TW201546957A TW103146498A TW103146498A TW201546957A TW 201546957 A TW201546957 A TW 201546957A TW 103146498 A TW103146498 A TW 103146498A TW 103146498 A TW103146498 A TW 103146498A TW 201546957 A TW201546957 A TW 201546957A
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layer
conductive structure
forming
integrated circuit
semiconductor integrated
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TWI556352B (zh
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高祥倫
林天祿
王永智
莊正吉
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台灣積體電路製造股份有限公司
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Abstract

本發明揭露半導體積體電路(IC)的製作方法。提供導電結構於基板上。沉積第一介電層於導電結構與基板上。形成一形成通孔溝槽(VFT)於第一介電層中，以露出該導電結構與導電結構周圍的基板。將犧牲層填入VFT中。形成通孔開口於犧牲層中，以露出導電結構。形成金屬插塞於通孔開口中，以連接至導電結構。移除犧牲層以形成圍繞空隙，其包圍金屬插塞與導電結構。沉積第二介電層於基板上以密封部份的圍繞空隙，並形成密閉氣隙圍繞金屬插塞與導電結構。

Description

半導體積體電路的製造方法
半導體積體電路(IC)產業已經歷快速成長一段時日。IC材料與設計的技術進步，使每一代的IC比前一代的IC更小且其電路更複雜。新一代的IC具有較大的功能密度(比如固定晶片面積中的內連線裝置數目)，與較小的尺寸(比如製程形成的最小構件或連線)。
製程尺寸縮小往往有利於增加製程效率並降低相關成本。製程尺寸縮小會增加製程複雜度，但製程尺寸縮小的優點顯而易見，因此需要更小的IC製程。技術領域之一為電晶體與其他裝置之間的打線或內連線。雖然現有製作IC裝置的方法通常適用於特定目的，但無法完全適用於所有領域。舉例來說，改良介電層與金屬內連線之製程與結構的發展正面臨挑戰。
本發明之下列詳細內容將搭配圖式說明以利了解。值得注意的是，在產業實際應用時，圖式中的多種結構並未依比例繪示。事實上，多種結構的尺寸可隨意增加或縮小，以清楚說明本發明。
第1圖係某些實施例中，製作半導體積體電路(IC)之方法的 流程圖。
第2至12圖係依據第1圖之方法製作之半導體積體電路(IC)於製程階段中的剖視圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
第1圖係本發明實施例中，製作一或多個半導體裝置之方法100的流程圖。方法100將詳述如下，並以第2至12圖中的IC裝置200舉例說明。可以理解的是其他實施例在上述方法之前、之中、及之後可進行額外步驟，且可採用其他步驟替換上述方法之某些步驟，甚至省略上述方法之某些步驟。
如第1與2圖所示，方法100開始於步驟102，其提供基板210。基板210包含矽。在其他實施例中，基板210可包 含其他半導體元素如鍺。基板210亦可包含半導體化合物如碳化矽、砷化鎵、砷化銦、或磷化銦。基板210亦包含半導體合金如矽鍺、碳化矽鍺、磷化鎵砷、或磷化鎵銦。在一實施例中，基板210包含磊晶層。舉例來說，基板210可包含磊晶層於基體半導體上。此外，基板210可包含絕緣層上矽(SOI)結構。舉例來說，基板210可包含埋置氧化物(BOX)層，其形成方法可為佈植氧隔離(SIMOX)或其他合適技術(比如晶圓接合與研磨)。
基板210亦可包含多種p型掺雜區及/或n型掺雜 區，其形成方法可為離子佈植及/或擴散。這些掺雜區包含n型井、p型井、輕掺雜區(LDD)、重掺雜源極與汲極(S/D)、與多種通道掺雜輪廓，設置以形成多種積體電路(IC)裝置如互補式金氧半場效電晶體(CMOSFET)、影像感測器、及/或發光二極體(LED)。基板210亦可包括其他功能結構如電阻或電容形成其上或其中。
基板210亦可包含多個隔離結構。隔離結構分隔基 板210中的多種裝置區。隔離結構包含不同製程技術形成的不同結構。舉例來說，隔離結構可包含淺溝槽隔離(STI)結構。 STI的形成方法可包含蝕刻溝槽於基板210中，再將絕緣材料如氧化矽、氮化矽、或氮氧化矽填入溝槽。填入溝槽的絕緣物可為多層結構，比如熱氧化物襯墊層與後續填入的氮化矽。接著可進行化學機械研磨(CMP)以回研磨多餘的絕緣材料，並平坦化隔離結構的上表面。
基板210亦可包含介電層與電極層形成的閘極堆 疊。介電層可包含界面層(IL)與高介電常數(HK)介電層，其沉 積方法可為合適技術如化學氣相沉積(CVD)、原子層沉積(ALD)、物理氣相沉積(PVD)、熱氧化法、上述之組合、或其他合適技術。電極層可包含單層或多層，比如金屬層、襯墊層、濕潤層、與黏著層，其形成方法可為ALD、PVD、CVD、或其他合適製程。
基板210亦包含第一介電層212。第一介電層212包 含介電材料如氧化矽或氮化矽。第一介電層212之介電常數(k)小於熱氧化矽(因此又稱作低介電常數介電材料層)，及/或具有其他合適的介電性質。第一介電層212的形成製程可為化學氣相沉積(CVD)或其他合適技術。
基板210亦包含多個導電結構214。導電結構214可 包含掺雜區如源極與汲極(S/D)、閘極、及/或部份內連線結構(如接點、金屬通孔、或金屬線路)。在一實施例中，導電結構214包含電極、電容、電阻、或部份電阻。導電結構214之形成方法可為一或多道製程如微影、蝕刻、與沉積。兩個相鄰的導電結構214之間具有第一間距s1。
在一實施例中，沿著導電結構214之側壁形成阻障 216。阻障216可包含氮化鈦(TiN)、氮化鉭(TaN)、氮化鎢(WN)、氮化鈦矽(TiSiN)、氮化鉭矽(TaSiN)、或其他合適材料。
如第1與3圖所示，方法100之步驟104沉積第二介 電層320於基板上，且第二介電層320位於導電結構214上。在一實施例中，先形成蓋層310覆蓋導電結構214之上表面，之後再沉積第二介電層320。蓋層310可包含鉭(Ta)、鈦(Ti)、錳(Mn)、鈷(Co)、釕(Ru)、TiN、TaN、WN、TiSiN、氧化錳(MnO)、 氮化鋁、氧化鋁、或其他合適材料。蓋層310之形成製程可為沉積、光微影、與蝕刻。
第二介電層320完全填入導電結構214之間的空 間，且延伸於導電結構214之上表面上的第二介電層320具有預定的厚度t。上述預定的厚度t係設計以定義後續步驟所形成的通孔開口其高度，請見後續說明。第二介電層320可包含介電材料層如氧化矽、氮化矽、介電常數低於熱氧化矽的介電材料層(又稱作低介電常數介電層)、或其他合適介電材料層。第二介電層320的形成製程可包含CVD、旋轉塗佈法、或其他合適技術。第二介電層320可為順應性或平坦的結構，其形成方法可為本技術領域已知的技術。在此實施例中，第二介電層320為化學機械研磨形成的平坦結構。
如第1與4圖所示，方法100之步驟106移除部份的 第二介電層320以形成VFT(形成通孔溝槽)330。VFT 330露出部份導電結構214A，亦露出部份導電結構214A周圍之部份第一介電層212。在某些實施例中，亦可露出導電結構214/214A之某些側壁或所有側壁。VFT 330之形成方法，可為經由圖案化光阻層蝕刻第二介電層320。一般而言，圖案化製程可包含塗佈光阻(如旋轉塗佈)、曝光、顯影光阻、其他合適製程、或上述之組合。接著經由圖案化光阻層蝕刻第二介電層320以形成VFT 330。第二介電層320可由多種方法蝕刻，包含乾蝕刻、濕蝕刻、或上述之組合。
如第1與5圖所示，方法100之步驟108將犧牲層410 填入VFT 330中。犧牲層410可包含氧化鈦(TiO)，其沉積方法 可為ALD或CVD。在其他實施例中，犧牲層410可包含旋塗玻璃(SOG)、氧化矽、或其他介電材料，其沉積方法可為任何合適方法如旋轉塗佈、ALD、CVD、或臭氧氧化法。在一實施例中，先沉積蝕刻停止層405於VFT 330上並包覆導電結構214A，之後再沉積犧牲層410。蝕刻停止層405可包含氮化矽、氧化矽、碳化矽、碳氮化矽、或其他合適材料。蝕刻停止層405之材料選擇不同於犧牲層410，以在後續蝕刻中具有蝕刻選擇性。後續蝕刻將說明於下述內容。蝕刻停止層405之沉積法可可為任何合適技術，比如CVD、PVD、或ALD。在一實施例中，凹陷製程可用以移除多餘的犧牲層410。
如第1與6圖所示，方法100之步驟110形成通孔開 口420於VFT 330中。通孔開口420對準個別的導電結構214A，並露出導電結構214A的上表面。通孔開口420之形成方法可為經由圖案化遮罩層，蝕刻犧牲層410與蝕刻停止層405。藉由犧牲層410與蝕刻停止層405的保護，形成通孔開口420的製程可完整保留與導電結構214A相鄰之導電結構214，進而降低通孔引發的金屬橋接(VIMB)問題。
如前述之步驟104，厚度t的範圍取決於通孔開口 420的高度。在一實施例中，通孔開口420之較低部份與較高部份的輪廓不同：較低部份具有垂直輪廓，而較高部份具有錐形輪廓(頂部的開口較寬)。通孔開口420的兩個部份之形成方法，可為兩個不同蝕刻條件(比如氣體或化學品)的蝕刻步驟。藉由控制通孔開口420之較寬開口的寬度w，可讓通孔開口420之頂部邊緣與VFT 330之邊緣具有第二間距s2。在一實施例中，第 二間距s2實質上小於第一間距s1，使後續製程形成的圍繞空隙具有窄頸入口，如下述內容所說明。VFT 330之外的犧牲層410與蝕刻停止層405，可由蝕刻通孔開口的製程移除，或由獨立的蝕刻製程移除。
如第1與7圖所示，方法100之步驟112沉積第三介 電層510於第二介電層320上並填入通孔開口420中。在許多實例中，第三介電層510可與前述第3圖中的第二介電層320類似。在一實施例中，第三介電層510與第二介電層320不同，以達後續蝕刻中的蝕刻選擇性。
如第1與8圖所示，方法100之步驟114形成介電溝槽520於第三介電層510中，並自通孔開口420移除第三介電層510。某些介電溝槽對準個別的通孔開口420，並標示為介電溝槽520A。在許多實施例中，介電溝槽520的形成方法與前述第4圖中的VFT 420之形成方法類似。第三介電層510的移除方法可為選擇性乾蝕刻、選擇性濕蝕刻、或上述之組合。上述蝕刻可選擇性地移除第三介電層，但實質上不蝕刻第二介電層320。在介電溝槽520A中，自通孔開口420向下移除第三介電層510。因此介電溝槽520A連接至通孔開口420。此蝕刻製程亦移除介電溝槽520A中的蝕刻停止層410。
如第1與9圖所示，方法100之步驟116形成金屬插塞610於介電溝槽520與520A及通孔開口420中。形成於介電溝槽520A與通孔開口420中的金屬插塞610，可形成完整的接點向下延伸至導電結構214A。為簡化說明，位於通孔開口420中的金屬插塞將標示為金屬插塞610A。金屬插塞610A與通孔開口 420一樣具有錐形輪廓，其第二間距s2亦小於第一間距s1。
在一實施例中，先形成阻障層605於介電溝槽520 及通孔開口420中，其形成方法為適當的沉積技術如PVD與CVD。阻障層605可包含導電的金屬，但不會與介電層及後續填入介電溝槽520中的導電材料互相擴散及反應。阻障層605可包含難熔金屬與其氮化物。在多種實例中，阻障層包含TiN、TaN、Co、WN、TiSiN、TaSiN、或上述之組合。阻障層可包含多層膜。
接著將金屬層填入介電溝槽520與520A及通孔開 口420中的阻障層605上。金屬層可包含銅(Cu)、鋁(Al)、鎢(W)、銅合金如銅鎂(CuMn)、銅鋁(CuAl)、或銅矽(CuSi)、或其他合適導電材料。金屬層610之沉積方法可為PVD、CVD、有機金屬化學氣相沉積(MOCVD)、或電鍍。此外可進行CMP以回蝕刻多餘的金屬層與阻障層605，以形成金屬插塞610於介電溝槽520中。
如第1與10圖所示，方法100之步驟118移除第三介 電層510。選擇性移除第三介電層510的方法可為濕蝕刻、乾蝕刻、或上述之組合。上述蝕刻選擇性地移除第三介電層510，但實質上不蝕刻第二介電層320與犧牲層410。
如第1與11圖所示，方法100之步驟120移除犧牲層 410以形成圍繞空隙710，其包圍金屬插塞610A與導電結構214A。選擇性移除犧牲層410的方法可為濕蝕刻、乾蝕刻、或上述之組合。藉由蝕刻停止層405，可改善製程容忍度並舒解蝕刻製程的限制。如前所述，一實施例之第二間距s2實質上小 於第一間距s1，使圍繞空隙710在金屬插塞610A之頂部邊緣與VFT 330之邊緣之間具有窄頸入口720。藉由調整第二間距s2，可調整窄頸入口720之寬度。
如第1與12圖所示，方法100之步驟124沉積第四介 電層810以密封圍繞空隙710，形成之封閉氣隙820完全包圍金屬插塞610A與導電結構214A。第四介電層810可包含氧化矽、氮化矽、介電常數(k)低於熱氧化矽的介電材料層(又稱作低介電常數材料層)、或其他合適的介電材料層。第四介電層810的沉積方法可為CVD、旋轉塗佈、或其他合適技術。藉由選擇合適的沉積製程，第四介電層810並非填入圍繞空隙710中，而是密封圍繞空隙710以形成密閉氣隙820，且密閉氣隙820完全包圍金屬插塞610A與導電結構214A。在一實施例中，第四介電層810之沉積方法為CVD，且CVD之沉積速率需高到在完全填入圍繞空隙710前，即封閉圍繞氣隙710之較高部份。在具有窄頸入口720的一實施例中，第四介電層810在完全填入圍繞空隙710中之前，會先在靠近窄頸入口720處密封圍繞空隙710。
在方法100之前、之中、或之後可進行額外步驟， 且其他實施例之方法100的某些步驟可置換、省略、或調整順序。IC裝置200可進行額外的CMOS或MOS技術製程，以形成多種結構與區域。
基於上述內容，本發明提供製作IC裝置的方法， 其藉由移除與金屬通孔相鄰之犧牲層以形成圍繞空隙，再沉積膜層於圍繞空隙上以密封圍繞空隙的較高部份，以形成密閉氣隙。此方法提供之方法可形成完全包圍導電結構之密閉氣隙。 此方法可改善VIMB與時間相關介電崩潰(TDDB)效能，並降低金屬線路的電容。
本發明提供許多不同實施例製作半導體IC以改良 現有研究。在一實施例中，半導體積體電路的製作方法包括：提供導電結構於基板上；沉積第一介電層於導電結構與基板上；形成一形成通孔溝槽(VFT)於第一介電層中，以露出導電結構及導電結構周圍的基板。上述方法亦包括將犧牲層填入VFT中；形成通孔開口於犧牲層中以露出導電結構；形成金屬插塞於通孔開口中以連接至導電結構；選擇性移除犧牲層以形成圍繞空隙包圍金屬插塞與導電結構；以及沉積第二介電層於基板上，以密封部份的圍繞空隙，並形成密閉氣隙包圍金屬插塞與導電結構。
在另一實施例中，半導體積體電路的製作方法包 括：提供導電結構於基板上；沉積第一介電層於導電結構與基板上；形成形成通孔溝槽(VFT)於第一介電層中，以露出導電結構及導電結構周圍的基板；將犧牲層填入VFT中；形成通孔開口於犧牲層中以露出導電結構；沉積第二介電層於犧牲層上；移除部份第二介電層，以形成介電溝槽向下連接至通孔開口；形成金屬插塞於介電溝槽與通孔開口中；移除第二介電層；選擇性移除犧牲層以形成圍繞空隙包圍金屬插塞與導電結構；以及沉積第三介電層於基板上，以密封部份圍繞空隙，並形成密閉氣隙完全包圍金屬插塞與導電結構。
在又一實施例中，半導體IC包括：基板；導電結 構位於基板上；通孔金屬位於導電結構上。通孔金屬具有錐形 輪廓，且錐形輪廓之頂部寬度大於錐形輪廓其較下部份的寬度。IC亦包括金屬插塞位於通孔金屬之頂部上；以及密閉氣隙圍繞導電結構與通孔金屬；IC亦包括介電層位於密閉氣隙上並分隔金屬插塞。
上述實施例之特徵有利於本技術領域中具有通常 知識者理解本發明。本技術領域中具有通常知識者應理解可採用本申請案作為基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明之精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。

Claims (20)

  1. 一種半導體積體電路的製作方法，包括：提供一導電結構於一基板上；沉積一第一介電層於該導電結構與該基板上；形成一形成通孔溝槽於該第一介電層中，以露出該導電結構及該導電結構周圍的基板；將一犧牲層填入該形成通孔溝槽中；形成一通孔開口於該犧牲層中以露出該導電結構；形成一金屬插塞於該通孔開口中以連接至該導電結構；選擇性移除該犧牲層以形成一圍繞空隙包圍該金屬插塞與該導電結構；以及沉積一第二介電層於該基板上，以密封該圍繞空隙的較上部份，並形成一密閉氣隙包圍該金屬插塞與該導電結構。
  2. 如申請專利範圍第1項所述之半導體積體電路的製作方法，更包括：在沉積該第一介電層前，先形成一蓋層於該導電結構的頂部上。
  3. 如申請專利範圍第1項所述之半導體積體電路的製作方法，其中形成該形成通孔溝槽之步驟包括：形成一圖案化遮罩於該第一介電層上；以及經由該圖案化遮罩蝕刻該第一介電層。
  4. 如申請專利範圍第3項所述之半導體積體電路的製作方法，更包括：在將該犧牲層填入該形成通孔溝槽之前，先沉積一蝕刻停 止層，其中移除該犧牲層之步驟停止於該蝕刻停止層。
  5. 如申請專利範圍第1項所述之半導體積體電路的製作方法，其中形成該通孔開口之步驟包括：形成一圖案化遮罩於該犧牲層上；以及經由該圖案化遮罩蝕刻該犧牲層，其中該通孔開口具有一錐形輪廓且頂部邊緣的開口較寬，其中該頂部邊緣至該形成通孔溝槽之邊緣的距離實質上小於該通孔開口至該形成通孔溝槽之距離。
  6. 如申請專利範圍第5項所述之半導體積體電路的製作方法，其中該金屬插塞的形成方法係將一金屬層填入該通孔開口中，其中該金屬插塞的錐形輪廓與該通孔開口的錐形輪廓相同。
  7. 如申請專利範圍第6項所述之半導體積體電路的製作方法，更包括：在將該金屬層填入該通孔開口中之前，先沉積一阻障層於該通孔開口中。
  8. 如申請專利範圍第5項所述之半導體積體電路的製作方法，其中包圍該金屬插塞之該圍繞空隙具有一窄頸入口，且該窄頸入口位於該通孔開口的頂部邊緣與該形成通孔溝槽的邊緣之間。
  9. 如申請專利範圍第5項所述之半導體積體電路的製作方法，藉由調整該頂部邊緣至該形成通孔溝槽之邊緣的距離，使該圍繞空隙的密封處靠近該窄頸入口。
  10. 如申請專利範圍第1項所述之半導體積體電路的製作方 法，其中該犧牲層之形成方法為原子層沉積氧化鈦層。
  11. 如申請專利範圍第1項所述之半導體積體電路的製作方法，更包括：在形成該通孔開口後，沉積一第三介電層於該犧牲層上並填入該通孔開口中；蝕刻該第三介電層並由該通孔開口移除該第三介電層，以形成一溝槽對準該通孔開口，其中該溝槽連接該通孔開口；將一金屬層填入該溝槽與該通孔開口中；以及移除多餘的該金屬層以形成一金屬結構。
  12. 一種半導體積體電路的製作方法，包括：提供一導電結構於一基板上；沉積一第一介電層於該導電結構與該基板上；形成一形成通孔溝槽於該第一介電層中，以露出該導電結構及該導電結構周圍的基板；將一犧牲層填入該形成通孔溝槽中；形成一通孔開口於該犧牲層中以露出該導電結構；沉積一第二介電層於該犧牲層上；移除部份該第二介電層，以形成一介電溝槽向下連接至該通孔開口；形成一金屬插塞於該介電溝槽與該通孔開口中；移除該第二介電層；選擇性移除該犧牲層以形成一圍繞空隙包圍該金屬插塞與該導電結構；以及沉積一第三介電層於該基板上，以密封部份該圍繞空隙， 並形成一密閉氣隙完全包圍該金屬插塞與該導電結構。
  13. 如申請專利範圍第12項所述之半導體積體電路的製作方法，更包括：在沉積該第一介電層前，先形成一蓋層於該導電結構的頂部上。
  14. 如申請專利範圍第12項所述之半導體積體電路的製作方法，其中形成該通孔開口之步驟包括：形成一圖案化遮罩於該犧牲層上；以及經由該圖案化遮罩蝕刻該犧牲層，其中該通孔開口具有一錐形輪廓且頂部邊緣的開口較寬，其中該頂部邊緣至該形成通孔溝槽之邊緣的距離實質上小於該通孔開口至該形成通孔溝槽之距離。
  15. 如申請專利範圍第14項所述之半導體積體電路的製作方法，其中該金屬插塞之形成方法為將一金屬層填入該通孔開口中，其中該金屬插塞之錐形輪廓與該通孔開口之錐形輪廓相同。
  16. 如申請專利範圍第15項所述之半導體積體電路的製作方法，其中包圍該金屬插塞之該圍繞空隙具有一窄頸入口，且該窄頸入口位於該通孔開口的頂部邊緣與該形成通孔溝槽的邊緣之間。
  17. 如申請專利範圍第16項所述之半導體積體電路的製作方法，藉由調整該頂部邊緣至該形成通孔溝槽之邊緣的距離，使該圍繞空隙的密封處靠近該窄頸入口。
  18. 如申請專利範圍第12項所述之半導體積體電路的製作方 法，其中該犧牲層的形成方法為原子層沉積氧化鈦層。
  19. 如申請專利範圍第12項所述之半導體積體電路的製作方法，更包括在將金屬層填入該通孔開口前，先沉積一阻障層於該通孔開口中。
  20. 一種半導體積體電路，包括：一基板；一導電結構位於該基板上；一通孔金屬位於該導電結構上，其中該通孔金屬具有一錐形輪廓，其中該錐形輪廓之頂部寬度大於該錐形輪廓其較下部份的寬度；一金屬插塞位於該通孔金屬之頂部上；一密閉氣隙圍繞該導電結構與該通孔金屬；以及一介電層位於該密閉氣隙上並分隔該金屬插塞。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109904113A (zh) * 2017-12-11 2019-06-18 格芯公司 在集成电路产品上形成接触结构的方法
CN111696914A (zh) * 2019-03-14 2020-09-22 长鑫存储技术有限公司 互连线结构的制备方法
US10804184B2 (en) 2018-11-30 2020-10-13 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
US11189565B2 (en) 2020-02-19 2021-11-30 Nanya Technology Corporation Semiconductor device with programmable anti-fuse feature and method for fabricating the same
TWI750059B (zh) * 2020-04-14 2021-12-11 南亞科技股份有限公司 具有氣隙結構的半導體元件結構及其製備方法
TWI763823B (zh) * 2017-04-10 2022-05-11 南韓商三星電子股份有限公司 具有異質接點的積體電路

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082770B2 (en) * 2012-10-24 2015-07-14 Taiwan Semiconductor Manufacturing Company Limited Damascene gap structure
US9455178B2 (en) 2014-03-14 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US9583434B2 (en) * 2014-07-18 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Metal line structure and method
US9496169B2 (en) * 2015-02-12 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect structure having an air gap and structure thereof
US9972529B2 (en) * 2015-09-28 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal interconnection
US9793204B2 (en) 2015-11-17 2017-10-17 Taiwan Semiconductor Manufacturing Company Limited Method of manufacturing semiconductor structure comprising plurality of through holes using metal hard mask
US10388564B2 (en) * 2016-01-12 2019-08-20 Micron Technology, Inc. Method for fabricating a memory device having two contacts
US10340181B2 (en) 2016-11-17 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure including air gap
US10319629B1 (en) * 2018-05-08 2019-06-11 International Business Machines Corporation Skip via for metal interconnects
US10665499B2 (en) * 2018-06-28 2020-05-26 Intel Corporation Integrated circuit with airgaps to control capacitance
KR102606784B1 (ko) * 2018-07-13 2023-11-28 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
CN110858578B (zh) * 2018-08-23 2021-07-13 联华电子股份有限公司 管芯封环及其制造方法
US10714382B2 (en) * 2018-10-11 2020-07-14 International Business Machines Corporation Controlling performance and reliability of conductive regions in a metallization network
US11557509B1 (en) * 2018-12-21 2023-01-17 Applied Materials, Inc. Self-alignment etching of interconnect layers
US11018169B2 (en) * 2019-08-19 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Metal-insulator-metal capacitor structure to increase capacitance density
KR20210049604A (ko) 2019-10-25 2021-05-06 삼성전자주식회사 집적회로 소자 및 이의 제조 방법
CN113314457B (zh) * 2020-02-27 2023-04-18 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构
US20230016154A1 (en) * 2021-07-16 2023-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure with interconnect structure having air gap

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037248A (en) * 1997-06-13 2000-03-14 Micron Technology, Inc. Method of fabricating integrated circuit wiring with low RC time delay
US6577011B1 (en) * 1997-07-10 2003-06-10 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US6177329B1 (en) * 1999-04-15 2001-01-23 Kurt Pang Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets
US6413852B1 (en) 2000-08-31 2002-07-02 International Business Machines Corporation Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
US7026235B1 (en) * 2002-02-07 2006-04-11 Cypress Semiconductor Corporation Dual-damascene process and associated floating metal structures
US6917109B2 (en) * 2002-11-15 2005-07-12 United Micorelectronics, Corp. Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device
US6764919B2 (en) * 2002-12-20 2004-07-20 Motorola, Inc. Method for providing a dummy feature and structure thereof
US20050189653A1 (en) 2004-02-26 2005-09-01 Hun-Jan Tao Dual damascene intermediate structure and method of fabricating same
US7285474B2 (en) * 2004-09-16 2007-10-23 International Business Machines Corporation Air-gap insulated interconnections
CN101375388B (zh) 2006-01-18 2011-08-03 Nxp股份有限公司 金属线之间的自对准沟槽的集成
KR100763538B1 (ko) * 2006-08-29 2007-10-05 삼성전자주식회사 마스크 패턴의 형성 방법 및 이를 이용한 미세 패턴의 형성방법
US7871923B2 (en) * 2007-01-26 2011-01-18 Taiwan Semiconductor Maufacturing Company, Ltd. Self-aligned air-gap in interconnect structures
JP2008294211A (ja) * 2007-05-24 2008-12-04 Toshiba Corp 半導体装置及びその製造方法
US20090081862A1 (en) * 2007-09-24 2009-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Air gap structure design for advanced integrated circuit technology
US7868455B2 (en) * 2007-11-01 2011-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Solving via-misalignment issues in interconnect structures having air-gaps
US7884477B2 (en) 2007-12-03 2011-02-08 International Business Machines Corporation Air gap structure having protective metal silicide pads on a metal feature
WO2009127914A1 (en) * 2008-04-17 2009-10-22 Freescale Semiconductor, Inc. Method of sealing an air gap in a layer of a semiconductor structure and semiconductor structure
DE102008026134A1 (de) 2008-05-30 2009-12-17 Advanced Micro Devices, Inc., Sunnyvale Mikrostrukturbauelement mit einer Metallisierungsstruktur mit selbstjustierten Luftspalten zwischen dichtliegenden Metallleitungen
DE102008059650B4 (de) 2008-11-28 2018-06-21 Globalfoundries Inc. Verfahren zur Herstellung einer Mikrostruktur mit einer Metallisierungsstruktur mit selbstjustierten Luftspalten zwischen dichtliegenden Metallleitungen
KR101912947B1 (ko) * 2011-11-09 2018-10-30 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
JP5898991B2 (ja) * 2012-02-10 2016-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US8841711B1 (en) * 2013-03-12 2014-09-23 Globalfoundries Inc. Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
KR102055299B1 (ko) * 2013-04-12 2019-12-16 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
US9455178B2 (en) 2014-03-14 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI763823B (zh) * 2017-04-10 2022-05-11 南韓商三星電子股份有限公司 具有異質接點的積體電路
US11437315B2 (en) 2017-04-10 2022-09-06 Samsung Electronics Co., Ltd. Integrated circuit having heterogeneous gate contacts over active regions
CN109904113A (zh) * 2017-12-11 2019-06-18 格芯公司 在集成电路产品上形成接触结构的方法
CN109904113B (zh) * 2017-12-11 2023-08-22 格芯(美国)集成电路科技有限公司 在集成电路产品上形成接触结构的方法
US10804184B2 (en) 2018-11-30 2020-10-13 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
TWI741270B (zh) * 2018-11-30 2021-10-01 南亞科技股份有限公司 半導體元件的製造方法
CN111696914A (zh) * 2019-03-14 2020-09-22 长鑫存储技术有限公司 互连线结构的制备方法
CN111696914B (zh) * 2019-03-14 2022-12-23 长鑫存储技术有限公司 互连线结构的制备方法
US11189565B2 (en) 2020-02-19 2021-11-30 Nanya Technology Corporation Semiconductor device with programmable anti-fuse feature and method for fabricating the same
US11735520B2 (en) 2020-02-19 2023-08-22 Nanya Technology Corporation Method for fabricating semiconductor device with programmable anti-fuse feature
TWI750059B (zh) * 2020-04-14 2021-12-11 南亞科技股份有限公司 具有氣隙結構的半導體元件結構及其製備方法

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