TW201541599A - 一種用以電性連接多個積體電路晶粒的組裝結構及方法 - Google Patents

一種用以電性連接多個積體電路晶粒的組裝結構及方法 Download PDF

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TW201541599A
TW201541599A TW104111844A TW104111844A TW201541599A TW 201541599 A TW201541599 A TW 201541599A TW 104111844 A TW104111844 A TW 104111844A TW 104111844 A TW104111844 A TW 104111844A TW 201541599 A TW201541599 A TW 201541599A
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Taiwan
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integrated circuit
circuit die
substrate
pad
diode
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TW104111844A
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English (en)
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TWI546926B (zh
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Tsung-Chuan Whang
Yi-Chieh Wang
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Global Unichip Corp
Taiwan Semiconductor Mfg
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Publication of TW201541599A publication Critical patent/TW201541599A/zh
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Abstract

本發明揭露了一種利用重佈層（RDL）連接多個積體電路晶粒的有效方法。利用天線二極體作為接地途徑，在封裝多個積體電路晶粒成一個系統封裝（System-In-Package，SIP）晶片之前，去除重佈層（RDL）上的不粘接接墊 (non-sticking pad) 以確保導線連接的完整性，減少因非粘結接墊之功能性測試所造成的不必要良率損失。另一方面，透過在積體電路晶粒中設置跨於兩個不同電源域的天線二極體來保護靜電放電（ESD），將一個二極體設置於積體電路晶粒中以保護另一個積體電路晶粒端子的ESD。

Description

一種用以電性連接多個積體電路晶粒的組裝結構及方法
本發明主要是關於一種系統封裝晶片，特別是封裝該系統封裝晶片的組裝結構。
隨著技術不斷的改進，邏輯閘數密度也日益增加，外觀也愈來愈小。於是各種類比晶片、數位晶片和記憶晶片的封裝也就益加重要。系統封裝是解決這個複雜問題的其中一種方法。然而將許多晶片封裝在一包並不是件普通的事，如果晶片設計不佳，就會造成接墊(PAD)不粘接的問題， 封裝廠就會需要用鍵結線來解決問題。
通常，封裝基底是用來電性連接各積體電路矽晶晶粒，並形成多個導線以連接積體電路矽晶晶粒的多個接墊和封裝基底的多個接腳。接墊不粘接（Non-Stick On Pad， NSOP）測試可應用於晶粒的各接墊以偵測不粘接的失敗。NSOP 測試是從接合完整性測試系統（Bond Integrity Test System ， BITS）之一個交直流(DC/AC) 完整性測試板通過一個連接晶粒的各接墊的BITS電纜來發送測試信號，以偵測從晶粒的各接墊至接地是否存在一電流迴路。如果其間有任何受阻電流迴路就無法形成，而NSOP測試就會失敗。
如第1A圖所示，在一封裝基底上放置一晶粒，在封裝基底下設置一接地的熱組件，以便能透過接合完整性測試系統（BITS）來進行鍵結線測試。該測試系統會經由探針送出測試信號到接墊，該探針連接晶粒上的接墊以便測試接墊的持續性。當測試信號帶有直流電壓，測試信號會通過該晶粒和基底接地。如此一來，就不需要另外一接地路徑以連接接墊到接地，因為連接接墊到接地的一導電路徑可通過晶粒和基底來形成。也就是說，接墊到接地間必須有一導電路徑，以確保接墊的連續性；否則接墊將被稱為不粘接接墊(Non-Sticking Pad)或浮動接墊(Floating Pad)，接墊的連續性測試將會失敗。
傳統方法之另一面向，在於皆是使用一封裝基底來連接多個積體電路晶粒的接墊和外部引腳，然而這會增加成本。
因此，我們需要一種更有效率的方法來連接系統封裝晶片之多個積體電路晶粒。
本發明提供一種使用重佈層（redistribution layer， RDL）以電性連接多個積體電路晶粒的方法。
在一個實施例中，天線二極體(antenna diode)被用來作為接地路徑，以除去重佈層（RDL）上之不粘接或浮動接墊，以使得在封裝多個積體電路晶粒成一系統級封裝晶片之前， 能確保導線連接的完整性，從而減少功能性測試時不粘接或浮動接墊所造成的不必要良率損失。
另一方面，本發明藉由經過兩個不同電源域的該二極體天線來提供靜電放電保護，藉由設置一二極體在一積體電路晶粒中，以提供另一積體電路晶粒之一端子的靜電放電保護。
在一個實施例中，揭露一種用以電性連接多個積體電路晶粒的組裝結構，包括： 一第一積體電路晶粒和第二積體電路晶粒；以及一設置在第一積體電路晶粒上的重佈層，該重佈層包含一第一接墊，用以電性連接該第一個積體電路晶粒和該第二積體電路晶粒，其中該第一積體電路晶粒包含一第一基底；其中，該第一積體電路晶粒包含一第一導電元件，用以形成位於該第一積體電路晶粒上的該第一接墊和該第一基底之間的導電通路， 其中該第一接墊在第一導電元件不存在於該第一積體電路晶粒時，為一浮動接墊。
在一個實施例中，該第一基底是P 型，該二極體的設置在第一基底中形成一N 型區域，以使在該P 型基底與該N 型區域間形成一P-N 結(P-N Junction)，其中該N 型區域電性連接該第一接墊。
在一個實施例中，該第二積體電路晶粒透過隔離層設置於第一積體電路晶粒上，其中該至少一接墊經鍵結線電性連接第二積體電路晶粒。
在一個實施例中，該第一積體電路晶粒和該第二積體電路晶粒下方沒有基底可以相連接。
在一個實施例中，該第一積體電路晶粒和該第二積體電路晶粒被封裝成一系統封裝晶片。
在一個實施例中，揭露一種用以組裝多個積體電路晶粒以成為一系統封裝晶片的方法，該方法包括： 提供多個積體電路晶粒；設置至少一重佈層於該多個積體電路晶粒中至少一積體電路晶粒上，用以電性連接該各個積體電路晶粒，而無需使用該多個積體電路晶粒底下的一基底；建立該多個積體電路晶粒之間的導線連接，及驗證導線連接的數量；以及 封裝多個積體電路晶粒及已驗證的連接線成為一系統封裝晶片。
在一個實施例中，該方法還包含設置一二極體於該第一積體電路晶粒中，用以移除該重佈層上的一浮動接墊，其中，該二極體的一負極端子電性連接該第一接墊，一正極端子電性連接該第一積體電路晶粒的該第一基底。
在一個實施例中，該第一基底是P 型，而該二極體的形成是藉由在該P 型第一基底中形成一N 型區域，以形成在該P 型基底和該N 型區域間形成一P-N 結(P-N Junction)，其中該N 型區域電性連接該至少一接墊之一對應的接墊。
在一個實施例中，一第二積體電路晶粒經由一隔離層設置於該第一積體電路上，其中，該至少一接墊以鍵結線電性連接該第二積體電路晶粒。
在一個實施例中，揭露一種具有多個積體電路晶粒的系統封裝晶片，包括：一第一積體電路晶粒和一第二積體電路晶粒，其中，該第一積體電路晶粒包含一第一端子，電性連接該第二積體電路晶粒，該第一積體電路晶粒包含一第一基底；其中，該第一積體電路晶粒包含一二極體，該二極體的一正極端子電性連接該第一積體電路晶粒的該第一端子，該二極體的一負極端子電性連接該第一積體電路晶粒的該第一基底，其中，該第二積體電路晶粒的該第二端子利用該第一積體電路晶粒的該二極體作為靜電放電（ESD）的保護。
在一個實施例中，該第一基底是P 型，而該二極體的形成是藉由在該P 型第一基底中形成一N 型區域，以形成在該P 型基底和該N 型區域間形成一P-N 結(P-N Junction)，其中該N 型區域電性連接該至 該第一積體電路晶粒的該第一端子。
在一個實施例中，該第一積體電路晶粒和該第二積體電路晶粒位於兩個不同的電源域。
本發明的詳細描述說明如下。所描述的較佳實施例是作為說明和描述的用途，並非用來限定本發明之範圍。
圖2係根據本發明的一個實施例之一由多個積體電路晶粒構成的組裝結構之示意圖，其中，藉由使用一重佈層當作一橋梁來連接導線，而該多個晶粒下方並無基底可用來連接導線。如圖2所示，一第一積體電路晶粒200堆疊在一第二積體電路晶粒220上，其中，該第一積體電路晶粒200主要是包含類比電路，而該第二積體電路晶粒主要是包含數位電路，其中一隔離層210設置在該第一積體電路晶粒200與該第二積體電路晶粒220之間，以使該類比電路完全隔離於該數位電路以達到高效能。一重佈層209設置在該第一積體電路晶粒200上，以連接該第二積體電路晶粒220的一端子與外部接腳，其中一第一接墊205以及一第二接墊206用來電性連接該第一積體電路晶粒200的一第一端子201與一第一導線203；一第三接墊207以及一第四接墊208用來電性連接該第一積體電路晶粒200的一第二端子202與一第二導線204。然而，該重佈層209上之接墊205 206 207 208是浮動的，因為，當該第一積體電路晶粒200透過該隔離層210被完全隔離時，該重佈層209上的接墊沒有電性連接至該第二積體電路晶粒220中之任何一個電路，而這可能是在已完成鍵結線及組裝後才被發現。在佈置鍵結線及組裝的過程中，因為該等接墊 205、 206、207、 208並沒有電性連接至該第一積體電路晶粒200中的電路，因而導致在測試時無法偵測到該些浮動接墊 205、 206、207、 208。在此例中，由於如上述提及的該類比電路需要與該數位電路完全隔離，所以並沒有使用另一基底來電性連接該第一積體電路晶粒200與該第二積體電路晶粒220。因此，組裝工廠在組裝該第一積體電路晶粒200與該第二積體電路晶粒220後，無法確保該系統封裝晶片的品質，而只有在功能性測試階段時，才能來偵測組裝完成的系統封裝晶片是否有錯誤。如此一來，將造成成本增加且可能影響系統封裝晶片的良率，因為功能性測試階段的失敗也可能與鍵結線的錯誤混淆，而修復系統封裝晶片的功能錯誤遠比修復鍵結線的錯誤來的困難且昂貴。
為了解決浮動接墊的問題，在本發明的一實施例中，一天線二極體設置在該浮動接墊下方的該第二積體電路晶粒220中以產生一可被感測的接地路徑，其中該天線二極體在該第二積體電路晶粒中並沒有電性連接至其他電路，而且該天線二極體對於該第二積體電路晶粒220的原始電路設計是非必要的。藉由在該第二積體電路晶粒220 設置一用以電性連接至該第一積體電路晶粒200的端子之一天線二極體來解決組裝時無黏著接墊的問題是一個簡單方便且低成本的解決方法， 同時可消除在功能性測試時的低良率問題。
在一實施例中，如圖3所示，在該第一基底中之第二接墊206的下方， 藉由增加一N+ 擴散區域231以形成一位於該浮動接墊206與該第二積體電路晶粒220的基底232間之P/N二極體231，因而產生一接地260路徑，且不必擔心有漏電流的問題。藉由這樣做，解決了連接多個晶粒時無黏著接墊的問題。在完成以及檢驗鍵結線後，該第一積體電路晶粒200以及該第二積體電路晶粒220可被封裝到一晶片裡。在一實施例中，該重佈層209上的浮動接墊205、206 透過在一封裝體 250上的一接墊203電性連接至一球形接腳251以及該重佈層209上的浮動接墊207、208透過在該封裝體 250上的一接墊204電性連接至一球形接腳252。
請注意，其他傳導元件也可能被用來取代該二極體231來解決浮動接墊的問題，例如一具有高阻抗的電阻或一汲極端子連接到該浮動接墊的NMOS電晶體，且該NMOS電晶體的源極以及閘極連接到該第二積體電路晶粒220的基底232，只要流過該傳導元件的電流夠小且不影響該系統封裝晶片的正常運作。
在一實施例中，該二極體230產生一靜電放電路徑來保護該第一積體電路晶粒。靜電放電模式包含元件充電模式(charged-device model)。
在一實施例中，該第二積體電路晶粒220主要是基於數位電路設計，例如一基頻設計，然而該第一積體電路晶粒200主要是基於類比電路設計，例如ADC/DAC/PLL設計。
圖4繪示一系統封裝晶片的組裝結構，在本發明的一實施例中，在該第一基底中之浮動接墊206的下方， 藉由增加一N+ 擴散區域231以形成一位於該浮動接墊206與該第二積體電路晶粒220的基底232間之P/N二極體231。另外，在該第一基底中之浮動接墊208的下方， 藉由增加一N+ 擴散區域241以形成一位於該浮動接墊208與該第二積體電路晶粒220的基底232間之P/N二極體241。其中該浮動接墊206透過在一封裝體 250上的一接墊203電性連接至一球形接腳251以及該浮動接墊208透過該封裝體 250上的一接墊204電性連接至一球形接腳252。請注意，有許多方法可以置放該些積體電路晶粒，例如，一第三積體電路晶粒(圖示中未表示)，具有一基底用以連接至接地點，該基底位於該第一積體電路晶粒的一邊，且一重佈層設置在該第三積體電路晶粒上以電性連接該第二積體電路晶粒的其他端子。也就是說，當一浮動接墊設置在一積體電路晶粒上之一重佈層上時，該積體電路晶粒可提供該浮動接墊一傳導路徑以解決在組裝階段時浮動接墊的問題，以使功能性測試能專注於該系統封裝晶片的功能，而不必擔心浮動接墊的問題。
在一實施例中，揭露一種具有多個積體電路晶粒的系統封裝晶片，其中該系統封裝晶片包含一第一積體電路晶粒與一第二積體電路晶粒，其中該第一積體電路晶粒包含一第一端子，電性連接至該第二積體電路晶粒的一第二端子，其中該第一積體電路晶粒具有一第一基底，其中該第一積體電路晶粒包含一二極體，其中該二極體的一正極端子電性連接至該第一端子以及該二極體的一負極端子電性連接至該第一積體電路晶粒的該第一基底，其中該第二積體電路的該第二端子使用該第一積體電路晶粒的該二極體用以作為靜電放電保護。
請再一次參閱圖4，藉由N+ 擴散區域231以及N+ 擴散區域241所形成之該些二極體是被用來提供該第一積體電路晶粒200的端子201與端子202之一靜電放電路徑。靜電放電模式包含元件充電模式(charged-device model) 。在本實施例中，接墊206與接墊208不必然是浮動接墊，同時，該第一積體電路晶粒200與該第二積體電路晶粒220可位於不同的電源域中。
在一實施例中，該第一基底是P 型且該二極體是藉由在該P 型基底中產生一N 型區域以形成在該P 型基底與該N 型區域間之一P-N 結 (P-N Junction)，其中該N 型區域電性連接至該第一積體電路晶粒的該第一端子。在一實施例中，該第二積體電路晶粒經由一隔離層以設置在該第一積體電路晶粒上，其中該重佈層包含一第一接墊，用以電性連接該第一積體電路晶粒的該第一端子以及該第二積體電路晶粒的該第二端子。
根據本發明的一實施例，圖5繪示一組裝多個積體電路晶粒為一系統封裝晶片的方法之流程圖，該方法包含：提供一複數個積體電路晶粒 (步驟501)；設置至少一重佈層於多個積體電路晶粒中至少一積體電路晶粒上用以電性連接各個積體電路晶粒，而無需使用多個積體電路晶粒底下的一基底 (步驟502)；建立多個積體電路晶粒之間的多個導線連接以及驗證該多個導線連接 (步驟503)；在驗證該多個導線連接後，封裝該複數個積體電路晶粒為一系統封裝晶片晶片(步驟504)。
在一實施例中，該至少一重佈層包含設置在一第一積體電路晶粒上之一第一重佈層，用以電性連接至一第二積體電路晶粒，其中步驟502更包含分別在該至少一接墊的每一接墊之下設置一在該第一積體電路晶粒中之二極體，其中該二極體的一負極端子電性連接至在該第一重佈層上的該至少一接墊的一對應接墊，用以連接該第二積體電路晶粒，以及該二極體的一正極端子電性連接至該第一積體電路晶粒的該第一基底，用以電性連接至一接地點。
在一實施中，該第一基底是P 型且形成該二極體是藉由在該第一基底中位於該至少一接墊的該對應接墊以及該重佈層的下方產生一N 型區域以形成位於該P 型基底與該N 型區域間之一P-N 結(P-N Junction)，其中該N 型區域電性連接至該至少一接墊的該對應接墊。
藉由參閱圖2到圖4，該方法的其他描述能被輕易的了解，因此不再描述。
本發明之最佳實施例詳述如上。然而此實施例非用以限制本發明，顯而易見地，在不脫離本發明之精神與範圍內，任何熟習技藝者得以完成許多更動及潤飾。本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。
200‧‧‧第一積體電路晶粒
201‧‧‧第一端子
202‧‧‧第二端子
203‧‧‧第一導線
204‧‧‧第二導線
205、206、207、208‧‧‧接墊
209‧‧‧重佈層
210‧‧‧隔離層
220‧‧‧第二積體電路晶粒
230‧‧‧二極體
231、241‧‧‧N+擴散區域
232‧‧‧基底
250‧‧‧封裝體
251、252‧‧‧球形接腳
260‧‧‧接地
第1圖係由多個積體電路晶粒構成的一傳統組裝結構之示意圖  。 第2圖係根據本發明的一個實施例之一由多個積體電路晶粒構成的組裝結構之示意圖。 第3圖係根據本發明的一個實施例之設置於一積體電路晶粒中用以移除浮動接墊的多個天線二極體之示意圖。 第4圖係根據本發明的一個實施例之一由多個積體電路晶粒構成且無浮動接墊的組裝結構之示意圖。 第5圖係根據本發明的一個實施例之一組裝多個積體電路晶粒成一系統封裝晶片的方法之流程圖。
200‧‧‧第一積體電路晶粒
201‧‧‧第一端子
202‧‧‧第二端子
203‧‧‧第一導線
204‧‧‧第二導線
205、206、207、208‧‧‧接墊(PAD)
209‧‧‧重佈層
210‧‧‧隔離層
220‧‧‧第二積體電路晶粒
250‧‧‧封裝體
251、252‧‧‧球形接腳

Claims (20)

  1. 一種用以電性連接多個積體電路晶粒的組裝結構，包括：                   一第一積體電路晶粒和一第二積體電路晶粒；以及                   一設置在第二積體電路晶粒上的重佈層，該重佈層包含一第一接墊，用以電性連接該第一個積體電路晶粒和該第二積體電路晶粒，其中該第二積體電路晶粒包含一第一基底；                   其中，該第二積體電路晶粒包含一第一導電元件，用以形成位於該第二積體電路晶粒上的該第一接墊和該第一基底之間的一導電通路， 其中在該第一導電元件不存在於該第二積體電路晶粒時，該第一接墊為一浮動接墊。
  2. 根據請求項1所述的組裝結構，其中，該第一導電元件為一二極體，該二極體的負極端子電性連接該第一接墊，該二極體的正極端子電性連接該第一基底。
  3. 根據請求項2所述的組裝結構，其中，該第一基底是P 型，該二極體的形成是藉由在該第一基底中形成一N 型區域，以在該P 型基底與該N 型區域間形成一P-N 結(P-N Junction)，其中該N 型區域電性連接該第一接墊。
  4. 根據請求項1所述的組裝結構，其中，該第一導電元件具有一高阻抗電阻，該高阻抗電阻的一端電性連接該第一接墊，該高阻抗電阻的另一端電性連接該第一基底。
  5. 根據請求項1所述的組裝結構，其中，該第一導電元件是一NMOS電晶體，該NMOS電晶體的一汲極端子電性連接該第一接墊，該NMOS電晶體的一源極端子和一閘極端子電性連接該第一基底。
  6. 根據請求項1所述的組裝結構，其中，該第二積體電路晶粒之下無用以電性連接該第一積體電路晶粒和該第二積體電路晶粒之基底。
  7. 根據請求項1所述的組裝結構，其中，該第一積體電路晶粒經由一隔離層被設置在該第二積體電路晶粒上，其中，該第一接墊是以鍵結線電性連接至該第一積體電路晶粒的一第一端子。
  8. 根據請求項7所述的組裝結構，其中，該第一積體電路晶粒主要是包含數位電路，該第二積體電路晶粒主要是包含類比電路。
  9. 根據請求項7所述的組裝結構，其中，該第一接墊電性連接該第一積體電路晶粒的該第一端子及一外部引腳。
  10. 根據請求項7所述的組裝結構，其中，該第一積體電路晶粒的該第一端子，利用該第二積體電路的二極體以作為靜電放電（ESD）的保護。
  11. 一系統封裝晶片，包含如請求項1所述的一組裝結構。
  12. 一種用以組裝多個積體電路晶粒以成為一系統封裝晶片的方法，該方法包括：                  提供多個積體電路晶粒；                  設置至少一重佈層於該多個積體電路晶粒中至少一積體電路晶粒上，用以電性連接該各個積體電路晶粒，而無需使用該多個積體電路晶粒底下的一基底；                  建立該多個積體電路晶粒之間的多個導線連接，及驗證該多個導線連接；以及                               封裝該多個積體電路晶粒及已驗證的該多個導線成為一系統封裝晶片。
  13. 根據請求項12所述的方法，其中，一重佈層設置於一第一積體電路晶粒上，該重佈層上設置至少一接墊以連接一第二積體電路晶粒，更包括：在該每一接墊下方，設置一二極體於該第一積體電路晶粒中，其中，該二極體的一負極端子電性連接該第一重佈層上的一對應接墊，用以連接該第二積體電路晶粒，該二極體的一正極端子電性連接該第一積體電路晶粒的一第一基底，用以連接一接地點。
  14. 根據請求項13所述的方法，其中，該第一基底是P 型，而該二極體的形成是藉由在該第一基底中形成一N 型區域，以在該P 型基底和該N 型區域間形成一P-N 結(P-N Junction)，其中該N 型區域電性連接該至少一接墊之一對應的接墊。
  15. 根據請求項13所述的方法，其中，在該二極體設置於該第一基底之前，該每個接墊都是浮動接墊，該系統封裝晶片具有多個引腳，該至少一接墊之每個接墊電性連接該多個引腳之一對應的引腳。
  16. 根據請求項13所述的方法，其中，一第二積體電路晶粒經由一隔離層設置於該第一積體電路上，其中，該至少一接墊以鍵結線電性連接該第二積體電路晶粒。
  17. 一種具有多個積體電路晶粒的系統封裝晶片，包括：                  一第一積體電路晶粒和一第二積體電路晶粒，其中，該第一積體電路晶粒包含一第一端子，電性連接該第二積體電路晶粒，該第二積體電路晶粒包含一第一基底；                  其中，該第二積體電路晶粒包含一二極體，該二極體的一正極端子電性連接該第一積體電路晶粒的該第一端子，該二極體的一負極端子電性連接該第二積體電路晶粒的該第一基底，其中，該第一積體電路晶粒的該第一端子利用該第二積體電路晶粒的該二極體作為靜電放電（ESD）的保護。
  18. 根據請求項17所述的系統封裝晶片，其中，該第一基底是P 型，該二極體的形成是藉由在該P 型第一基底中形成一N 型區域，以在該P 型基底和該N 型區域間形成一P-N 結(P-N Junction)，其中該N 型區域電性連接該至該第一積體電路晶粒的該第一端子。
  19. 根據請求項18所述的系統封裝晶片，其中，該第一積體電路晶粒和該第二積體電路晶粒位於兩個不同的電源域。
  20. 根據請求項18所述的系統封裝晶片，其中，該第一積體電路晶粒經由一隔離層被設置於該第二積體電路上，其中，一重佈層設置於該第二積體電路晶粒上，其中，該重佈層包含一第一接墊，用以電性連接該第一積體電路晶粒的該第一端子與該二極體。
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