200908281 九、發明說明： 【發明所屬之技術領域j 本發明係有關於一種多晶片堆聂 於一種可電性隔離已封裝不良曰曰 ' 、，特別係有關 構造及其使用之基板。 片之夕晶片堆疊封裝 【先前技術】 半導體產品在晶圓、晶片、封裝 ^ 階段中必須經過多道的測試步驟，以' 广、’’且接合等不同 用。例如在晶圓等級測試良好的避免不良品被誤 曰)r dn. 3曰片便稱之為已知良好 晶片（Known Good Die，KGD)。妹 ^ ‘、、'而測試的次數越多， 代表製造成本越高。因此，習知 ^ a 進行多晶片封裝製程， 有可能全部或部分是選用未測試曰 . 日曰片。之後再對封裝構 造進行電性測試。由於進行容曰u 多日日片封裝（Multi-Chip Package, MCP)所使用之晶片品質 焉及狀況並不相同。♦ 測試得知封裝成品無法正常運作 * 中咬邛時’即使知道是那一顆 晶片發生故障，由於不良晶片已祜 ^饿封膠密封，所以無法 進行重工修補，其餘功能正常之 <曰曰片只能隨著含有不良 晶片之多晶片封裝構造報廢丟棄 承導致浪費。 請參閱第1圖所示，緣示一插羽 搜習知多晶片堆疊封裝構 造之截面示意圖。該多晶片堆疊封裝構造⑽主要包含— 基板110、-第-晶片120、一第二晶片13〇以及一封膠體 140。該基板110係具有一上表面m、一下表面112、 複數個内接墊1 1 3、1 1 4以及複數個外接墊丨丨5，該些外 接塾1 1 5係形成於該基板11 〇之下表面丨丨2，以接合辉 5 200908281 球1 5 〇。一種習知多晶片堆疊封裝構造i 〇〇係為窗口型球 格陣列封裝並具有背對背堆疊型態，故該基板11〇係更具 囪孔1 1 6以供打線連接之通道。該第一晶片i 2 0 之主動面係可利用黏晶材料黏貼在該基板1〗〇之上 111，複數個第一銲線丨6丨通過該窗孔丨丨6將該第一晶 1 片120之第一銲墊121電性連接至該基板之該些内接墊 U4。該第二晶片130係設置於該第一晶片120上並以複數 (\ 第—銲線162電性連接該第二晶片130之第二銲墊131 與碴些内接墊113。該封膠體14〇形成於該基板n〇之上 1面111之上與該窗孔116内，以密封該些晶片12〇、 以及該些銲線i 6丨、i 6 2。在封裝後進行測試時若 ^ πχ第一晶片1 3 0為不良品，由於已被該封膠體1 4 〇 密封，只能將整個多晶片堆疊封裝構造1〇〇報廢並無法進 行修整。 ^我國專利公告第4〇9330號「可修整式多晶片模組封 〇 凌」揭不一種可修整的多晶片封裝製程，晶片固定基板 ^，並以打線電性連接之銲線電性連接晶片與基板測 試步驟往前調整到封膠步驟之前’當測得有不良晶片 寺，則拉斷連接不良晶片的銲線，以使不良晶片與基板 '〖生、乡巴緣’並在不良晶片之上堆設一已知良好晶片 Rgd)，再第二次打線連接。最後將良好晶片、不 氣 日曰 /、已知良好晶片以封膠體密封。由於測試在封膠 J曰曰片與銲線缺乏保護，容易在測試過程以及機台轉 移搬運過程發生塵粒污染。此外，在進行修整（Repair) 200908281 過程’連接不良晶片的銲線被拉斷， 1 θ有懸空殘線，封 膠時會有接觸其它正常銲線導致短路問題。 【發明内容】 本發明之主要目的係在於提供一種可電性隔離已封 裝不良晶片之U片堆4封裝構造及其使用之基板，基 板之上表面預留有—第二封膠區，其内形成一雷射修整 區’以使被封膠之不良晶片與外接端為電性斷路，以修 整該多晶片堆疊封裝構造’避免因為一個或少數已封膠 晶片發生故障導致整個多晶片堆疊封裝構造的報廢。 本心月之a目的係在於提供一種可電性隔離已封 裝不良晶片之多晶片堆疊封裝構造及其使用之基板能 解決習知在修整過程中因拉斷銲線產生懸空殘線接觸而短 路的問題，並避免測試污染。 本發明的目的及解沐立ϋ i片日5 3 Ρ π鮮决具技術問喊是採用以下技術方 案來實現的。依據本發明，一種可電性隔離已封裝不良 晶片之多晶片堆疊封裝構造主要包含—基板、一第一晶 片、一第二晶片、一第一封膠體以及一第二封膠體。該基板 係具有-上表面與一下表面，其t該上表面係包含一晶片設 置區、-第-封膠區及-第二封料，該基板並具有複數個 導通孔、複數個位於該上表面之内接塾、複數個連接該些導 通孔與該些内接墊之線路以及複數個位於該下表面之外接 勢，該些内接塾係經由該些線路與該些導通孔電性連接至該 些外接墊’其中該第二封膠區係形成有—雷射修整區，用以 顯露該些線路之-區段。該第U係設置於該基板之該晶 7 200908281 片設置區。該第二晶片係設置於該第一晶片上並電性連接該 些内接墊。該第一封膠體係形成於該基板之該第一封膠區， 以密封該第-晶片與該第二晶片。該第二封膠體係形成於該 基板之該第二封膠區’以密封該雷射修整區。另揭示上述 多晶片堆疊封裝構造所使用之基板。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在則述之多晶片堆疊封裝構造中，該雷射修整區係 可由該基板之一防銲層開孔所界定。 在前述之多晶片堆疊封裝構造中，該雷射修整區係 可為長條槽孔。 在引述之夕晶片堆疊封裝構造中該些線路於該雷 射G正區内之顯露區段係能以雷射選擇性切斷，以使該 第二晶片與該些外接墊為電性絕緣。 在則述之多晶片堆疊封裝構造中，該基板係可具有 一窗孔’以供打線通過。 在前述之多晶片堆疊封裝構造中，可另包含有複數 個辉球，其係設置於該些外接墊。 在前述之多晶片堆疊封裝構造中，可另包含有複數 個第—銲線與第二銲線’該些第一銲線係通過該窗孔電 生連接該第一晶片與該基板，該些第二銲線係電性連接 °亥第二晶片至該基板之該些内接墊。 在前述之多晶片堆疊封裝構造中，可另包含有一第 二封膠體，其係填入於該窗孔，以密封該些第—銲線。 8 200908281 在前述之多晶片堆疊封裝構造中，其中該第一晶片 與該第二晶片係可為背對背堆疊。 在前述之多晶片堆疊封裝構造中，該些導通孔係可 排列在该基板之周邊。 在前述之多晶片堆疊封裝構造中，該些内接墊係可 位於該第一封膠區内並鄰近該晶片設置區 在前述之多晶片堆疊封裝構造中，該第一封膠區係 可圍繞《亥Ba片设置區，並且該第二封膠區係圍繞該第一 〇 封膠區。 、 【實施方式】 依據本發明之第一具體實施例，揭示—種可電性隔 離已封裝不良晶片之多晶片堆疊封裝構造，其係為窗口 型球格陣列封裝型態。如第2圖所示，該多晶片堆疊封 裝構造200主要包含一基板21〇、一第—晶片22〇、一第 二晶片230、一第一封膠體241以及—第二封膠體Μ。其 ( 中，5玄第一晶片220與該第二晶片230係堆疊在該基板210 上並以該第一封膠體24 1封膠保護。 請參閱第2及3圖所示’該基板210係具有一上表面 211與一下表面212。其中配合參閱第4圖，該上表面211 係包含一晶片設置區211A、一第一封膠區211B及一第二封 膠區2 11C。如第4圖所示，該晶片設置區2 11A係位於該基 板210之上表面211中央，以晶片之堆疊設置。該第一封膠 區2 Π B係圍繞該晶片設置區2 11 A，作為該第一封膠體2 4 1 於該基板210之覆蓋區（如第2圖所示）。又，該第二封膠區 9 200908281 211C係圍繞該第—封膠區211B’作為該第二封膠體μ於 該基板210之覆蓋區（如第2圖所示）。在本實施例中，該第 二封膠區211C係對齊於該基板21〇之上表面211之四周側 邊緣。 該基板210係可為一種多層印刷電路板◎如第3及4圖 所示，該基板210係具有複數個導通孔213、複數個位於該 上表面211之内接墊214、複數個連接該些導通孔213與該 些内接墊214之線路2 1 5以及複數個位於該下表面212之外 ' 接墊2 1 6。位於該上表面2 11之該些内接墊2 14係經由該些 線路215與該些導通孔213電性連接至該些外接墊217。並 且’ 5亥第一封膠區2 11 C係形成有一雷射修整區2 11D，用以 顯露該些線路2 1 5之一線路顯露區段2 1 5 A(如第4圖所示）， 即是’該些線路2 1 5係經過該雷射修整區2 11D。如第4圖 所示’該雷射修整區211D係可由該基板210之一防銲層開 孔21 7 A所界定（如第3圖所示）。在本實施例中，該雷射修 | . 整區2 11 D係可為長條槽孔。較佳地，該些内接墊2丨4係可 位於δ亥第* —封膠區240内並鄰近该晶片設置區211Α。該些 導通孔2 1 3係可排列在該基板2 1 0之周邊。藉以增加該雷射 修整區2 11D之配置空間，並縮短該些線路2 1 5之配線長度， 以利高頻傳輸。 此外，該基板21 0係可具有一窗孔21 8，以供打線 之銲線通過。該基板2 1 0另可具有複數個位於該下表面 212之内接墊219，其係鄰近於該窗孔218。 如第2圖所示，該第一晶片220係設置於該基板2 1 0之 10 200908281 該晶片設置區21 ΙΑ，該第二晶片230係堆疊設置在該第— 晶片220之上方，以構成多晶片堆疊型態。此外，不受局限 地’更多晶片可堆疊在該第一晶片230的上方（圖未繪出）。 該第一晶片220之一主動面222係設有複數個第一銲塾 221 ;而該第二晶片230之一主動面232係設有複數個第二 銲墊23 1。在本實施例中，該第一晶片220與該第二晶片23〇 係為實質相同之晶片，例如可為具有相同尺寸、相同功能、 相同容量之記憶體晶片。 β玄第一晶片220並電性連接至該基板2 1 0。在本實 施例中，如第2圖所示，可以利用一黏晶層270將該第一 晶片220之主動面222貼設於該基板21〇之該上表面 2 Π，再以複數個打線形成之第一銲線261將該第一晶 片220之第一銲墊221電性連接至該基板21〇之内接墊 219。其中，該些第一銲線261係通過該窗孔218，以電 性連接該第一晶片2 2 0與該基板2 1 0。 設置於該第一晶片220上方之該第二晶片23〇係電性連 接該基板210之該些内接墊214。其中該第一晶片22〇與 該第二晶片230係可為背對背堆疊。該第二晶片23〇之第二 銲墊23 1，可藉由複數個第二銲線262電性連接至該些内接 塾2 14，使5亥第一晶片2 3 〇與該基板21 〇電性互連。 通常以模封、點膠或印刷方式可以形成該第一封膠體 241與該第二封膠體242。如第2及3圖所示，該第一封膠 體241係形成於該基♦反21〇之該第一封膠@ 2ιιβ，以密封 該第一晶片220與該第二晶片23〇,避免外界水氣或污染 11 200908281 物侵入。在本實施例中’該第一封膠體241係更密封該些 第二銲線262 ’但不覆蓋該雷射修整區211D。因此，在該第 一封膠體241形成之後，該第一晶片220、該第二晶片230 與該些第二銲線262能得到足夠的保護，便可進行各種測 試’以偵測該第一晶片22〇與該第二晶片230是否良好或堪 用。如第2及4圖所示，如確定該第二晶片23〇為不良品該 些線路215於該雷射修整區2UD内之線路顯露區段215八 係能以雷射選擇性切斷，以使該第二晶片23〇與該基板2ι〇 之該些外接墊2 1 6為電性絕緣，同時不會有習知拉斷銲線的 修補方式產生懸空殘線接觸而短路與測試污染的問題。該些 外接墊216仍可順利傳輸至該第一晶片22〇，整個多晶片堆 疊封裝構造200仍可使用，不需要報廢，能節省至少一 次的晶圓測試或/及晶圓預燒，以符合低成本的多晶片 封裝測試趨勢。 而該第二封膠體242係形成於該基板210之該第二封膠200908281 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a multi-wafer stack in which a substrate which is electrically isolated from packaged defects, particularly related to the structure and use thereof. Chip Array Wafer Stacking [Prior Art] Semiconductor products must undergo multiple test steps in the wafer, wafer, and package stages, and are used in different ways, such as 'wide', and bonding. For example, the wafer level test is good to avoid defective products being erroneous.) The 曰 dn 曰 film is called Known Good Die (KGD). The more times the sister ^ ‘,,’ is tested, the higher the manufacturing cost. Therefore, it is known that a a multi-chip packaging process, it is possible to use all or part of the untested 曰. The package structure is then electrically tested. The quality and condition of the chips used in the Multi-Chip Package (MCP) are not the same. ♦ Test that the finished package is not working properly* In the case of biting, even if it is known that the wafer has failed, the defective wafer has been sealed and sealed, so it is impossible to repair it. The rest of the function is normal. The film can only be wasted as a multi-chip package structure containing defective wafers is discarded. Please refer to Figure 1 for a cross-sectional view of a multi-wafer stack package structure. The multi-wafer stacked package structure (10) mainly comprises a substrate 110, a first wafer 120, a second wafer 13A, and a gel 140. The substrate 110 has an upper surface m, a lower surface 112, a plurality of inner pads 1 1 3, 1 1 4 and a plurality of external pads 5, and the external 塾1 15 is formed on the substrate 11 The lower surface 丨丨 2 to join the hui 5 200908281 ball 1 5 〇. A conventional multi-wafer stack package structure is a window-type grid array package and has a back-to-back stacking pattern, so that the substrate 11 has a plurality of via holes 1 16 for wiring connection. The active surface of the first wafer i 2 0 can be adhered to the substrate 1 by using a die bonding material, and the plurality of first bonding wires 丨 6 丨 pass the first crystal 1 through the aperture 丨丨 6 The first pad 121 of the 120 is electrically connected to the inner pads U4 of the substrate. The second wafer 130 is disposed on the first wafer 120 and electrically connected to the second pad 131 of the second wafer 130 and the inner pads 113 by a plurality of wires 162. The sealant 14 is electrically connected to the first wafer 120. The germanium is formed on the upper surface 111 of the substrate n and over the window 116 to seal the wafers 12 and the bonding wires i 6 , i 6 2 . The first wafer 130 is a defective product, and since it has been sealed by the sealant, only the entire multi-wafer stack package structure can be scrapped and cannot be trimmed. ^ China Patent Publication No. 4, 9330 The trimmable multi-chip module package is not a trimtable multi-chip package process, the wafer is fixed on the substrate, and the test wire is electrically connected to the wafer and the substrate test step is adjusted to the sealant. Before the step, 'When a bad wafer temple is detected, the bonding wire of the badly connected wafer is broken, so that the defective wafer and the substrate 'study, the rural edge, and a known good wafer Rgd are stacked on the defective wafer. Then connect the cable for the second time. Finally, a good wafer, a non-gas, or a known good wafer is sealed with a sealant. Due to the lack of protection in the sealant J-sheet and the wire bond, it is easy to cause dust pollution during the test process and the transfer process of the machine. In addition, during the repairing process (Repair) 200908281, the solder wire of the defective wafer is broken, and 1 θ has a floating residual line, which may cause a short circuit when contacting the other normal bonding wires. SUMMARY OF THE INVENTION The main object of the present invention is to provide a U-chip stack 4 package structure and a substrate for electrically isolating a packaged defective wafer, and a second sealant region is reserved on the upper surface of the substrate. Forming a laser trimming zone 'to electrically disconnect the poorly bonded wafer and the external terminal to trim the multi-wafer stacked package structure' to avoid the entire multi-wafer stacked package structure due to failure of one or a few of the encapsulated wafers Retirement. The purpose of the present invention is to provide a multi-wafer stack package structure capable of electrically isolating a packaged defective wafer and a substrate for use thereof, which can solve the short circuit caused by the contact of the suspended wire in the trimming process. Problems and avoid testing pollution. The purpose of the present invention and the solution of the Mu Liyi i film day 5 3 Ρ π fresh decision technical call is implemented by the following technical solutions. According to the present invention, a multi-wafer stacked package structure for electrically isolating a packaged defective wafer mainly comprises a substrate, a first wafer, a second wafer, a first encapsulant and a second encapsulant. The substrate has an upper surface and a lower surface, wherein the upper surface comprises a wafer setting region, a first sealing layer and a second sealing material, the substrate has a plurality of via holes, and the plurality of the upper surfaces are located thereon a plurality of in-plane contacts, a plurality of wires connecting the via holes and the inner pads, and a plurality of wires located outside the lower surface, wherein the inner vias are electrically connected to the via holes via the wires To the external pads, wherein the second sealing zone is formed with a laser trimming area for revealing the sections of the lines. The U-th system is disposed on the substrate 7 200908281 chip setting area of the substrate. The second wafer is disposed on the first wafer and electrically connected to the inner pads. The first encapsulation system is formed on the first encapsulation region of the substrate to seal the first wafer and the second wafer. The second encapsulation system is formed in the second encapsulation zone of the substrate to seal the laser trimming zone. Further disclosed is a substrate used in the above multi-wafer stacked package structure. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the multi-wafer stacked package construction described above, the laser trimming region can be defined by one of the solder mask openings of the substrate. In the aforementioned multi-wafer stack package configuration, the laser trimming area may be a long slot. In the wafer stack package construction described, the exposed segments of the lines in the positive region of the laser G can be selectively laser-cut to electrically insulate the second wafer from the external pads. In the multi-wafer stacked package construction described above, the substrate may have a window aperture for passing through the wire. In the foregoing multi-wafer stack package configuration, a plurality of glow balls may be further included, which are disposed on the external pads. In the foregoing multi-wafer stack package structure, a plurality of first bonding wires and second bonding wires may be further included. The first bonding wires electrically connect the first wafer and the substrate through the apertures. The second bonding wire is electrically connected to the inner pads of the second wafer to the substrate. In the foregoing multi-wafer stack package structure, a second encapsulant may be further included in the window to seal the first bonding wires. 8 200908281 In the foregoing multi-wafer stacked package configuration, wherein the first wafer and the second wafer system can be stacked back to back. In the aforementioned multi-wafer stacked package structure, the via holes may be arranged around the periphery of the substrate. In the foregoing multi-wafer stack package configuration, the inner pads may be located in the first encapsulation region and adjacent to the wafer placement region in the foregoing multi-wafer stack package configuration, the first encapsulation region may surround The Hai Ba sheet setting area, and the second seal area surrounds the first sealant area. [Embodiment] According to a first embodiment of the present invention, a multi-wafer stacked package structure capable of electrically isolating a packaged defective wafer is disclosed, which is a window type ball grid array package type. As shown in FIG. 2, the multi-wafer stack package structure 200 mainly includes a substrate 21, a first wafer 22, a second wafer 230, a first sealant 241, and a second sealant. The first wafer 220 and the second wafer 230 are stacked on the substrate 210 and protected by the first sealing body 24 1 . Please refer to FIGS. 2 and 3 'the substrate 210 There is an upper surface 211 and a lower surface 212. Referring to FIG. 4, the upper surface 211 includes a wafer setting area 211A, a first sealing area 211B and a second sealing area 2 11C. As shown, the wafer setting area 2 11A is located in the center of the upper surface 211 of the substrate 210, and is arranged in a stack of wafers. The first sealing area 2 Π B surrounds the wafer setting area 2 11 A as the first sealing The colloid 2 4 1 is in the coverage area of the substrate 210 (as shown in Fig. 2). Further, the second encapsulation area 9 200908281 211C surrounds the first encapsulation area 211B' as the second encapsulant μ. The cover area of the substrate 210 (as shown in Fig. 2). In this embodiment, the second sealant area 211C is aligned with the peripheral side edge of the upper surface 211 of the substrate 21. The substrate 210 can be a kind of Multilayer printed circuit board ◎ As shown in FIGS. 3 and 4, the substrate 210 has a plurality of via holes 213, and a plurality of An inner pad 214 of the upper surface 211, a plurality of wires 2 15 connecting the via holes 213 and the inner pads 214, and a plurality of pads 2 16 outside the lower surface 212. The upper surface is located on the upper surface The inner pads 2 14 of the second layer are electrically connected to the outer pads 217 via the wires 215, and the first sealing region 2 11 C of the 5 sea is formed with a laser trimming. Zone 2 11D, for revealing one of the lines 2 1 5, the line revealing section 2 1 5 A (as shown in FIG. 4 ), that is, the lines 2 1 5 pass through the laser trimming zone 2 11D As shown in Fig. 4, the laser trimming zone 211D can be defined by one of the solder resist layer openings 21 7 A of the substrate 210 (as shown in Fig. 3). In this embodiment, the laser repair is performed. The entire area 2 11 D system may be a long slot. Preferably, the inner pads 2 丨 4 may be located in the Δ 第 — 密封 密封 密封 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 The via holes 2 1 3 can be arranged around the substrate 210 to increase the arrangement space of the laser trimming area 2 11D and shorten the wiring length of the lines 2 15 to facilitate high frequency transmission. The substrate 21 0 may have a window hole 21 8 for the wire bonding wire to pass through. The substrate 210 may further have a plurality of inner pads 219 located on the lower surface 212 adjacent to the window hole. 218. As shown in FIG. 2, the first wafer 220 is disposed on the substrate 2 10 10 200908281, the wafer setting area 21 ΙΑ, and the second wafer 230 is stacked above the first wafer 220 to Form a multi-wafer stack type. Moreover, without limitation, more wafers may be stacked above the first wafer 230 (not shown). One active surface 222 of the first wafer 220 is provided with a plurality of first solder pads 221; and one of the active surfaces 232 of the second wafer 230 is provided with a plurality of second solder pads 23 1 . In this embodiment, the first wafer 220 and the second wafer 23 are substantially identical wafers, and may be, for example, memory chips having the same size, the same function, and the same capacity. The β-first wafer 220 is electrically connected to the substrate 210. In this embodiment, as shown in FIG. 2, the active surface 222 of the first wafer 220 may be pasted on the upper surface 2 of the substrate 21 by a bonding layer 270, and then formed by a plurality of wires. The first bonding wire 261 electrically connects the first pad 221 of the first wafer 220 to the inner pad 219 of the substrate 21 . The first bonding wires 261 pass through the apertures 218 to electrically connect the first wafer 220 and the substrate 210. The second wafer 23 disposed above the first wafer 220 is electrically connected to the inner pads 214 of the substrate 210. The first wafer 22 and the second wafer 230 may be stacked back to back. The second pad 23 1 of the second chip 23 can be electrically connected to the inner pads 2 14 by a plurality of second bonding wires 262 to make the first wafer 2 3 〇 and the substrate 21 Electrical interconnection. The first encapsulant 241 and the second encapsulant 242 are typically formed by molding, dispensing or printing. As shown in the second and third figures, the first encapsulant 241 is formed on the first encapsulant @ 2ιιβ of the base 211 to seal the first wafer 220 and the second wafer 23 to avoid the outside. Water vapor or pollution 11 200908281 Intrusion. In the present embodiment, the first encapsulant 241 further seals the second bonding wires 262' but does not cover the laser trimming region 211D. Therefore, after the first encapsulant 241 is formed, the first wafer 220, the second wafer 230, and the second bonding wires 262 can be sufficiently protected to perform various tests to detect the first wafer. 22〇 is good or usable with the second wafer 230. As shown in FIGS. 2 and 4, if it is determined that the second wafer 23 is defective, the line 215 of the line 215 in the laser trimming area 2UD can be selectively cut by laser. The second wafer 23 is electrically insulated from the external pads 2 16 of the substrate 2 ι, and there is no problem that the repairing method of the conventional broken wire can cause the contact of the suspended residual wire to short-circuit and test the pollution. . The external pads 216 can still be smoothly transferred to the first wafer 22, and the entire multi-wafer stacked package structure 200 can still be used without scrapping, saving at least one wafer test or/and wafer burn-in to meet Low-cost multi-chip package testing trends. The second encapsulant 242 is formed on the second encapsulant of the substrate 210.
區2UC’以密封該雷射修整區2UD’以保護該些線路215 之線路顯露區段215A。此外，如第2圖所示，該多晶片堆 疊封裝構造200可另包含有一第三封膠體243，其係填入於 該窗孔2U’以密封該些第一銲線261。其中，該第三封膠 體243與該第一封膠體241可同時形成且在多晶片測試之 則，該第二封膠體242則形成在多晶片測試之後。 如第2圖所示’在本發明之—具體架構中，該多晶 月堆璧封裝構造200可另包含有複數個鮮球25〇 ,其係設 置於§玄些外接墊216。該多晶片堆疊封裝構造係可藉 12 200908281 由該些銲球2 5 0接合至一外部印刷電路板。 本發明之多晶片堆疊封裝構造可以有不同的封裝型態與 應用。如第5圖所示，另一種可電性隔離已封裝不良晶片 之多晶片堆疊封裝構造3 0 〇係為記憶卡封裝型態，主要 包含一基板310、一第一晶片32〇、一第二晶片33〇、一第 一封膠體341以及一第二封膠體342。該基板31〇係具有一 上表面311與一下表面312。其中配合參閱第6圖，該上表 面3 11係包含一晶片設置區3 i i a以設置該些晶片32〇與 (330、一第一封膠區311B及一第二封膠區311C。該第一封 膠區311B係圍繞該晶片設置區3UA，該第二封膠區3uc 係圍繞該第一封膠區311B並且該第二封膠區3UC之外邊緣 係對齊於該基板310之上表面311之四周側邊緣。該第二封 膠區3 11C係形成有複數個雷射修整區3丨丨〇。 如第5及6圖所不，該基板3丨〇並具有複數個導通孔 313、複數個位於該上表面311之第一内接墊gw與第二内 (；接墊318、複數個連接該些導通孔313與該些内接墊3 14、 3 1 8之線路3 1 5以及複數個位於該下表面3 1 2之外接墊3 1 6。 如第6圖所不，該些第一内接墊314與該些第二内接墊 係經由該些線路3丨5與該些導通孔3丨3電性連接至該些外接 墊316。該些線路315會通過該些雷射修整區3nD，故位於 該第二封膠區311C之該些雷射修整區311D係顯露該些線路 3 1 5之區段3 1 5 A。如第6圖所示，在本實施例中，至少一 ‘ L孔3 1 3係以多條線路3 1 5連接，而使該導通孔3丨3被具 相同功能之該第—内接墊314與第二内接墊318所共用。 13 200908281 該第一晶片320係設置於該基板3 1 0之該晶片設置區 3 Η Α。在本實施例中，該第一晶片32〇之主動面係朝上而遠 離該基板310並具有複數個在主動面邊緣之第一銲墊321。 利用複數個第一銲線35 1電性連接該些第一銲墊32 1與該些 第一内接墊3 1 4。 έ亥第二晶片330係設置於該第一晶片320之上方並電性 連接該些第二内接墊3 1 8。在本實施例中，該第二晶片3 3 〇 之主動面係朝上而遠離該基板310並具有複數個在主動面邊 緣之第二銲墊33 1。利用複數個第二銲線352電性連接該些 第二銲墊331與該些第二内接墊318。此外，在該第一晶片 320與該第二晶片330之間可設有一間隔層360，如膠帶、 含間隔球之液態膠 '覆線膠層、虛晶片（dummy chip)、金屬 片等等，以避免該第二晶片330之背面碰觸該些第一銲線 351 〇 該第一封膠體34 1係形成於該基板3丨〇之該第一封膠區 311B，以密封該第一晶片320與該第二晶片33〇，更可密封 該些第一銲線3 5 1與第二銲線3 52，但顯露該些雷射修整區 3 11D。在該第一封膠體341形成之後，進行電性測試、預燒 測試或其它可靠度測試，當測得第一晶片32〇為不良，可利 用雷射光選擇性照射部分之雷射修整區3UD，以打斷連接 至第一内接墊314之線路315之顯露區段315A，使得該第 一晶片320與該些外接墊3 16為電性絕緣，故該第二晶片33〇 仍可正常運作。反之，當測得第二晶片33〇為不良，則利用 雷射光打斷連接至第二内接墊31S之線路315之顯露區段 14 200908281 ★使彳于該第二晶片330與該些外接墊3 1 6為電性絕緣， 故4 $日日片32G仍可正常運作。藉此可以電性隔離已封裝 不良BB片，不需要報廢整個多晶片堆疊封裝構造3 〇〇。 =外，該第二封膠體342係形成於該基板31〇之該第二 封膠區31 ic ’以密封該些雷射修整區3ud，進而密封該些 線路3 15之顯露區段315A。在本實施例中，該第二封膠體 342係僅包覆該第一封膠體341之側邊，而顯露該第一封膠 體341之頂面。 ' 因此，利用本發明之多晶片堆疊封裝構造3〇〇在修整過 如中不會有拉斷銲線的懸空殘線接觸短路與測試污染的問 題。 、上所述，僅是本發明的較佳實施例而已，並非對 本心月作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單U改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖： 第2圖： 一種習知多晶片堆疊封裝構造之截面示意圖。 依據本發明之第—具體實施例，一種可電性隔 離已封裝不良晶片之多晶片堆疊封裝構造之截面 示意圖。 15 200908281 第3 圖： 依據本發 •明之第一具體實施 例， 該多晶 片堆疊 封裝構造 之基板之截面示意圖 〇 第4 圖： 依據本發 •明之第一具體實施 例， 該多晶 片堆疊 封裝構造 之基板之頂面示意圖 〇 第5 圖： 依據本發 明之第二具體實施‘ 例， 另一種 可電性 隔離已封 裝不良晶片之多晶片 堆疊 封裝構造之截 面示意圖 0 第6 圖： 依據本發 -明之第二具體實施 例’ 該多晶 片堆疊 封裝構造 之基板之頂面示意圖 0 [主 要元件符號說明】 100 多晶 片堆疊封裝構造 110 基板 111上表面 112 下表面 113 内接墊 11 4内接塾 115 外接墊 116 窗孔 120 第一 晶片 121第一銲墊 130 第二 晶片 131第二銲墊 140 第一 封膠體 150銲球 161 第一 銲線 162第二銲線 200 多晶 片堆疊封裝構造 210 基板 211上表面 211A晶片設置區 211E (第- -封膠區 211C第二封膠區 2 11D雷射修整區 212 下表 面 213導通孔 214 内接墊 215 線路 21 5A線路顯露區段 216 外接墊 217 防銲層 217A防銲層開孔 16 200908281 218 窗孔 219 内接墊 220 第一晶片 221 第一銲墊 222 主動面 230 弟二晶片 23 1 第二銲墊 232 主動面 241 第一封膠體 242 第二封膠體 243 第三封膠體 250 鲜球 261 第一銲線 262 第二銲線 270 黏晶層 300 多晶片堆疊封裝構造 3 10 基板 311 上表面 3114 t晶片設置區 3 11 B第一封膠區 311C :第二封膠區 311E >雷射修整區 312 下表面 313 導通孔 314 第一内接墊 3 15 線路 3 15A線路顯露區段 316 外接墊 3 17 防銲層 3 18 第二内接墊 320 第一晶片 321 第一銲墊 330 第二晶片 331 第二銲墊 341 第一封膠體 342 第二封膠體 351 第一銲線 352 第二銲線 360 間隔層 17Zone 2UC' seals the laser trimming zone 2UD' to protect the line revealing section 215A of the lines 215. In addition, as shown in FIG. 2, the multi-wafer stack package structure 200 may further include a third encapsulant 243 which is filled in the window 2U' to seal the first bonding wires 261. Wherein, the third encapsulant 243 and the first encapsulant 241 can be formed simultaneously and in the multi-wafer test, the second encapsulant 242 is formed after the multi-wafer test. As shown in Fig. 2, in the specific architecture of the present invention, the polycrystalline moon-stacked package structure 200 may further include a plurality of fresh balls 25, which are disposed on the outer pads 216. The multi-wafer stacked package structure can be bonded to an external printed circuit board by the solder balls 250 by 12 200908281. The multi-wafer stack package construction of the present invention can have different package types and applications. As shown in FIG. 5, another multi-wafer stack package structure capable of electrically isolating a packaged defective wafer is a memory card package type, and mainly includes a substrate 310, a first wafer 32, and a second. The wafer 33, a first encapsulant 341 and a second encapsulant 342. The substrate 31 has an upper surface 311 and a lower surface 312. Referring to FIG. 6, the upper surface 3 11 includes a wafer setting area 3 iia for disposing the wafers 32 and 330, a first sealing area 311B and a second sealing area 311C. The sealing area 311B surrounds the wafer setting area 3UA, the second sealing area 3uc surrounds the first sealing area 311B, and the outer edge of the second sealing area 3UC is aligned with the upper surface 311 of the substrate 310. The second sealing zone 3 11C is formed with a plurality of laser finishing zones 3 丨丨〇. As shown in FIGS. 5 and 6 , the substrate 3 丨〇 has a plurality of vias 313 and a plurality of a first inner pad gw and a second inner portion of the upper surface 311 (the pad 318, a plurality of wires 3 315 connecting the via holes 313 and the inner pads 3 14 , 3 1 8 and a plurality of The first inner pad 314 and the second inner pads are connected to the through holes by the wires 3 丨 5 and the second inner pads as shown in FIG. 6 . 3丨3 is electrically connected to the external pads 316. The lines 315 pass through the laser trimming areas 3nD, so the laser finishing areas 3 in the second sealing area 311C The 11D system exposes the sections 3 1 5 A of the lines 3 1 5 . As shown in FIG. 6 , in the embodiment, at least one 'L hole 3 1 3 is connected by a plurality of lines 3 1 5 , so that The via hole 3丨3 is shared by the first inner pad 314 and the second inner pad 318 having the same function. 13 200908281 The first chip 320 is disposed in the wafer setting area 3 of the substrate 310. In this embodiment, the active surface of the first wafer 32 is upwardly facing away from the substrate 310 and has a plurality of first pads 321 at the edge of the active surface. The plurality of first bonding wires 35 1 are used. The first solder pads 32 1 and the first inner pads 3 1 4 are connected to the first inner pads 320 and electrically connected to the second inner pads 3 . In the embodiment, the active surface of the second wafer 33 is facing upwards away from the substrate 310 and has a plurality of second pads 33 1 at the edge of the active surface. The plurality of second bonding wires are utilized. 352 is electrically connected to the second pads 331 and the second interconnect pads 318. Further, a spacer layer 360 may be disposed between the first wafer 320 and the second wafer 330. Such as a tape, a liquid glue containing a spacer ball, a dummy layer, a dummy chip, a metal piece, etc., to prevent the back surface of the second wafer 330 from contacting the first bonding wires 351. The first sealing layer 311B is formed on the first sealing layer 311B of the substrate 3 to seal the first wafer 320 and the second wafer 33, and the first bonding wire 3 5 1 and the second sealing layer are sealed. The wire is 3 52, but the laser trimming zone 3 11D is revealed. After the first encapsulant 341 is formed, an electrical test, a burn-in test or other reliability test is performed. When the first wafer 32 is measured as defective, the laser trimming zone 3UD can be selectively irradiated with the laser light. The first wafer 320 is electrically insulated from the external pads 3 16 by breaking the exposed portion 315A of the line 315 connected to the first interconnect pad 314, so that the second wafer 33 is still functioning normally. On the contrary, when the second wafer 33 is detected as defective, the exposed portion 14 of the line 315 connected to the second internal pad 31S is interrupted by the laser light, and the second wafer 330 and the external pads are placed on the second wafer 330. 3 1 6 is electrically insulated, so the 4 $ 日 32G can still operate normally. Thereby, it is possible to electrically isolate the packaged bad BB piece without scrapping the entire multi-wafer stack package structure. In addition, the second encapsulant 342 is formed on the second encapsulation area 31 ic ' of the substrate 31 to seal the laser trimming areas 3ud, thereby sealing the exposed sections 315A of the lines 3 15 . In this embodiment, the second encapsulant 342 covers only the side of the first encapsulant 341 to expose the top surface of the first encapsulant 341. Therefore, with the multi-wafer stack package structure 3 of the present invention, there is no problem that the dummy stubs of the wire bond wire are not short-circuited and tested for contamination during trimming. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple U change, equivalent change and modification are still within the scope of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 : FIG. 2 is a schematic cross-sectional view showing a conventional multi-wafer stacked package structure. In accordance with a first embodiment of the present invention, a cross-sectional view of a multi-wafer stacked package structure that electrically isolates a packaged defective wafer. 15 200908281 FIG. 3 is a cross-sectional view of a substrate of the multi-wafer stacked package structure according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view of the multi-wafer stacked package according to the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a multi-wafer stacked package structure capable of electrically isolating a packaged defective wafer according to a second embodiment of the present invention. FIG. 6: According to the present invention - The second embodiment of the present invention is a top view of the substrate of the multi-wafer stacked package structure. [Main element symbol description] 100 multi-chip stacked package structure 110 substrate 111 upper surface 112 lower surface 113 inner pad 11 4 inscribed 塾 115 External pad 116 window 120 first wafer 121 first pad 130 second wafer 131 second pad 140 first gel 150 solder ball 161 first bonding wire 162 second bonding wire 200 multi-chip stacked package structure 210 substrate 211 Upper surface 211A wafer setting area 211E (first - - sealing area 211C second sealant zone 2 11D laser trimming zone 212 lower surface 213 via 214 inner pad 215 line 21 5A line exposed section 216 external pad 217 solder mask 217A solder mask opening 16 200908281 218 window hole 219 Pad 220 First wafer 221 First pad 222 Active surface 230 Second chip 23 1 Second pad 232 Active surface 241 First gel 242 Second seal 243 Third seal 250 Fresh ball 261 First wire 262 second bonding wire 270 adhesive layer 300 multi-chip stacked package structure 3 10 substrate 311 upper surface 3114 t wafer setting area 3 11 B first sealing area 311C: second sealing area 311E > laser finishing area 312 Surface 313 via 314 first inner pad 3 15 line 3 15A line exposed section 316 external pad 3 17 solder mask 3 18 second inner pad 320 first wafer 321 first pad 330 second wafer 331 second Pad 341 first gel 342 second seal 351 first bond wire 352 second bond wire 360 spacer layer 17