TWI344202B - Multi-chip stacked package enabling to electrically isolate an encapsulated fail chip and a substrate utilized for the package - Google Patents

Description

1344202, IX. Description of the Invention: The present invention relates to a multi-wafer stacked package, and more particularly to a multi-wafer stacked package structure and a substrate for electrically isolating a packaged defective wafer. [Prior Art] Semiconductor products must undergo multiple test steps at different stages of wafer, wafer, package, and module bonding to avoid misuse of defective products. For example, a wafer that is well tested at the wafer level is called a Known Good Die (KGD). However, the more times the test is performed, the higher the manufacturing cost. Therefore, it is conventional to carry out a multi-wafer packaging process, and it is possible to select all or part of the untested wafer. The package structure is then electrically tested. The quality and condition of the chips used in the Multi-Chip Package (MCP) are not the same. When the test knows that the packaged product is not working properly, even if it is known that the wafer is faulty, since the defective wafer has been sealed by the sealant, it cannot be repaired by rework. The remaining normal functions of the wafer can only be accompanied by the number of defective wafers. The chip package structure is discarded and discarded, resulting in waste. Referring to Figure 1, a schematic diagram of a conventional multi-wafer stacked package structure is shown. The multi-wafer stack package structure 100 mainly includes a substrate 110, a first wafer 120, a second wafer 130, and a gel 140. The substrate 110 has an upper surface 111, a lower surface 112, a plurality of internal pads 1 1 3, 1 1 4 and a plurality of external pads 11 5 formed on the substrate 1 1 0 The lower surface 1 1 2 is joined to weld 5 balls 150. The conventional multi-wafer stacked package structure (10) is a window type ball column package and has a back-to-back stacked type. i The 〇 system has a window 1 1 6 for the connection of the wire connection. The active surface of the first wafer t 2 可 can be adhered to the upper surface of the substrate by using a die bonding material. 1 1 1 'a plurality of first bonding wires 1 61 pass through the window & ii 6 to the first crystal 20 The first fresh electrode 1 2 1 is electrically connected to the inner pads 114 of the substrate u. The second wafer 13 is disposed on the first wafer 12 and electrically connected to the second wafer 1 62 by a plurality of solder wires 1 62. The second pads 1 3 i : the inner pads 13. The encapsulant 丨4〇 is formed on the substrate (1) above the two sides (1) and the window hole 6 to seal the wafers 120, 0 and the bonding wires i 6 ij 62. When the test is performed after encapsulation, if the second wafer 丨3 is defective, the entire multi-wafer stack can only be trimmed because it has been sealed by the sealant. Qiu package structure _ scrap and can not enter China's patent announcement No. 4 0 9 3 3 0 "opening technology ... dream, e $ trimmed multi-chip module seal," not a kind of repairable more, *, Guang The manufacturing process, the wafer fixed substrate wave is electrically connected by wire bonding, and the test is run. 4 11 The wafer and the substrate are connected. When measuring, the glue is 7 ' 'When the defective wafer is measured, the solder of the badly connected wafer is broken. The wire, the electrical property, causes the bad B-day film to be insulated from the substrate, and is placed on the defective wafer (KGn, * is stacked with a known good wafer), and the second wire is connected. The most good wafers with P 4 years, bad crystals, and α good wafers were sealed with a sealant. ^ Before, a κ life force seal. Due to the transfer of the test in the sealer 勿« Do not carry out dust pollution during the test process and the transfer of the machine. In addition, during the repair process (Repair) 1344202. The bonding wire of the poorly connected wafer is broken, and there is a problem that the other normal bonding wires may cause a short circuit when the residual wire is suspended. [Content of the Invention]

The main object of the present invention is to provide a multi-wafer stack package structure capable of electrically isolating a packaged defective wafer and a substrate therefor, and a second sealant region is formed on the upper surface of the substrate, and a laser is formed therein. (4) Zones to electrically disconnect the poorly bonded wafers and the external terminals to trim the multi-wafer stack package structure 'avoiding the end of the entire multi-wafer (4) package structure due to failure of one or a few of the packaged wafers. The second objective of the present invention is to provide a multi-wafer stack package structure capable of electrically isolating a packaged defective wafer and a substrate for use thereof, which can solve the problem of short-circuiting due to the contact of the suspended wire by the pull-off residual line during the trimming process. And avoid testing for contamination. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-wafer stack package structure capable of electrically isolating a packaged defective wafer mainly comprises a substrate, a first sheet, a second wafer, a - a sealant, and a second seal. The base has: an upper surface and a lower surface, wherein the upper surface comprises a wafer setting region, a first sealing layer region, and a second sealing region, the substrate having a plurality of via holes and a plurality of The inner surface of the upper surface, the plurality of wires connecting the via holes and the inner pads, and the plurality of wires located outside the lower surface are electrically connected to the via holes via the wires and the via holes Sexually connected to the external rafts', which causes the second sealed area to form a laser trimming area for revealing the sections of the lines. The first wafer is disposed on the substrate 7 1344202 sheet setting region. The first - some innings. A sheet is disposed on the first wafer and electrically connected to seal the 'sealanting system' formed on the first sealing region of the substrate, and the wafer and the second wafer. The second encapsulation system is formed on the second sealing glue & ' of the substrate to seal the laser trimming area. The substrate used in the stacking and packaging structure of the above-mentioned 曰 a 曰 sheet is further disclosed. And to solve its technical problems can be further realized by the following technical measures.

In the ten-month-old 1J-34 wafer stack package structure, the laser trimming region can be defined by the solder mask opening of the germanium substrate. In the aforementioned multi-wafer stack package configuration, the laser trimming area may be a long slot. In the multi-wafer stack package configuration described above, the exposed segments of the lines in the laser trim region are laser-selectively cut to electrically insulate the second wafer from the external pads.

In the aforementioned multi-wafer stacked package configuration, the substrate may have a window for passing the wire. In the foregoing multi-wafer stack package configuration, a plurality of solder balls may be further included, which are disposed on the external pads. In the foregoing multi-wafer stack package structure, a plurality of first bonding wires and a second bonding wire may be further included, and the bonding wires are electrically connected to the first wafer and the substrate through the window holes. The second bonding wire electrically connects the second wafer to the inner pads of the substrate. In the foregoing multi-wafer stack package structure, a third sealant may be further included in the window to seal the first bonding wires.

S 1344202. In the foregoing multi-wafer stacked package construction, wherein the first wafer and the second wafer system can be stacked back to back. In the aforementioned multi-wafer stacked package structure, the via holes may be arranged around the periphery of the substrate. In the multi-wafer stack package construction described above, the inner pads may be located adjacent to the first seal region and adjacent to the wafer set region. In the multi-wafer stacked package configuration described above, the first encapsulation zone φ can surround the wafer placement zone and the second encapsulation zone surrounds the first encapsulation zone. [Embodiment] According to a first embodiment of the present invention, a multi-wafer stack package structure capable of electrically isolating a packaged defective wafer is disclosed, which is a window type ball grid array package type. As shown in FIG. 2, the multi-wafer stack package structure 200 mainly includes a substrate 210, a first wafer 220, a second wafer 230, a first encapsulant 241, and a second encapsulant 242. The first crystal 220 and the second wafer 230 are stacked on the substrate 210 and protected by the first encapsulant 24 1 . Referring to Figures 2 and 3, the substrate 210 has an upper surface 211 and a lower surface 212. Referring to FIG. 4, the upper surface 211 includes a wafer setting area 211A, a first sealing area 211B and a second sealing area 2 1 1 C. As shown in Fig. 4, the wafer setting area 2a is located at the center of the upper surface 2 of the substrate 210, and is arranged in a stack of wafers. The first encapsulation region 2 11 B surrounds the wafer placement region 211 A as a coverage area of the first encapsulant 24 1 (shown in FIG. 2 ). Moreover, the second encapsulation area 9 1344202 is disposed on the wafer setting area 2 11 A, and the second wafer 23 is stacked on top of the first μ sheet 220 to form a multi-wafer stack tangential state. Moreover, without limitation, more wafers may be stacked above the second wafer 23' (not shown). The active surface 222 of the first wafer 220 is provided with a plurality of first pads 221; and the active surface 232 of the second wafer 230 is provided with a plurality of second pads 23, in this embodiment, The first wafer 22 is substantially the same wafer as the second wafer, and may be, for example, a memory wafer having the same size, the same function, and the same capacity. The first wafer 220 is electrically connected to the substrate 2 . In the present embodiment, as shown in FIG. 2, the active surface 222 of the first wafer 220 may be pasted on the upper surface 2 of the substrate 2 by a bonding layer 27, and then a plurality of wires may be used. Forming the first bonding wire 261 to the first crystal. — — — — — — —

The inner pad 2 1 8 is electrically connected to the inner pad 214. Wherein the first wafer 22 is stacked back to back. The second plurality of second bonding wires 262 of the second wafer 23 are electrically connected to the inner connecting pieces 230 and electrically connected to the substrate 21 . ...the chess piece, the dispensing or the printing method can form the second 241 and the second one

- The sealant "'I is small, the first sealant' seal area 2 11Β, to seal to avoid external moisture or pollution i 11 1344202*. In this embodiment, the first sealant 241 is more sealed. The second bonding wires 262, but not covering the laser trimming regions 211D. Therefore, after the first bonding body 241 is formed, the first wafer 220, the second wafer 230, and the second bonding wires 262 can With sufficient protection, various tests can be performed to detect whether the first wafer 220 and the second wafer 230 are good or usable. As shown in Figures 2 and 4, if the second wafer 230 is determined to be defective The

The line 215 is in the laser trimming area 21 1D, and the line exposure section 21 5A is laser-selectively cut off to make the second wafer 230 and the substrate 2 j 外 些 外 外 2 1 6 is electrical insulation, and there is no problem that the repair method of the conventional broken wire can cause the contact of the suspended residual wire and short circuit and test pollution. The external pads 216 can still be smoothly transferred to the first wafer 22, and the entire multi-wafer stack package structure 200 can still be used, and does not need to be scrapped, which can save at least one wafer test or/and wafer burn-in. To meet the trend of low-cost multi-chip package testing. The second brother of the second brother, 2UC, is sealed to seal the laser finishing area 2UD to protect the line 215A of the line. In addition, as shown in FIG. 2, the multi-slice stack package structure 2〇0 may further include a third sealant (4) which is filled in the window hole 218 to seal the first fresh lines 26 Wherein, the third sealant 243 and the first sealant 241 can be opened simultaneously; 忐b B u _ J丨J矸 is formed and after the multi-wafer test, the second sealant 242 is formed after the multi-wafer test . As shown in Fig. 2, in the specific structure of the present invention, the polycrystalline wafer stacked package structure can be placed in the external 塾 216. Two solder balls 250' are provided (four) 216 4 multi-chip stacked package structure 2 can be joined by j 12 1344202 from the solder balls 250 to an external printed circuit board. The multi-wafer stack package construction of the present invention can have different package types and applications. As shown in FIG. 5, another multi-wafer stack package structure 300 that electrically isolates a packaged defective chip is a memory card package type, and mainly includes a substrate 310, a first wafer 320, and a second wafer 330. a first sealant 34 1 and a second sealant 342. The substrate 3 1 has an upper surface 311 and a lower surface 312. Referring to FIG. 6 , the upper surface 3 11 includes a wafer setting area 3 1 1 a for disposing the wafers 3 2 〇 and 330, a first sealing area 3 ι 1 Β and a second sealing area 3 丨 1 (: The first sealant zone 3 1 1 B surrounds the wafer set area 3 1丨a, the second sealant zone 3 nc surrounds the first sealant zone 3 1 1 B and the second sealant The outer edge of the region 3 1 1 C is aligned with the peripheral side edge of the upper surface 3 11 of the substrate 310. The second sealing region 3 11C is formed with a plurality of laser trimming regions 3 11 D. And the substrate 3 has a plurality of vias 313, a plurality of first inner pads 314 and second inner pads 318 on the upper surface 311, and a plurality of the vias 313 are connected The lines 3 1 5 of the inner pads 314, 318 and the plurality of pads 3 16 outside the lower surface 3 1 2 . As shown in the figure, the first inner pads 314 and the The second inner pad 318 is electrically connected to the external vias 316 via the wires 315 and the vias 316. The wires 315 pass through the laser trimming regions 311D. Second seal area 3 11 The laser trimming zone 3 1 1 D of C exposes one of the sections 315 of the lines 315. As shown in the figure, in the embodiment, at least one of the vias 3 13 is connected by a plurality of lines 3 5 is connected, and the via hole 3丨3 is shared by the first inner pad 314 and the second inner pad 318 having the same function. 13 4 1344202 The first chip 320 is disposed on the substrate 3 In the present embodiment, the active surface of the first wafer 320 faces upward and away from the substrate 310 and has a plurality of first pads 32 at the edges of the active surface. The bonding wire 351 is electrically connected to the first bonding pads 321 and the first internal pads 314. The second wafer 330 is disposed above the first wafer 320 and electrically connected to the second inner pads 3 In the present embodiment, the active surface of the second wafer 33 is facing upwards away from the substrate 310 and has a plurality of second pads 331 at the edge of the active surface. A plurality of second bonding wires 352 are utilized. The second solder pads 33 1 and the second inner pads 3 丨 8 are electrically connected. Further, 'the first wafer 320 and the second wafer 33 are connected to each other. There may be a spacer layer 36〇, such as a tape 'a liquid ball glue, a glue layer, a dummy wafer, a metal sheet, etc., to avoid touching the back surface of the second wafer 33. The first bonding wire 35 is formed on the first sealing region 3 11 B of the substrate 31 to seal the first wafer 320 and the second wafer 330, and the sealing portion is sealed. The first bonding wire 351 and the second bonding wire 352, but the laser finishing regions 311D are exposed. After the first encapsulant 341 is formed, an electrical test, a burn-in test or other reliability test is performed. When the first wafer 320 is measured to be defective, a portion of the laser trimming region 311D may be selectively irradiated with laser light to The exposed portion 3丨5A of the line 3丨5 connected to the first inner pad 3 14 is interrupted, so that the first wafer 320 is electrically insulated from the external pads 3 16 , so the second wafer 33 remains Can work positively. On the other hand, if the U33G is bad, the laser is used to break the exposed section of the line 3丨5 connected to the second inner (four) 318.

A 14 1344202 3 1 5 A, the second wafer 330 is electrically insulated from the external pads 3 16 , so that the first wafer 320 can still operate normally. Thereby, it is possible to electrically isolate the packaged defective wafers' without having to scrap the entire multi-wafer stack package structure. In addition, the second encapsulant 342 is formed on the second encapsulation area 311C′ of the substrate 310 to seal the laser trimming regions 311D, thereby sealing the exposed sections 3丨5 of the lines 3 1 5 . a. In this embodiment, the second encapsulant 342 covers only the side of the first encapsulant 341 to expose the top surface of the first encapsulant 341. Therefore, the multi-wafer stacked package structure 3 of the present invention does not have the problem of contact short-circuiting and test contamination of the suspended wire of the broken wire in the trimming process. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is intended to be The above-disclosed technical content makes a slight modification or modification to the equivalent variation of the embodiment of the present invention, but does not depart from the technical solution of the present invention. Any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the present invention. 'All still fall within the scope of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional multi-wafer stacked package structure. Figure 2 is a cross-sectional view showing a multi-wafer stacked package structure for electrically isolating a packaged defective wafer in accordance with a first embodiment of the present invention.

A 15 1344202 Fig. 3 is a schematic cross-sectional view of a substrate of the multi-wafer stacked package structure in accordance with a first embodiment of the present invention. Figure 4 is a top plan view of a substrate of the multi-wafer stacked package structure in accordance with a first embodiment of the present invention. Fig. 5 is a perspective view showing another embodiment of a multi-wafer stacked package structure for electrically isolating a packaged defective wafer in accordance with a second embodiment of the present invention. Figure 6 is a top plan view of a substrate of the multi-wafer stacked package structure in accordance with a second embodiment of the present invention. [Main component symbol description] 100 multi-chip stacked package structure 110 substrate 111 upper surface 112 lower surface 113 inner pad 114 inner pad 115 external pad 116 window 120 first wafer 1 21 first fresh 塾 130 苐 two wafer 1 3 1 second bonding pad 140 first colloid 1 50 fresh ball 161 first bonding wire 162 second bonding wire 200 multi wafer stacking package structure 210 substrate 2 11 upper surface 21 1A wafer setting area 2 11 B first sealing area 2 11 C second encapsulation zone 2 11 D laser trimming zone 212 lower surface 213 via 214 inner pad 215 line 215A line exposed section 216 external pad 217 solder mask 217A solder mask opening 16 1344202

300 multi-chip stacked package structure 310 substrate 311 upper surface 3 11 B first encapsulation area 3 11 C second encapsulation area 315A line exposure section 316 external pad 2 1 8 aperture 220 first wafer 230 second wafer 241 A colloidal 250 solder ball 270 adhesive layer 312 lower surface 315 line 3 1 7 solder mask 320 first wafer 330 second wafer 341 first encapsulant 3 5 1 first bonding wire 360 spacer layer 2 1 9 inner pad 221 first pad 23 1 second pad 242 second encapsulant 261 first bonding wire 3 13 via 318 second inner pad 321 first pad 331 second pad 342 second encapsulant 352 second welding Line 222 active surface 232 active surface 243 third sealing body 262 second bonding wire 311A wafer setting area 3 11 D laser trimming area 314 first inner pad

A 17

Claims (1)

Patent application scope: 1. A multi-wafer stack package structure capable of electrically isolating a packaged defective wafer, comprising: a substrate having an upper surface and an upper surface, wherein the upper surface includes a wafer setting area, a first encapsulation zone and a second encapsulation zone, the substrate has a plurality of via holes, a plurality of inner pads on the upper surface, a plurality of wires connecting the via holes and the inner pads, and a plurality of outer pads on the lower surface, the inner connecting wires are electrically connected to the outer connecting holes via the wires and the outer connecting holes, wherein the second sealing region is formed with a laser trimming area, The first wafer is disposed in the wafer setting area of the substrate; a second wafer is disposed on the first wafer and electrically connected to the inner pads a first sealant formed on the first sealant region of the substrate to seal the first wafer and the second wafer; and a second sealant formed on the substrate Second sealing area to seal the mine Shoot the entire area. [2] The multi-wafer stacked package structure of the electrically-insulable packaged non-produced wafer, as described in claim 1, wherein the laser trimming zone is defined by a solder mask opening of the substrate. ^ 3, such as applying for a patented ribs ^ ^ χ J target enclosure 1 described in the electrical isolation has been sealed non-product multi-chip stacked package structure, wherein the laser trimming system is: 1344202 4, such as application The multi-wafer stack package structure of the electrically insulating isolated packaged defective wafer according to the first aspect of the invention, wherein the exposed sections of the lines in the laser trimming area are laser-selectively cut so that the The second wafer is electrically insulated from the external pads. 5. The multi-wafer stacked package structure of the electrically quarantinable packaged defective wafer according to claim 1, wherein the substrate has a window for passing the wire. 6. The multi-wafer stack package structure for electrically isolating a packaged defective wafer according to claim 1 or 5, further comprising a plurality of solder balls disposed on the external 塾β7, as in the application The multi-wafer stacked package structure of the electrically-insulable sealed defective wafer described in the fifth aspect of the patent scope further includes a plurality of first bonding wires and a second bonding wire, and the first bonding wires pass through the window holes The first wafer is electrically connected to the substrate, and the second bonding wires are electrically connected to the second wafer to the inner vias of the substrate. 8 'A multi-wafer stack package structure for electrically isolating a packaged defective wafer as described in claim 7 of the patent application, further comprising a third sealant filled in the window to seal the first Welding wire. 9. The multi-wafer stacked package structure of the electrically quarantinable packaged defective wafer of claim 8, wherein the first wafer and the second wafer are stacked back to back. 10. The multi-wafer stack package structure of the electrically-insulable packaged defective wafer according to claim 1, wherein the via holes are arranged around the substrate. The 344202 u, the multi-wafer stack package structure of the electrically-insulable packaged defective wafer according to claim 1, wherein the inner pads are located in the first seal region and adjacent to the wafer Area. 1 . The multi-wafer stack package structure of electrically insulating the packaged defective wafer according to claim 1, wherein the first sealant region surrounds the wafer setup region, and the second seal region is Around the first seal area. 13. A multi-wafer stacked package structure for electrically isolating a packaged defective wafer. The substrate has an upper surface and a lower surface, wherein the upper surface includes a wafer setting region, a first sealing region, and a second encapsulating area 'the substrate has a plurality of via holes, a plurality of interconnects located on the upper surface, a plurality of lines connecting the via holes and the inner pads, and a plurality of the lower surfaces The external pads are electrically connected to the external contacts via the wires and the via holes, wherein the second sealing region is formed with a laser trimming region for revealing the wires One section. 14. The substrate of the multi-wafer stacked package structure of electrically insulating the packaged defective wafer as described in claim 13 wherein the laser trimming zone is defined by a solder mask opening of the substrate. A substrate for electrically isolating a multi-wafer stacked package structure of a packaged defective wafer, wherein the laser trimming region is a long slot, as described in claim 13 of the patent application. 10. A substrate for electrically isolating a multi-wafer stacked package structure of a packaged defective wafer as described in claim 5, wherein the substrate holder 20 has a window opening for passing the wire. The substrate of the solar cell of the patent scope s 1 3 can be electrically isolated from the substrate of the defective package, wherein the via holes are arranged around the substrate. The substrate of the multi-wafer stack package structure for electrically isolating the packaged defective cymbal according to claim 13, wherein the inner pads are located in the first seal region and adjacent to the wafer Set the area. 19 such as Shen. The substrate of the multi-wafer stack package structure of the electrically-insulated packaged defective wafer according to Item 13 of the patent scope of the present invention, wherein the first sealant region surrounds the sheet set region, and the second sealant region surrounds the substrate The first rubber area. A 21